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bhyve: clean up trailing whitespaces

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Clean up trailing whitespaces. No functional changes.

Reviewed by: jhb
Differential Revision: https://reviews.freebsd.org/D33681
This commit is contained in:
Toomas Soome 2021-12-26 09:52:38 +02:00
parent 62ed2d0152
commit c2fa905cf6
34 changed files with 130 additions and 130 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
usr.sbin/bhyve/acpi.c
View File

@ -77,7 +77,7 @@ __FBSDID("$FreeBSD$");
#include "vmgenc.h"
/*
* Define the base address of the ACPI tables, the sizes of some tables,
* Define the base address of the ACPI tables, the sizes of some tables,
* and the offsets to the individual tables,
*/
#define BHYVE_ACPI_BASE 0xf2400
@ -447,7 +447,7 @@ basl_fwrite_fadt(FILE *fp)
EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
PM1A_EVT_ADDR);
EFPRINTF(fp, "\n");
EFPRINTF(fp,
"[0012]\t\tPM1B Event Block : [Generic Address Structure]\n");
EFPRINTF(fp, "[0001]\t\tSpace ID : 01 [SystemIO]\n");
@ -642,7 +642,7 @@ basl_fwrite_facs(FILE *fp)
EFFLUSH(fp);
return (0);
err_exit:
return (errno);
}
@ -842,7 +842,7 @@ basl_load(struct vmctx *ctx, int fd, uint64_t off)
if (fstat(fd, &sb) < 0)
return (errno);
gaddr = paddr_guest2host(ctx, basl_acpi_base + off, sb.st_size);
if (gaddr == NULL)
return (EFAULT);
@ -876,7 +876,7 @@ basl_compile(struct vmctx *ctx, int (*fwrite_section)(FILE *), uint64_t offset)
fmt = basl_verbose_iasl ?
"%s -p %s %s" :
"/bin/sh -c \"%s -p %s %s\" 1> /dev/null";
snprintf(iaslbuf, sizeof(iaslbuf),
fmt,
BHYVE_ASL_COMPILER,
@ -907,7 +907,7 @@ basl_make_templates(void)
err = 0;
/*
*
*
*/
if ((tmpdir = getenv("BHYVE_TMPDIR")) == NULL || *tmpdir == '\0' ||
(tmpdir = getenv("TMPDIR")) == NULL || *tmpdir == '\0') {

2
usr.sbin/bhyve/audio.h
View File

@ -28,7 +28,7 @@
* $FreeBSD$
*/
#ifndef _AUDIO_EMUL_H_
#ifndef _AUDIO_EMUL_H_
#define _AUDIO_EMUL_H_
#include <sys/types.h>

10
usr.sbin/bhyve/bhyverun.c
View File

@ -212,7 +212,7 @@ struct bhyvestats {
struct mt_vmm_info {
pthread_t mt_thr;
struct vmctx *mt_ctx;
int mt_vcpu;
int mt_vcpu;
} mt_vmm_info[VM_MAXCPU];
static cpuset_t *vcpumap[VM_MAXCPU] = { NULL };
@ -1066,7 +1066,7 @@ do_open(const char *vmname)
bool reinit, romboot;
#ifndef WITHOUT_CAPSICUM
cap_rights_t rights;
const cap_ioctl_t *cmds;
const cap_ioctl_t *cmds;
size_t ncmds;
#endif
@ -1109,7 +1109,7 @@ do_open(const char *vmname)
#ifndef WITHOUT_CAPSICUM
cap_rights_init(&rights, CAP_IOCTL, CAP_MMAP_RW);
if (caph_rights_limit(vm_get_device_fd(ctx), &rights) == -1)
if (caph_rights_limit(vm_get_device_fd(ctx), &rights) == -1)
errx(EX_OSERR, "Unable to apply rights for sandbox");
vm_get_ioctls(&ncmds);
cmds = vm_get_ioctls(NULL);
@ -1119,7 +1119,7 @@ do_open(const char *vmname)
errx(EX_OSERR, "Unable to apply rights for sandbox");
free((cap_ioctl_t *)cmds);
#endif
if (reinit) {
error = vm_reinit(ctx);
if (error) {
@ -1354,7 +1354,7 @@ main(int argc, char *argv[])
set_config_bool("x86.mptable", false);
break;
case 'h':
usage(0);
usage(0);
default:
usage(1);
}

2
usr.sbin/bhyve/block_if.c
View File

@ -120,7 +120,7 @@ struct blockif_ctxt {
struct mevent *bc_resize_event;
/* Request elements and free/pending/busy queues */
TAILQ_HEAD(, blockif_elem) bc_freeq;
TAILQ_HEAD(, blockif_elem) bc_freeq;
TAILQ_HEAD(, blockif_elem) bc_pendq;
TAILQ_HEAD(, blockif_elem) bc_busyq;
struct blockif_elem bc_reqs[BLOCKIF_MAXREQ];

2
usr.sbin/bhyve/config.c
View File

@ -221,7 +221,7 @@ _expand_config_value(const char *value, int depth)
fputc('%', valfp);
vp++;
break;
}
}
if (vp[1] != '(' || vp[2] == '\0')
cp = NULL;
else

2
usr.sbin/bhyve/config.h
View File

@ -45,7 +45,7 @@
* Configuration variables are stored in a tree. The full path of a
* variable is specified as a dot-separated name similar to sysctl(8)
* OIDs.
*/
*/
/*
* Fetches the value of a configuration variable. If the "raw" value

2
usr.sbin/bhyve/fwctl.c
View File

@ -98,7 +98,7 @@ fwctl_send_rest(uint32_t *data, size_t len)
int i;
cdata = (uint8_t *) data;
u.w = 0;
u.w = 0;
for (i = 0, u.w = 0; i < len; i++)
u.c[i] = *cdata++;

26
usr.sbin/bhyve/hda_reg.h
View File

@ -668,7 +668,7 @@
/* Channel Count Control */
#define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d
#define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
#define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
#define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \
(HDA_CMD_12BIT((cad), (nid), \
@ -677,20 +677,20 @@
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload)))
#define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
#define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
#define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg)))
#define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
#define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
#define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_GET_HDMI_ELDD, (off)))
#define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
#define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
#define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
#define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
#define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \
(HDA_CMD_12BIT((cad), (nid), \
@ -699,8 +699,8 @@
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload)))
#define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
#define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
#define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
#define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
#define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \
(HDA_CMD_12BIT((cad), (nid), \
@ -709,8 +709,8 @@
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload)))
#define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
#define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
#define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
#define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
#define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \
(HDA_CMD_12BIT((cad), (nid), \
@ -719,11 +719,11 @@
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload)))
#define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
#define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
#define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
#define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
#define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
#define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
#define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
#define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
#define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \
(HDA_CMD_12BIT((cad), (nid), \

4
usr.sbin/bhyve/inout.c
View File

@ -86,11 +86,11 @@ default_inout(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
return (0);
}
static void
static void
register_default_iohandler(int start, int size)
{
struct inout_port iop;
VERIFY_IOPORT(start, size);
bzero(&iop, sizeof(iop));

2
usr.sbin/bhyve/inout.h
View File

@ -70,7 +70,7 @@ struct inout_port {
0 \
}; \
DATA_SET(inout_port_set, __CONCAT(__inout_port, __LINE__))
void init_inout(void);
int emulate_inout(struct vmctx *, int vcpu, struct vm_exit *vmexit);
int register_inout(struct inout_port *iop);

16
usr.sbin/bhyve/mem.c
View File

@ -96,7 +96,7 @@ mmio_rb_lookup(struct mmio_rb_tree *rbt, uint64_t addr,
*entry = res;
return (0);
}
return (ENOENT);
}
@ -172,7 +172,7 @@ access_memory(struct vmctx *ctx, int vcpu, uint64_t paddr, mem_cb_t *cb,
{
struct mmio_rb_range *entry;
int err, perror, immutable;
pthread_rwlock_rdlock(&mmio_rwlock);
/*
* First check the per-vCPU cache
@ -187,7 +187,7 @@ access_memory(struct vmctx *ctx, int vcpu, uint64_t paddr, mem_cb_t *cb,
if (entry == NULL) {
if (mmio_rb_lookup(&mmio_rb_root, paddr, &entry) == 0) {
/* Update the per-vCPU cache */
mmio_hint[vcpu] = entry;
mmio_hint[vcpu] = entry;
} else if (mmio_rb_lookup(&mmio_rb_fallback, paddr, &entry)) {
perror = pthread_rwlock_unlock(&mmio_rwlock);
assert(perror == 0);
@ -335,23 +335,23 @@ register_mem_fallback(struct mem_range *memp)
return (register_mem_int(&mmio_rb_fallback, memp));
}
int
int
unregister_mem(struct mem_range *memp)
{
struct mem_range *mr;
struct mmio_rb_range *entry = NULL;
int err, perror, i;
pthread_rwlock_wrlock(&mmio_rwlock);
err = mmio_rb_lookup(&mmio_rb_root, memp->base, &entry);
if (err == 0) {
mr = &entry->mr_param;
assert(mr->name == memp->name);
assert(mr->base == memp->base && mr->size == memp->size);
assert(mr->base == memp->base && mr->size == memp->size);
assert((mr->flags & MEM_F_IMMUTABLE) == 0);
RB_REMOVE(mmio_rb_tree, &mmio_rb_root, entry);
/* flush Per-vCPU cache */
/* flush Per-vCPU cache */
for (i=0; i < VM_MAXCPU; i++) {
if (mmio_hint[i] == entry)
mmio_hint[i] = NULL;
@ -362,7 +362,7 @@ unregister_mem(struct mem_range *memp)
if (entry)
free(entry);
return (err);
}

8
usr.sbin/bhyve/mevent.c
View File

@ -29,7 +29,7 @@
*/
/*
* Micro event library for FreeBSD, designed for a single i/o thread
* Micro event library for FreeBSD, designed for a single i/o thread
* using kqueue, and having events be persistent by default.
*/
@ -117,7 +117,7 @@ static void
mevent_notify(void)
{
char c = '\0';
/*
* If calling from outside the i/o thread, write a byte on the
* pipe to force the i/o thread to exit the blocking kevent call.
@ -546,10 +546,10 @@ mevent_dispatch(void)
if (ret == -1 && errno != EINTR) {
perror("Error return from kevent monitor");
}
/*
* Handle reported events
*/
mevent_handle(eventlist, ret);
}
}
}

2
usr.sbin/bhyve/mevent.h
View File

@ -44,7 +44,7 @@ enum ev_type {
struct mevent;
struct mevent *mevent_add(int fd, enum ev_type type,
struct mevent *mevent_add(int fd, enum ev_type type,
void (*func)(int, enum ev_type, void *),
void *param);
struct mevent *mevent_add_flags(int fd, enum ev_type type, int fflags,

2
usr.sbin/bhyve/mevent_test.c
View File

@ -111,7 +111,7 @@ timer_callback(int fd, enum ev_type type, void *param)
#ifdef MEVENT_ECHO
struct esync {
pthread_mutex_t e_mt;
pthread_cond_t e_cond;
pthread_cond_t e_cond;
};
static void

6
usr.sbin/bhyve/mptbl.c
View File

@ -180,7 +180,7 @@ mpt_build_bus_entries(bus_entry_ptr mpeb)
memset(mpeb, 0, sizeof(*mpeb));
mpeb->type = MPCT_ENTRY_BUS;
mpeb->bus_id = 1;
mpeb->bus_id = 1;
memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
}
@ -243,7 +243,7 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int id)
/*
* The following config is taken from kernel mptable.c
* mptable_parse_default_config_ints(...), for now
* mptable_parse_default_config_ints(...), for now
* just use the default config, tweek later if needed.
*/
@ -287,7 +287,7 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int id)
/* Next, generate entries for any PCI INTx interrupts. */
for (bus = 0; bus <= PCI_BUSMAX; bus++)
pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
}
void

2
usr.sbin/bhyve/net_backends.c
View File

@ -525,7 +525,7 @@ ng_init(struct net_backend *be, const char *devname,
/*
* The default ng_socket(4) buffer's size is too low.
* Calculate the minimum value between NG_SBUF_MAX_SIZE
* and kern.ipc.maxsockbuf.
* and kern.ipc.maxsockbuf.
*/
msbsz = sizeof(maxsbsz);
if (sysctlbyname("kern.ipc.maxsockbuf", &maxsbsz, &msbsz,

4
usr.sbin/bhyve/pci_ahci.c
View File

@ -1937,7 +1937,7 @@ ata_ioreq_cb(struct blockif_req *br, int err)
if (!err && aior->more) {
if (dsm)
ahci_handle_dsm_trim(p, slot, cfis, aior->done);
else
else
ahci_handle_rw(p, slot, cfis, aior->done);
goto out;
}
@ -2470,7 +2470,7 @@ pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
sc->ports = p;
ret = 1;
goto open_fail;
}
}
sc->port[p].bctx = bctxt;
sc->port[p].pr_sc = sc;
sc->port[p].port = p;

44
usr.sbin/bhyve/pci_e82545.c
View File

@ -264,7 +264,7 @@ struct e82545_softc {
uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */
uint32_t esc_LEDCTL; /* x0E00 LED control */
uint32_t esc_PBA; /* x1000 pkt buffer allocation */
/* Interrupt control */
int esc_irq_asserted;
uint32_t esc_ICR; /* x00C0 cause read/clear */
@ -294,12 +294,12 @@ struct e82545_softc {
uint32_t esc_TIDV; /* x3820 intr delay */
uint32_t esc_TXDCTL; /* x3828 desc control */
uint32_t esc_TADV; /* x382C intr absolute delay */
/* L2 frame acceptance */
struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
/* Receive */
struct e1000_rx_desc *esc_rxdesc;
pthread_cond_t esc_rx_cond;
@ -320,7 +320,7 @@ struct e82545_softc {
uint32_t esc_RADV; /* x282C intr absolute delay */
uint32_t esc_RSRPD; /* x2C00 recv small packet detect */
uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */
/* IO Port register access */
uint32_t io_addr;
@ -578,7 +578,7 @@ e82545_icr_assert(struct e82545_softc *sc, uint32_t bits)
uint32_t new;
DPRINTF("icr assert: 0x%x", bits);
/*
* An interrupt is only generated if bits are set that
* aren't already in the ICR, these bits are unmasked,
@ -654,7 +654,7 @@ e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value)
{
DPRINTF("intr_write: off %x, val %x", offset, value);
switch (offset) {
case E1000_ICR:
e82545_icr_deassert(sc, value);
@ -688,7 +688,7 @@ e82545_intr_read(struct e82545_softc *sc, uint32_t offset)
retval = 0;
DPRINTF("intr_read: off %x", offset);
switch (offset) {
case E1000_ICR:
retval = sc->esc_ICR;
@ -734,10 +734,10 @@ e82545_rx_update_rdba(struct e82545_softc *sc)
/* XXX verify desc base/len within phys mem range */
sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 |
sc->esc_RDBAL;
/* Cache host mapping of guest descriptor array */
sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx,
sc->esc_rdba, sc->esc_RDLEN);
sc->esc_rdba, sc->esc_RDLEN);
}
static void
@ -792,7 +792,7 @@ static void
e82545_tx_ctl(struct e82545_softc *sc, uint32_t val)
{
int on;
on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN);
/* ignore TCTL_EN settings that don't change state */
@ -1028,7 +1028,7 @@ e82545_txdesc_type(uint32_t lower)
int type;
type = 0;
if (lower & E1000_TXD_CMD_DEXT)
type = lower & E1000_TXD_MASK;
@ -1591,14 +1591,14 @@ e82545_read_ra(struct e82545_softc *sc, int reg)
eu->eu_eth.octet[0];
}
return (retval);
return (retval);
}
static void
e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
{
int ridx;
if (offset & 0x3) {
DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value);
return;
@ -1744,7 +1744,7 @@ e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
break;
case E1000_VFTA ... (E1000_VFTA + (127*4)):
sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value;
break;
break;
case E1000_EECD:
{
//DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value);
@ -1799,7 +1799,7 @@ e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
return;
}
case E1000_MANC:
case E1000_STATUS:
case E1000_STATUS:
return;
default:
DPRINTF("Unknown write register: 0x%x value:%x", offset, value);
@ -1892,7 +1892,7 @@ e82545_read_register(struct e82545_softc *sc, uint32_t offset)
case E1000_RSRPD:
retval = sc->esc_RSRPD;
break;
case E1000_RXCSUM:
case E1000_RXCSUM:
retval = sc->esc_RXCSUM;
break;
case E1000_TXCW:
@ -1941,7 +1941,7 @@ e82545_read_register(struct e82545_softc *sc, uint32_t offset)
break;
case E1000_VFTA ... (E1000_VFTA + (127*4)):
retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2];
break;
break;
case E1000_EECD:
//DPRINTF("EECD read %x", sc->eeprom_control);
retval = sc->eeprom_control;
@ -2137,7 +2137,7 @@ e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
{
struct e82545_softc *sc;
uint64_t retval;
//DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size);
sc = pi->pi_arg;
retval = 0;
@ -2209,7 +2209,7 @@ e82545_reset(struct e82545_softc *sc, int drvr)
}
sc->esc_LEDCTL = 0x07061302;
sc->esc_PBA = 0x00100030;
/* start nvm in opcode mode. */
sc->nvm_opaddr = 0;
sc->nvm_mode = E82545_NVM_MODE_OPADDR;
@ -2223,7 +2223,7 @@ e82545_reset(struct e82545_softc *sc, int drvr)
sc->esc_ICS = 0;
sc->esc_IMS = 0;
sc->esc_IMC = 0;
/* L2 filters */
if (!drvr) {
memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan));
@ -2239,7 +2239,7 @@ e82545_reset(struct e82545_softc *sc, int drvr)
for (i = 0; i < 16; i++)
sc->esc_uni[i].eu_valid = 0;
}
/* receive */
if (!drvr) {
sc->esc_RDBAL = 0;
@ -2307,7 +2307,7 @@ e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1);
/* TODO: this card also supports msi, but the freebsd driver for it
* does not, so I have not implemented it. */
pci_lintr_request(pi);

6
usr.sbin/bhyve/pci_emul.c
View File

@ -2341,7 +2341,7 @@ pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
} else {
printf("diow: memw unknown size %d\n", size);
}
/*
* magic interrupt ??
*/
@ -2366,7 +2366,7 @@ pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
offset, size);
return (0);
}
value = 0;
if (size == 1) {
value = sc->ioregs[offset];
@ -2385,7 +2385,7 @@ pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
offset, size);
return (0);
}
i = baridx - 1; /* 'memregs' index */
if (size == 1) {

10
usr.sbin/bhyve/pci_emul.h
View File

@ -110,7 +110,7 @@ struct msix_table_entry {
uint32_t vector_control;
} __packed;
/*
/*
* In case the structure is modified to hold extra information, use a define
* for the size that should be emulated.
*/
@ -156,7 +156,7 @@ struct pci_devinst {
int table_count;
uint32_t pba_offset;
int pba_size;
int function_mask;
int function_mask;
struct msix_table_entry *table; /* allocated at runtime */
uint8_t *mapped_addr;
size_t mapped_size;
@ -263,21 +263,21 @@ int pci_pause(struct vmctx *ctx, const char *dev_name);
int pci_resume(struct vmctx *ctx, const char *dev_name);
#endif
static __inline void
static __inline void
pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
{
assert(offset <= PCI_REGMAX);
*(uint8_t *)(pi->pi_cfgdata + offset) = val;
}
static __inline void
static __inline void
pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
{
assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
*(uint16_t *)(pi->pi_cfgdata + offset) = val;
}
static __inline void
static __inline void
pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
{
assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);

2
usr.sbin/bhyve/pci_fbuf.c
View File

@ -377,7 +377,7 @@ pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
{
int error;
struct pci_fbuf_softc *sc;
if (fbuf_sc != NULL) {
EPRINTLN("Only one frame buffer device is allowed.");
return (-1);

2
usr.sbin/bhyve/pci_hda.h
View File

@ -28,7 +28,7 @@
* $FreeBSD$
*/
#ifndef _HDA_EMUL_H_
#ifndef _HDA_EMUL_H_
#define _HDA_EMUL_H_
#include <stdio.h>

2
usr.sbin/bhyve/pci_lpc.c
View File

@ -161,7 +161,7 @@ lpc_uart_intr_assert(void *arg)
static void
lpc_uart_intr_deassert(void *arg)
{
/*
/*
* The COM devices on the LPC bus generate edge triggered interrupts,
* so nothing more to do here.
*/

10
usr.sbin/bhyve/pci_nvme.c
View File

@ -5,7 +5,7 @@
* Copyright (c) 2018 Leon Dang
* Copyright (c) 2020 Chuck Tuffli
*
* Function crc16 Copyright (c) 2017, Fedor Uporov
* Function crc16 Copyright (c) 2017, Fedor Uporov
* Obtained from function ext2_crc16() in sys/fs/ext2fs/ext2_csum.c
*
* Redistribution and use in source and binary forms, with or without
@ -780,7 +780,7 @@ pci_nvme_aer_get(struct pci_nvme_softc *sc)
sc->aer_count--;
}
pthread_mutex_unlock(&sc->aer_mtx);
return (aer);
}
@ -1041,7 +1041,7 @@ pci_nvme_init_controller(struct vmctx *ctx, struct pci_nvme_softc *sc)
DPRINTF("%s mapping Admin-SQ guest 0x%lx, host: %p",
__func__, sc->regs.asq, sc->submit_queues[0].qbase);
acqs = ((sc->regs.aqa >> NVME_AQA_REG_ACQS_SHIFT) &
acqs = ((sc->regs.aqa >> NVME_AQA_REG_ACQS_SHIFT) &
NVME_AQA_REG_ACQS_MASK) + 1;
sc->compl_queues[0].size = acqs;
sc->compl_queues[0].qbase = vm_map_gpa(ctx, sc->regs.acq,
@ -1222,7 +1222,7 @@ nvme_opc_create_io_sq(struct pci_nvme_softc* sc, struct nvme_command* command,
DPRINTF("%s completed creating IOSQ qid %u",
__func__, qid);
} else {
/*
/*
* Guest sent non-cont submission queue request.
* This setting is unsupported by this emulation.
*/
@ -1842,7 +1842,7 @@ pci_nvme_handle_admin_cmd(struct pci_nvme_softc* sc, uint64_t value)
sqhead = sq->head;
DPRINTF("sqhead %u, tail %u", sqhead, sq->tail);
while (sqhead != atomic_load_acq_short(&sq->tail)) {
cmd = &(sq->qbase)[sqhead];
compl.cdw0 = 0;

18
usr.sbin/bhyve/pci_passthru.c
View File

@ -97,7 +97,7 @@ static int
msi_caplen(int msgctrl)
{
int len;
len = 10; /* minimum length of msi capability */
if (msgctrl & PCIM_MSICTRL_64BIT)
@ -211,7 +211,7 @@ cfginitmsi(struct passthru_softc *sc)
}
} else if (cap == PCIY_MSIX) {
/*
* Copy the MSI-X capability
* Copy the MSI-X capability
*/
sc->psc_msix.capoff = ptr;
caplen = 12;
@ -271,7 +271,7 @@ cfginitmsi(struct passthru_softc *sc)
#endif
/* Make sure one of the capabilities is present */
if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
return (-1);
else
return (0);
@ -726,13 +726,13 @@ msicap_access(struct passthru_softc *sc, int coff)
return (0);
}
static int
static int
msixcap_access(struct passthru_softc *sc, int coff)
{
if (sc->psc_msix.capoff == 0)
if (sc->psc_msix.capoff == 0)
return (0);
return (coff >= sc->psc_msix.capoff &&
return (coff >= sc->psc_msix.capoff &&
coff < sc->psc_msix.capoff + MSIX_CAPLEN);
}
@ -819,12 +819,12 @@ passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
msix_table_entries = pi->pi_msix.table_count;
for (i = 0; i < msix_table_entries; i++) {
error = vm_setup_pptdev_msix(ctx, vcpu,
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
sc->psc_sel.pc_func, i,
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
sc->psc_sel.pc_func, i,
pi->pi_msix.table[i].addr,
pi->pi_msix.table[i].msg_data,
pi->pi_msix.table[i].vector_control);
if (error)
err(1, "vm_setup_pptdev_msix");
}

4
usr.sbin/bhyve/pci_virtio_9p.c
View File

@ -153,7 +153,7 @@ pci_vt9p_get_buffer(struct l9p_request *req, struct iovec *iov, size_t *niov,
{
struct pci_vt9p_request *preq = req->lr_aux;
size_t n = preq->vsr_niov - preq->vsr_respidx;
memcpy(iov, preq->vsr_iov + preq->vsr_respidx,
n * sizeof(struct iovec));
*niov = n;
@ -304,7 +304,7 @@ pci_vt9p_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
sc->vsc_config->tag_len = (uint16_t)strlen(sharename);
memcpy(sc->vsc_config->tag, sharename, sc->vsc_config->tag_len);
if (l9p_backend_fs_init(&sc->vsc_fs_backend, rootfd, ro) != 0) {
errno = ENXIO;
return (1);

4
usr.sbin/bhyve/pci_virtio_console.c
View File

@ -593,7 +593,7 @@ pci_vtcon_control_send(struct pci_vtcon_softc *sc,
vq_relchain(vq, req.idx, sizeof(struct pci_vtcon_control) + len);
vq_endchains(vq, 1);
}
static void
pci_vtcon_notify_tx(void *vsc, struct vqueue_info *vq)
@ -696,7 +696,7 @@ pci_vtcon_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
sc->vsc_config = calloc(1, sizeof(struct pci_vtcon_config));
sc->vsc_config->max_nr_ports = VTCON_MAXPORTS;
sc->vsc_config->cols = 80;
sc->vsc_config->rows = 25;
sc->vsc_config->rows = 25;
vi_softc_linkup(&sc->vsc_vs, &vtcon_vi_consts, sc, pi, sc->vsc_queues);
sc->vsc_vs.vs_mtx = &sc->vsc_mtx;

14
usr.sbin/bhyve/pci_virtio_net.c
View File

@ -117,7 +117,7 @@ struct pci_vtnet_softc {
int resetting; /* protected by tx_mtx */
uint64_t vsc_features; /* negotiated features */
pthread_mutex_t rx_mtx;
int rx_merge; /* merged rx bufs in use */
@ -628,9 +628,9 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
sc->vsc_consts.vc_hv_caps |= VIRTIO_NET_F_MRG_RXBUF |
netbe_get_cap(sc->vsc_be);
/*
/*
* Since we do not actually support multiqueue,
* set the maximum virtqueue pairs to 1.
* set the maximum virtqueue pairs to 1.
*/
sc->vsc_config.max_virtqueue_pairs = 1;
@ -643,7 +643,7 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
/* Link is always up. */
sc->vsc_config.status = 1;
vi_softc_linkup(&sc->vsc_vs, &sc->vsc_consts, sc, pi, sc->vsc_queues);
sc->vsc_vs.vs_mtx = &sc->vsc_mtx;
@ -660,12 +660,12 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
sc->rx_merge = 0;
sc->vhdrlen = sizeof(struct virtio_net_rxhdr) - 2;
pthread_mutex_init(&sc->rx_mtx, NULL);
pthread_mutex_init(&sc->rx_mtx, NULL);
/*
/*
* Initialize tx semaphore & spawn TX processing thread.
* As of now, only one thread for TX desc processing is
* spawned.
* spawned.
*/
sc->tx_in_progress = 0;
pthread_mutex_init(&sc->tx_mtx, NULL);

2
usr.sbin/bhyve/pci_virtio_scsi.c
View File

@ -628,7 +628,7 @@ pci_vtscsi_requestq_notify(void *vsc, struct vqueue_info *vq)
}
static int
pci_vtscsi_init_queue(struct pci_vtscsi_softc *sc,
pci_vtscsi_init_queue(struct pci_vtscsi_softc *sc,
struct pci_vtscsi_queue *queue, int num)
{
struct pci_vtscsi_worker *worker;

18
usr.sbin/bhyve/pci_xhci.c
View File

@ -489,7 +489,7 @@ pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
if (XHCI_DEVINST_PTR(sc, port))
p->portsc |= XHCI_PS_CCS;
@ -545,7 +545,7 @@ pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
break;
}
break;
case 4:
case 4:
/* Port power management status and control register */
p->portpmsc = value;
break;
@ -599,7 +599,7 @@ pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb,
if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
if (guestaddr)
*guestaddr = curtrb->qwTrb0 & ~0xFUL;
next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
} else {
if (guestaddr)
@ -1264,7 +1264,7 @@ pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot,
cmderr = pci_xhci_find_stream(sc, ep_ctx, streamid, &sctx);
if (sctx != NULL) {
assert(devep->ep_sctx != NULL);
devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
devep->ep_sctx_trbs[streamid].ringaddr =
trb->qwTrb0 & ~0xF;
@ -1383,7 +1383,7 @@ pci_xhci_complete_commands(struct pci_xhci_softc *sc)
while (1) {
sc->opregs.cr_p = trb;
type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
@ -1478,7 +1478,7 @@ pci_xhci_complete_commands(struct pci_xhci_softc *sc)
}
if (type != XHCI_TRB_TYPE_LINK) {
/*
/*
* insert command completion event and assert intr
*/
evtrb.qwTrb0 = crcr;
@ -1606,7 +1606,7 @@ pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer,
if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
evtrb.qwTrb0 = trb->qwTrb0;
evtrb.dwTrb2 = (edtla & 0xFFFFF) |
evtrb.dwTrb2 = (edtla & 0xFFFFF) |
XHCI_TRB_2_ERROR_SET(err);
evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
edtla = 0;
@ -2556,7 +2556,7 @@ pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
if (dev) {
port->portsc = XHCI_PS_CCS | /* connected */
XHCI_PS_PP; /* port power */
if (dev->dev_ue->ue_usbver == 2) {
port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
@ -2565,7 +2565,7 @@ pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
XHCI_PS_PED | /* enabled */
XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
}
DPRINTF(("Init port %d 0x%x", portn, port->portsc));
} else {
port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;

2
usr.sbin/bhyve/ps2mouse.h
View File

@ -32,7 +32,7 @@
#define _PS2MOUSE_H_
struct atkbdc_softc;
struct vm_snapshot_meta;
struct vm_snapshot_meta;
struct ps2mouse_softc *ps2mouse_init(struct atkbdc_softc *sc);

2
usr.sbin/bhyve/rtc.c
View File

@ -75,7 +75,7 @@ rtc_time(struct vmctx *ctx)
void
rtc_init(struct vmctx *ctx)
{
{
size_t himem;
size_t lomem;
int err;

10
usr.sbin/bhyve/uart_emul.c
View File

@ -381,11 +381,11 @@ uart_drain(int fd, enum ev_type ev, void *arg)
struct uart_softc *sc;
int ch;
sc = arg;
sc = arg;
assert(fd == sc->tty.rfd);
assert(ev == EVF_READ);
/*
* This routine is called in the context of the mevent thread
* to take out the softc lock to protect against concurrent
@ -422,7 +422,7 @@ uart_write(struct uart_softc *sc, int offset, uint8_t value)
sc->dll = value;
goto done;
}
if (offset == REG_DLH) {
sc->dlh = value;
goto done;
@ -540,7 +540,7 @@ uart_read(struct uart_softc *sc, int offset)
reg = sc->dll;
goto done;
}
if (offset == REG_DLH) {
reg = sc->dlh;
goto done;
@ -558,7 +558,7 @@ uart_read(struct uart_softc *sc, int offset)
iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
intr_reason = uart_intr_reason(sc);
/*
* Deal with side effects of reading the IIR register
*/

6
usr.sbin/bhyve/usb_mouse.c
View File

@ -535,8 +535,8 @@ umouse_request(void *scarg, struct usb_data_xfer *xfer)
eshort = data->blen > 0;
break;
case UREQ(UR_GET_STATUS, UT_READ_INTERFACE):
case UREQ(UR_GET_STATUS, UT_READ_ENDPOINT):
case UREQ(UR_GET_STATUS, UT_READ_INTERFACE):
case UREQ(UR_GET_STATUS, UT_READ_ENDPOINT):
DPRINTF(("umouse: (UR_GET_STATUS, UT_READ_INTERFACE)"));
if (data != NULL && len > 1) {
USETW(udata, 0);
@ -752,7 +752,7 @@ umouse_data_handler(void *scarg, struct usb_data_xfer *xfer, int dir,
sc->polling = 0;
pthread_mutex_unlock(&sc->mtx);
} else {
} else {
USB_DATA_SET_ERRCODE(data, USB_STALL);
err = USB_ERR_STALLED;
}