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Remove burn bridges code that saved/restored the pci config registers

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that are now handled in the pci bus layer.  They are no longer
necessary.
This commit is contained in:
Warner Losh 2004-06-28 20:07:03 +00:00
parent b351299ca3
commit c3e7434f34
15 changed files with 6 additions and 473 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
sys/dev/dc/if_dc.c
View File

@ -226,9 +226,6 @@ static int dc_attach (device_t);
static int dc_detach (device_t);
static int dc_suspend (device_t);
static int dc_resume (device_t);
#ifndef BURN_BRIDGES
static void dc_acpi (device_t);
#endif
static struct dc_type *dc_devtype (device_t);
static int dc_newbuf (struct dc_softc *, int, int);
static int dc_encap (struct dc_softc *, struct mbuf **);
@ -1630,35 +1627,6 @@ dc_probe(device_t dev)
return (ENXIO);
}
#ifndef BURN_BRIDGES
static void
dc_acpi(device_t dev)
{
int unit;
u_int32_t iobase, membase, irq;
unit = device_get_unit(dev);
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
/* Save important PCI config data. */
iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
irq = pci_read_config(dev, DC_PCI_CFIT, 4);
/* Reset the power state. */
printf("dc%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
pci_write_config(dev, DC_PCI_CFIT, irq, 4);
}
}
#endif
static void
dc_apply_fixup(struct dc_softc *sc, int media)
{
@ -1876,12 +1844,7 @@ dc_attach(device_t dev)
mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
dc_acpi(dev);
#endif
/*
* Map control/status registers.
*/
@ -3798,21 +3761,12 @@ static int
dc_suspend(device_t dev)
{
struct dc_softc *sc;
int i, s;
int s;
s = splimp();
sc = device_get_softc(dev);
dc_stop(sc);
for (i = 0; i < 5; i++)
sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
sc->suspended = 1;
splx(s);
@ -3829,26 +3783,12 @@ dc_resume(device_t dev)
{
struct dc_softc *sc;
struct ifnet *ifp;
int i, s;
int s;
s = splimp();
sc = device_get_softc(dev);
ifp = &sc->arpcom.ac_if;
#ifndef BURN_BRIDGES
dc_acpi(dev);
#endif
/* better way to do this? */
for (i = 0; i < 5; i++)
pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
/* reenable busmastering */
pci_enable_busmaster(dev);
pci_enable_io(dev, DC_RES);
/* reinitialize interface if necessary */
if (ifp->if_flags & IFF_UP)

24
sys/dev/sf/if_sf.c
View File

@ -649,30 +649,6 @@ sf_attach(dev)
mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
/* Reset the power state. */
printf("sf%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/dev/sk/if_sk.c
View File

@ -1498,30 +1498,6 @@ skc_attach(dev)
mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
/* Reset the power state. */
printf("skc%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/dev/vr/if_vr.c
View File

@ -715,30 +715,6 @@ vr_attach(dev)
mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
/* Reset the power state. */
printf("vr%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

66
sys/pci/if_dc.c
View File

@ -226,9 +226,6 @@ static int dc_attach (device_t);
static int dc_detach (device_t);
static int dc_suspend (device_t);
static int dc_resume (device_t);
#ifndef BURN_BRIDGES
static void dc_acpi (device_t);
#endif
static struct dc_type *dc_devtype (device_t);
static int dc_newbuf (struct dc_softc *, int, int);
static int dc_encap (struct dc_softc *, struct mbuf **);
@ -1630,35 +1627,6 @@ dc_probe(device_t dev)
return (ENXIO);
}
#ifndef BURN_BRIDGES
static void
dc_acpi(device_t dev)
{
int unit;
u_int32_t iobase, membase, irq;
unit = device_get_unit(dev);
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
/* Save important PCI config data. */
iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
irq = pci_read_config(dev, DC_PCI_CFIT, 4);
/* Reset the power state. */
printf("dc%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
pci_write_config(dev, DC_PCI_CFIT, irq, 4);
}
}
#endif
static void
dc_apply_fixup(struct dc_softc *sc, int media)
{
@ -1876,12 +1844,7 @@ dc_attach(device_t dev)
mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
dc_acpi(dev);
#endif
/*
* Map control/status registers.
*/
@ -3798,21 +3761,12 @@ static int
dc_suspend(device_t dev)
{
struct dc_softc *sc;
int i, s;
int s;
s = splimp();
sc = device_get_softc(dev);
dc_stop(sc);
for (i = 0; i < 5; i++)
sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
sc->suspended = 1;
splx(s);
@ -3829,26 +3783,12 @@ dc_resume(device_t dev)
{
struct dc_softc *sc;
struct ifnet *ifp;
int i, s;
int s;
s = splimp();
sc = device_get_softc(dev);
ifp = &sc->arpcom.ac_if;
#ifndef BURN_BRIDGES
dc_acpi(dev);
#endif
/* better way to do this? */
for (i = 0; i < 5; i++)
pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
/* reenable busmastering */
pci_enable_busmaster(dev);
pci_enable_io(dev, DC_RES);
/* reinitialize interface if necessary */
if (ifp->if_flags & IFF_UP)

24
sys/pci/if_pcn.c
View File

@ -497,30 +497,6 @@ pcn_attach(dev)
/* Initialize our mutex. */
mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
/* Reset the power state. */
printf("pcn%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

57
sys/pci/if_rl.c
View File

@ -889,32 +889,6 @@ rl_attach(dev)
mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
/* Reset the power state. */
printf("rl%d: chip is is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/
@ -1890,24 +1864,10 @@ static int
rl_suspend(dev)
device_t dev;
{
#ifndef BURN_BRIDGES
register int i;
#endif
struct rl_softc *sc;
sc = device_get_softc(dev);
rl_stop(sc);
#ifndef BURN_BRIDGES
for (i = 0; i < 5; i++)
sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
#endif
sc->suspended = 1;
return (0);
@ -1922,29 +1882,12 @@ static int
rl_resume(dev)
device_t dev;
{
#ifndef BURN_BRIDGES
register int i;
#endif
struct rl_softc *sc;
struct ifnet *ifp;
sc = device_get_softc(dev);
ifp = &sc->arpcom.ac_if;
#ifndef BURN_BRIDGES
/* better way to do this? */
for (i = 0; i < 5; i++)
pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
/* reenable busmastering */
pci_enable_busmaster(dev);
pci_enable_io(dev, RL_RES);
#endif
/* reinitialize interface if necessary */
if (ifp->if_flags & IFF_UP)
rl_init(sc);

8
sys/pci/if_rlreg.h
View File

@ -682,14 +682,6 @@ struct rl_softc {
#ifdef DEVICE_POLLING
int rxcycles;
#endif
#ifndef BURN_BRIDGES
u_int32_t saved_maps[5]; /* pci data */
u_int32_t saved_biosaddr;
u_int8_t saved_intline;
u_int8_t saved_cachelnsz;
u_int8_t saved_lattimer;
#endif
};
#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)

24
sys/pci/if_sf.c
View File

@ -649,30 +649,6 @@ sf_attach(dev)
mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
/* Reset the power state. */
printf("sf%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/pci/if_sis.c
View File

@ -1053,30 +1053,6 @@ sis_attach(dev)
sc->sis_type = SIS_TYPE_83815;
sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
/* Reset the power state. */
printf("sis%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/pci/if_sk.c
View File

@ -1498,30 +1498,6 @@ skc_attach(dev)
mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
/* Reset the power state. */
printf("skc%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/pci/if_ste.c
View File

@ -1005,30 +1005,6 @@ ste_attach(dev)
mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
/* Reset the power state. */
printf("ste%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

24
sys/pci/if_vr.c
View File

@ -715,30 +715,6 @@ vr_attach(dev)
mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
/* Reset the power state. */
printf("vr%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

25
sys/pci/if_wb.c
View File

@ -798,31 +798,6 @@ wb_attach(dev)
mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF | MTX_RECURSE);
#ifndef BURN_BRIDGES
/*
* Handle power management nonsense.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
/* Reset the power state. */
printf("wb%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/

41
sys/pci/if_xl.c
View File

@ -1358,47 +1358,6 @@ xl_attach(dev)
break;
}
#ifndef BURN_BRIDGES
/*
* If this is a 3c905B, we have to check one extra thing.
* The 905B supports power management and may be placed in
* a low-power mode (D3 mode), typically by certain operating
* systems which shall not be named. The PCI BIOS is supposed
* to reset the NIC and bring it out of low-power mode, but
* some do not. Consequently, we have to see if this chip
* supports power management, and if so, make sure it's not
* in low-power mode. If power management is available, the
* capid byte will be 0x01.
*
* I _think_ that what actually happens is that the chip
* loses its PCI configuration during the transition from
* D3 back to D0; this means that it should be possible for
* us to save the PCI iobase, membase and IRQ, put the chip
* back in the D0 state, then restore the PCI config ourselves.
*/
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
/* Reset the power state. */
printf("xl%d: chip is in D%d power mode "
"-- setting to D0\n", unit,
pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
/* Restore PCI config data. */
pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
}
#endif
/*
* Map control/status registers.
*/