Add a driver for the AVM Fritz!Card PCI version 2 ISDN controller.
MFC after: 4 weeks
This commit is contained in:
Gary Jennejohn
parent
be9546c713
commit
c3e8386594
@ -58,6 +58,7 @@
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#define L0IFPNPUNIT(u) ( (((L1DRVR_IFPNP) << 8) & 0xff00) | ((u) & 0xff))
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#define L0ICCHPUNIT(u) ( (((L1DRVR_ICCHP) << 8) & 0xff00) | ((u) & 0xff))
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#define L0ITJCUNIT(u) ( (((L1DRVR_ITJC) << 8) & 0xff00) | ((u) & 0xff))
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#define L0IFPI2UNIT(u) ( (((L1DRVR_IFPI2) << 8) & 0xff00) | ((u) & 0xff))
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/* jump table for the multiplex functions */
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struct i4b_l1mux_func {
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@ -36,6 +36,7 @@
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#include "isic.h"
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#include "iwic.h"
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#include "ifpi.h"
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#include "ifpi2.h"
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#include "ifpnp.h"
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#include "ihfc.h"
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#include "itjc.h"
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@ -95,6 +96,10 @@ static int l1iwicunittab[MAXL1UNITS];
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static int l1ifpiunittab[MAXL1UNITS];
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#endif
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#if NIFPI2 > 0
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static int l1ifpi2unittab[MAXL1UNITS];
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#endif
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#if NIHFC > 0
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static int l1ihfcunittab[MAXL1UNITS];
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#endif
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@ -177,6 +182,11 @@ getl1tab(int drv)
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return(l1ifpiunittab);
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break;
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#endif
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#if NIFPI2 > 0
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case L1DRVR_IFPI2:
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return(l1ifpi2unittab);
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break;
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#endif
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#if NIHFC > 0
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case L1DRVR_IHFC:
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return(l1ihfcunittab);
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@ -315,6 +325,11 @@ i4b_l1_mph_status_ind(int drv_unit, int status, int parm, struct i4b_l1mux_func
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printf("ifpi%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
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break;
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#endif
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#if NIFPI2 > 0
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case L1DRVR_IFPI2:
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printf("ifpi2-%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
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break;
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#endif
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#if NIFPNP > 0
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case L1DRVR_IFPNP:
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printf("ifpnp%d: passive stack unit %d\n", L0UNIT(drv_unit), numl1units);
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64
sys/i4b/layer1/ifpi2/i4b_ifpi2_ext.h
Normal file
64
sys/i4b/layer1/ifpi2/i4b_ifpi2_ext.h
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2001 Gary Jennejohn. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_ifpi2 - Fritz!Card PCI Version 2 for split layers
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* ------------------------------------------
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*
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* $Id$
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*
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* $FreeBSD$
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*
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*
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*---------------------------------------------------------------------------*/
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#ifndef _I4B_IFPI2_EXT_H_
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#define _I4B_IFPI2_EXT_H_
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#include <i4b/include/i4b_l3l4.h>
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void ifpi2_set_linktab(int , int , drvr_link_t * );
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isdn_link_t *ifpi2_ret_linktab(int , int );
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int ifpi2_ph_data_req(int , struct mbuf *, int );
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int ifpi2_ph_activate_req(int );
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int ifpi2_mph_command_req(int , int , void *);
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void ifpi2_isacsx_irq(struct l1_softc *, int );
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void ifpi2_isacsx_l1_cmd(struct l1_softc *, int );
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int ifpi2_isacsx_init(struct l1_softc *);
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void ifpi2_recover(struct l1_softc *);
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char * ifpi2_printstate(struct l1_softc *);
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void ifpi2_next_state(struct l1_softc *, int );
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#define IFPI2_MAXUNIT 4
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extern struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
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/* the ISACSX has 2 mask registers of interest - cannot use ISAC_IMASK */
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extern unsigned char isacsx_imaskd;
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extern unsigned char isacsx_imask;
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#endif /* _I4B_IFPI2_EXT_H_ */
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600
sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.c
Normal file
600
sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.c
Normal file
@ -0,0 +1,600 @@
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/*
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* Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
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* Copyright (c) 2001 Gary Jennejohn. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_ifpi2_isac.c - i4b Fritz PCI Version 2 ISACSX handler
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* --------------------------------------------
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*
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* $Id$
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*
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* $FreeBSD$
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*
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*
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*---------------------------------------------------------------------------*/
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#include "ifpi2.h"
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#include "pci.h"
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#if (NIFPI2 > 0) && (NPCI > 0)
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#include "opt_i4b.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#include <machine/i4b_trace.h>
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#include <i4b/layer1/i4b_l1.h>
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#include <i4b/layer1/isic/i4b_isic.h>
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#include <i4b/layer1/isic/i4b_hscx.h>
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#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
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#include <i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h>
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#include <i4b/include/i4b_global.h>
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#include <i4b/include/i4b_mbuf.h>
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static u_char ifpi2_isacsx_exir_hdlr(register struct l1_softc *sc, u_char exir);
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static void ifpi2_isacsx_ind_hdlr(register struct l1_softc *sc, int ind);
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/* the ISACSX has 2 mask registers of interest - cannot use ISAC_IMASK */
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unsigned char isacsx_imaskd;
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unsigned char isacsx_imask;
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/*---------------------------------------------------------------------------*
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* ISACSX interrupt service routine
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*---------------------------------------------------------------------------*/
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void
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ifpi2_isacsx_irq(struct l1_softc *sc, int ista)
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{
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register u_char c = 0;
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register u_char istad = 0;
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NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
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/* was it an HDLC interrupt ? */
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if (ista & ISACSX_ISTA_ICD)
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{
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istad = ISAC_READ(I_ISTAD);
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NDBGL1(L1_F_MSG, "unit %d: istad = 0x%02x", sc->sc_unit, istad);
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if(istad & (ISACSX_ISTAD_RFO|ISACSX_ISTAD_XMR|ISACSX_ISTAD_XDU))
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{
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/* not really EXIR, but very similar */
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c |= ifpi2_isacsx_exir_hdlr(sc, istad);
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}
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}
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if(istad & ISACSX_ISTAD_RME) /* receive message end */
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{
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register int rest;
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u_char rsta;
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/* get rx status register */
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rsta = ISAC_READ(I_RSTAD);
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/* Check for Frame and CRC valid */
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if((rsta & ISACSX_RSTAD_MASK) != (ISACSX_RSTAD_VFR|ISACSX_RSTAD_CRC))
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{
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int error = 0;
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if(!(rsta & ISACSX_RSTAD_VFR)) /* VFR error */
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{
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error++;
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NDBGL1(L1_I_ERR, "unit %d: Frame not valid error", sc->sc_unit);
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}
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if(!(rsta & ISACSX_RSTAD_CRC)) /* CRC error */
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{
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error++;
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NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
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}
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if(rsta & ISACSX_RSTAD_RDO) /* ReceiveDataOverflow */
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{
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error++;
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NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
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}
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if(rsta & ISACSX_RSTAD_RAB) /* ReceiveABorted */
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{
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error++;
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NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
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}
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if(error == 0)
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NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTAD = 0x%02x!", sc->sc_unit, rsta);
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i4b_Dfreembuf(sc->sc_ibuf);
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c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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ISAC_WRITE(I_CMDRD, ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES);
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return;
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}
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rest = (ISAC_READ(I_RBCLD) & (ISACSX_FIFO_LEN-1));
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if(rest == 0)
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rest = ISACSX_FIFO_LEN;
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if(sc->sc_ibuf == NULL)
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{
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if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
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sc->sc_ib = sc->sc_ibuf->m_data;
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else
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panic("ifpi2_isacsx_irq: RME, i4b_Dgetmbuf returns NULL!\n");
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sc->sc_ilen = 0;
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}
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if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
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{
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ISAC_RDFIFO(sc->sc_ib, rest);
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/* the last byte contains status, strip it */
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sc->sc_ilen += rest - 1;
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sc->sc_ibuf->m_pkthdr.len =
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sc->sc_ibuf->m_len = sc->sc_ilen;
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if(sc->sc_trace & TRACE_D_RX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = L0IFPI2UNIT(sc->sc_unit);
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hdr.type = TRC_CH_D;
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hdr.dir = FROM_NT;
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hdr.count = ++sc->sc_trace_dcount;
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MICROTIME(hdr.time);
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i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
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}
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c |= ISACSX_CMDRD_RMC;
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if(sc->sc_enabled &&
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(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
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{
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i4b_l1_ph_data_ind(L0IFPI2UNIT(sc->sc_unit), sc->sc_ibuf);
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}
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else
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{
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i4b_Dfreembuf(sc->sc_ibuf);
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}
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}
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else
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{
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NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
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i4b_Dfreembuf(sc->sc_ibuf);
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c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
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}
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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}
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if(istad & ISACSX_ISTAD_RPF) /* receive fifo full */
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{
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if(sc->sc_ibuf == NULL)
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{
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if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
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sc->sc_ib= sc->sc_ibuf->m_data;
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else
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panic("ifpi2_isacsx_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
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sc->sc_ilen = 0;
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}
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if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISACSX_FIFO_LEN))
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{
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ISAC_RDFIFO(sc->sc_ib, ISACSX_FIFO_LEN);
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sc->sc_ilen += ISACSX_FIFO_LEN;
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sc->sc_ib += ISACSX_FIFO_LEN;
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c |= ISACSX_CMDRD_RMC;
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}
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else
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{
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NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
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i4b_Dfreembuf(sc->sc_ibuf);
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
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}
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}
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if(istad & ISACSX_ISTAD_XPR) /* transmit fifo empty (XPR bit set) */
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{
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if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
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{
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sc->sc_freeflag = sc->sc_freeflag2;
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sc->sc_obuf = sc->sc_obuf2;
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sc->sc_op = sc->sc_obuf->m_data;
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sc->sc_ol = sc->sc_obuf->m_len;
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sc->sc_obuf2 = NULL;
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#ifdef NOTDEF
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printf("ob2=%x, op=%x, ol=%d, f=%d #",
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sc->sc_obuf,
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sc->sc_op,
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sc->sc_ol,
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sc->sc_state);
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#endif
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}
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else
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{
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#ifdef NOTDEF
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printf("ob=%x, op=%x, ol=%d, f=%d #",
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sc->sc_obuf,
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sc->sc_op,
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sc->sc_ol,
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sc->sc_state);
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#endif
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}
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if(sc->sc_obuf)
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{
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ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISACSX_FIFO_LEN));
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if(sc->sc_ol > ISACSX_FIFO_LEN) /* length > 32 ? */
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{
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sc->sc_op += ISACSX_FIFO_LEN; /* bufferptr+32 */
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sc->sc_ol -= ISACSX_FIFO_LEN; /* length - 32 */
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c |= ISACSX_CMDRD_XTF; /* set XTF bit */
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}
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else
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{
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if(sc->sc_freeflag)
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{
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i4b_Dfreembuf(sc->sc_obuf);
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sc->sc_freeflag = 0;
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}
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sc->sc_obuf = NULL;
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sc->sc_op = NULL;
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sc->sc_ol = 0;
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c |= ISACSX_CMDRD_XTF | ISACSX_CMDRD_XME;
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}
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}
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else
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{
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sc->sc_state &= ~ISAC_TX_ACTIVE;
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}
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}
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if(ista & ISACSX_ISTA_CIC) /* channel status change CISQ */
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{
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register u_char ci;
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/* get command/indication rx register*/
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ci = ISAC_READ(I_CIR0);
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/* C/I code change IRQ (flag already cleared by CIR0 read) */
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if(ci & ISACSX_CIR0_CIC0)
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ifpi2_isacsx_ind_hdlr(sc, (ci >> 4) & 0xf);
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}
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if(c)
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{
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ISAC_WRITE(I_CMDRD, c);
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}
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}
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/*---------------------------------------------------------------------------*
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* ISACSX L1 Extended IRQ handler
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*---------------------------------------------------------------------------*/
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static u_char
|
||||
ifpi2_isacsx_exir_hdlr(register struct l1_softc *sc, u_char exir)
|
||||
{
|
||||
u_char c = 0;
|
||||
|
||||
if(exir & ISACSX_ISTAD_XMR)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
|
||||
|
||||
c |= ISACSX_CMDRD_XRES;
|
||||
}
|
||||
|
||||
if(exir & ISACSX_ISTAD_XDU)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
|
||||
|
||||
c |= ISACSX_CMDRD_XRES;
|
||||
}
|
||||
|
||||
if(exir & ISACSX_ISTAD_RFO)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
|
||||
|
||||
c |= ISACSX_CMDRD_RMC;
|
||||
}
|
||||
|
||||
#if 0 /* all blocked per default */
|
||||
if(exir & ISACSX_EXIR_SOV)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
|
||||
}
|
||||
|
||||
if(exir & ISACSX_EXIR_MOS)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
|
||||
}
|
||||
|
||||
if(exir & ISACSX_EXIR_SAW)
|
||||
{
|
||||
/* cannot happen, STCR:TSF is set to 0 */
|
||||
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
|
||||
}
|
||||
|
||||
if(exir & ISACSX_EXIR_WOV)
|
||||
{
|
||||
/* cannot happen, STCR:TSF is set to 0 */
|
||||
|
||||
NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
|
||||
}
|
||||
#endif
|
||||
|
||||
return(c);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* ISACSX L1 Indication handler
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
ifpi2_isacsx_ind_hdlr(register struct l1_softc *sc, int ind)
|
||||
{
|
||||
register int event;
|
||||
|
||||
switch(ind)
|
||||
{
|
||||
case ISACSX_CIR0_IAI8:
|
||||
NDBGL1(L1_I_CICO, "rx AI8 in state %s", ifpi2_printstate(sc));
|
||||
if(sc->sc_bustyp == BUS_TYPE_IOM2)
|
||||
ifpi2_isacsx_l1_cmd(sc, CMD_AR8);
|
||||
event = EV_INFO48;
|
||||
i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IAI10:
|
||||
NDBGL1(L1_I_CICO, "rx AI10 in state %s", ifpi2_printstate(sc));
|
||||
if(sc->sc_bustyp == BUS_TYPE_IOM2)
|
||||
ifpi2_isacsx_l1_cmd(sc, CMD_AR10);
|
||||
event = EV_INFO410;
|
||||
i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IRSY:
|
||||
NDBGL1(L1_I_CICO, "rx RSY in state %s", ifpi2_printstate(sc));
|
||||
event = EV_RSY;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IPU:
|
||||
NDBGL1(L1_I_CICO, "rx PU in state %s", ifpi2_printstate(sc));
|
||||
event = EV_PU;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IDR:
|
||||
NDBGL1(L1_I_CICO, "rx DR in state %s", ifpi2_printstate(sc));
|
||||
ifpi2_isacsx_l1_cmd(sc, CMD_DIU);
|
||||
event = EV_DR;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IDID:
|
||||
NDBGL1(L1_I_CICO, "rx DID in state %s", ifpi2_printstate(sc));
|
||||
event = EV_INFO0;
|
||||
i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IDIS:
|
||||
NDBGL1(L1_I_CICO, "rx DIS in state %s", ifpi2_printstate(sc));
|
||||
event = EV_DIS;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IEI:
|
||||
NDBGL1(L1_I_CICO, "rx EI in state %s", ifpi2_printstate(sc));
|
||||
ifpi2_isacsx_l1_cmd(sc, CMD_DIU);
|
||||
event = EV_EI;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IARD:
|
||||
NDBGL1(L1_I_CICO, "rx ARD in state %s", ifpi2_printstate(sc));
|
||||
event = EV_INFO2;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_ITI:
|
||||
NDBGL1(L1_I_CICO, "rx TI in state %s", ifpi2_printstate(sc));
|
||||
event = EV_INFO0;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_IATI:
|
||||
NDBGL1(L1_I_CICO, "rx ATI in state %s", ifpi2_printstate(sc));
|
||||
event = EV_INFO0;
|
||||
break;
|
||||
|
||||
case ISACSX_CIR0_ISD:
|
||||
NDBGL1(L1_I_CICO, "rx SD in state %s", ifpi2_printstate(sc));
|
||||
event = EV_INFO0;
|
||||
break;
|
||||
|
||||
default:
|
||||
NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, ifpi2_printstate(sc));
|
||||
event = EV_INFO0;
|
||||
break;
|
||||
}
|
||||
ifpi2_next_state(sc, event);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* execute a layer 1 command
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
ifpi2_isacsx_l1_cmd(struct l1_softc *sc, int command)
|
||||
{
|
||||
u_char cmd;
|
||||
|
||||
#ifdef I4B_SMP_WORKAROUND
|
||||
|
||||
/* XXXXXXXXXXXXXXXXXXX */
|
||||
|
||||
/*
|
||||
* patch from Wolfgang Helbig:
|
||||
*
|
||||
* Here is a patch that makes i4b work on an SMP:
|
||||
* The card (TELES 16.3) didn't interrupt on an SMP machine.
|
||||
* This is a gross workaround, but anyway it works *and* provides
|
||||
* some information as how to finally fix this problem.
|
||||
*/
|
||||
|
||||
HSCX_WRITE(0, H_MASK, 0xff);
|
||||
HSCX_WRITE(1, H_MASK, 0xff);
|
||||
ISAC_WRITE(I_MASKD, 0xff);
|
||||
ISAC_WRITE(I_MASK, 0xff);
|
||||
DELAY(100);
|
||||
HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
|
||||
HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
|
||||
ISAC_WRITE(I_MASKD, isacsx_imaskd);
|
||||
ISAC_WRITE(I_MASK, isacsx_imask);
|
||||
|
||||
/* XXXXXXXXXXXXXXXXXXX */
|
||||
|
||||
#endif /* I4B_SMP_WORKAROUND */
|
||||
|
||||
if(command < 0 || command > CMD_ILL)
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, ifpi2_printstate(sc));
|
||||
return;
|
||||
}
|
||||
|
||||
cmd = ISACSX_CIX0_LOW;
|
||||
|
||||
switch(command)
|
||||
{
|
||||
case CMD_TIM:
|
||||
NDBGL1(L1_I_CICO, "tx TIM in state %s", ifpi2_printstate(sc));
|
||||
cmd |= (ISACSX_CIX0_CTIM << 4);
|
||||
break;
|
||||
|
||||
case CMD_RS:
|
||||
NDBGL1(L1_I_CICO, "tx RS in state %s", ifpi2_printstate(sc));
|
||||
cmd |= (ISACSX_CIX0_CRS << 4);
|
||||
break;
|
||||
|
||||
case CMD_AR8:
|
||||
NDBGL1(L1_I_CICO, "tx AR8 in state %s", ifpi2_printstate(sc));
|
||||
cmd |= (ISACSX_CIX0_CAR8 << 4);
|
||||
break;
|
||||
|
||||
case CMD_AR10:
|
||||
NDBGL1(L1_I_CICO, "tx AR10 in state %s", ifpi2_printstate(sc));
|
||||
cmd |= (ISACSX_CIX0_CAR10 << 4);
|
||||
break;
|
||||
|
||||
case CMD_DIU:
|
||||
NDBGL1(L1_I_CICO, "tx DIU in state %s", ifpi2_printstate(sc));
|
||||
cmd |= (ISACSX_CIX0_CDIU << 4);
|
||||
break;
|
||||
}
|
||||
ISAC_WRITE(I_CIX0, cmd);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* L1 ISACSX initialization
|
||||
*---------------------------------------------------------------------------*/
|
||||
int
|
||||
ifpi2_isacsx_init(struct l1_softc *sc)
|
||||
{
|
||||
isacsx_imaskd = 0xff; /* disable all irqs */
|
||||
isacsx_imask = 0xff; /* disable all irqs */
|
||||
|
||||
ISAC_WRITE(I_MASKD, isacsx_imaskd);
|
||||
ISAC_WRITE(I_MASK, isacsx_imask);
|
||||
|
||||
/* the ISACSX only runs in IOM-2 mode */
|
||||
NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
|
||||
|
||||
/* TR_CONF0: Transceiver Configuration Register 0:
|
||||
* DIS_TR - transceiver enabled
|
||||
* EN_ICV - normal operation
|
||||
* EXLP - no external loop
|
||||
* LDD - automatic clock generation
|
||||
*/
|
||||
ISAC_WRITE(I_WTR_CONF0, 0);
|
||||
|
||||
/* TR_CONF2: Transceiver Configuration Register 1:
|
||||
* DIS_TX - transmitter enabled
|
||||
* PDS - phase deviation 2 S-bits
|
||||
* RLP - remote line loop open
|
||||
*/
|
||||
ISAC_WRITE(I_WTR_CONF2, 0);
|
||||
|
||||
/* MODED: Mode Register:
|
||||
* MDSx - transparent mode 0
|
||||
* TMD - timer mode = external
|
||||
* RAC - Receiver enabled
|
||||
* DIMx - digital i/f mode
|
||||
*/
|
||||
ISAC_WRITE(I_WMODED, ISACSX_MODED_MDS2|ISACSX_MODED_MDS1|ISACSX_MODED_RAC|ISACSX_MODED_DIM0);
|
||||
|
||||
/* enabled interrupts:
|
||||
* ===================
|
||||
* RME - receive message end
|
||||
* RPF - receive pool full
|
||||
* RPO - receive pool overflow
|
||||
* XPR - transmit pool ready
|
||||
* XMR - transmit message repeat
|
||||
* XDU - transmit data underrun
|
||||
*/
|
||||
|
||||
isacsx_imaskd = ISACSX_MASKD_LOW;
|
||||
ISAC_WRITE(I_MASKD, isacsx_imaskd);
|
||||
|
||||
/* enabled interrupts:
|
||||
* ===================
|
||||
* ICD - HDLC interrupt from D-channel
|
||||
* CIC - C/I channel change
|
||||
*/
|
||||
|
||||
isacsx_imask = ~(ISACSX_MASK_ICD | ISACSX_MASK_CIC);
|
||||
|
||||
ISAC_WRITE(I_MASK, isacsx_imask);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
#endif /* NIFPI2 > 0 */
|
||||
573
sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h
Normal file
573
sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h
Normal file
@ -0,0 +1,573 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Gary Jennejohn. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
* 4. Altered versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software and/or documentation.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*---------------------------------------------------------------------------
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef I4B_ISACSX_H_
|
||||
#define I4B_ISACSX_H_
|
||||
|
||||
#define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
|
||||
|
||||
#define ISACSX_V13 0x01
|
||||
|
||||
/*
|
||||
* definitions of registers and bits for the ISAC-SX ISDN chip.
|
||||
*/
|
||||
|
||||
typedef struct isacsx_reg {
|
||||
|
||||
/* 32 byte deep FIFO always first */
|
||||
|
||||
unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
|
||||
|
||||
/* most registers can be read/written, but have different names */
|
||||
/* so define a union with read/write names to make that clear */
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned char isacsx_istad;
|
||||
unsigned char isacsx_stard;
|
||||
unsigned char isacsx_moded;
|
||||
unsigned char isacsx_exmd1;
|
||||
unsigned char isacsx_timr1;
|
||||
unsigned char dummy_25;
|
||||
unsigned char isacsx_rbcld;
|
||||
unsigned char isacsx_rbchd;
|
||||
unsigned char isacsx_rstad;
|
||||
unsigned char isacsx_tmd;
|
||||
unsigned char dummy_2a;
|
||||
unsigned char dummy_2b;
|
||||
unsigned char dummy_2c;
|
||||
unsigned char dummy_2d;
|
||||
unsigned char isacsx_cir0;
|
||||
unsigned char isacsx_codr1;
|
||||
unsigned char isacsx_tr_conf0;
|
||||
unsigned char isacsx_tr_conf1;
|
||||
unsigned char isacsx_tr_conf2;
|
||||
unsigned char isacsx_tr_sta;
|
||||
unsigned char dummy_34;
|
||||
unsigned char isacsx_sqrr1;
|
||||
unsigned char isacsx_sqrr2;
|
||||
unsigned char isacsx_sqrr3;
|
||||
unsigned char isacsx_istatr;
|
||||
unsigned char isacsx_masktr;
|
||||
unsigned char dummy_3a;
|
||||
unsigned char dummy_3b;
|
||||
unsigned char isacsx_acgf2;
|
||||
unsigned char dummy_3d;
|
||||
unsigned char dummy_3e;
|
||||
unsigned char dummy_3f;
|
||||
unsigned char isacsx_cda10;
|
||||
unsigned char isacsx_cda11;
|
||||
unsigned char isacsx_cda20;
|
||||
unsigned char isacsx_cda21;
|
||||
unsigned char isacsx_cda_tsdp10;
|
||||
unsigned char isacsx_cda_tsdp11;
|
||||
unsigned char isacsx_cda_tsdp20;
|
||||
unsigned char isacsx_cda_tsdp21;
|
||||
unsigned char dummy_48;
|
||||
unsigned char dummy_49;
|
||||
unsigned char dummy_4a;
|
||||
unsigned char dummy_4b;
|
||||
unsigned char isacsx_tr_tsdp_bc1;
|
||||
unsigned char isacsx_tr_tsdp_bc2;
|
||||
unsigned char isacsx_cda1_cr;
|
||||
unsigned char isacsx_cda2_cr;
|
||||
unsigned char isacsx_tr_cr;
|
||||
unsigned char dummy_51;
|
||||
unsigned char dummy_52;
|
||||
unsigned char isacsx_dci_cr;
|
||||
unsigned char isacsx_mon_cr;
|
||||
unsigned char isacsx_sds_cr;
|
||||
unsigned char dummy_56;
|
||||
unsigned char isacsx_iom_cr;
|
||||
unsigned char isacsx_sti;
|
||||
unsigned char isacsx_msti;
|
||||
unsigned char isacsx_sds_conf;
|
||||
unsigned char isacsx_mcda;
|
||||
unsigned char isacsx_mor;
|
||||
unsigned char isacsx_mosr;
|
||||
unsigned char isacsx_mocr;
|
||||
unsigned char isacsx_msta;
|
||||
unsigned char isacsx_ista;
|
||||
unsigned char isacsx_auxi;
|
||||
unsigned char isacsx_mode1;
|
||||
unsigned char isacsx_mode2;
|
||||
unsigned char isacsx_id;
|
||||
unsigned char isacsx_timr2;
|
||||
unsigned char dummy_66;
|
||||
unsigned char dummy_67;
|
||||
unsigned char dummy_68;
|
||||
unsigned char dummy_69;
|
||||
unsigned char dummy_6a;
|
||||
unsigned char dummy_6b;
|
||||
unsigned char dummy_6c;
|
||||
unsigned char dummy_6d;
|
||||
unsigned char dummy_6e;
|
||||
unsigned char dummy_6f;
|
||||
} isacsx_r;
|
||||
struct {
|
||||
unsigned char isacsx_maskd;
|
||||
unsigned char isacsx_cmdrd;
|
||||
unsigned char isacsx_moded;
|
||||
unsigned char isacsx_exmd1;
|
||||
unsigned char isacsx_timr1;
|
||||
unsigned char isacsx_sap1;
|
||||
unsigned char isacsx_sap2;
|
||||
unsigned char isacsx_tei1;
|
||||
unsigned char isacsx_tei2;
|
||||
unsigned char isacsx_tmd;
|
||||
unsigned char dummy_2a;
|
||||
unsigned char dummy_2b;
|
||||
unsigned char dummy_2c;
|
||||
unsigned char dummy_2d;
|
||||
unsigned char isacsx_cix0;
|
||||
unsigned char isacsx_codx1;
|
||||
unsigned char isacsx_tr_conf0;
|
||||
unsigned char isacsx_tr_conf1;
|
||||
unsigned char isacsx_tr_conf2;
|
||||
unsigned char dummy_33;
|
||||
unsigned char dummy_34;
|
||||
unsigned char isacsx_sqrx1;
|
||||
unsigned char dummy_36;
|
||||
unsigned char dummy_37;
|
||||
unsigned char dummy_38;
|
||||
unsigned char isacsx_masktr;
|
||||
unsigned char dummy_3a;
|
||||
unsigned char dummy_3b;
|
||||
unsigned char isacsx_acgf2;
|
||||
unsigned char dummy_3d;
|
||||
unsigned char dummy_3e;
|
||||
unsigned char dummy_3f;
|
||||
unsigned char isacsx_cda10;
|
||||
unsigned char isacsx_cda11;
|
||||
unsigned char isacsx_cda20;
|
||||
unsigned char isacsx_cda21;
|
||||
unsigned char isacsx_cda_tsdp10;
|
||||
unsigned char isacsx_cda_tsdp11;
|
||||
unsigned char isacsx_cda_tsdp20;
|
||||
unsigned char isacsx_cda_tsdp21;
|
||||
unsigned char dummy_48;
|
||||
unsigned char dummy_49;
|
||||
unsigned char dummy_4a;
|
||||
unsigned char dummy_4b;
|
||||
unsigned char isacsx_tr_tsdp_bc1;
|
||||
unsigned char isacsx_tr_tsdp_bc2;
|
||||
unsigned char isacsx_cda1_cr;
|
||||
unsigned char isacsx_cda2_cr;
|
||||
unsigned char isacsx_tr_cr;
|
||||
unsigned char dummy_51;
|
||||
unsigned char dummy_52;
|
||||
unsigned char isacsx_dci_cr;
|
||||
unsigned char isacsx_mon_cr;
|
||||
unsigned char isacsx_sds_cr;
|
||||
unsigned char dummy_56;
|
||||
unsigned char isacsx_iom_cr;
|
||||
unsigned char isacsx_asti;
|
||||
unsigned char isacsx_msti;
|
||||
unsigned char isacsx_sds_conf;
|
||||
unsigned char dummy_5b;
|
||||
unsigned char isacsx_mox;
|
||||
unsigned char dummy_5d;
|
||||
unsigned char isacsx_mocr;
|
||||
unsigned char isacsx_mconf;
|
||||
unsigned char isacsx_mask;
|
||||
unsigned char isacsx_auxm;
|
||||
unsigned char isacsx_mode1;
|
||||
unsigned char isacsx_mode2;
|
||||
unsigned char isacsx_sres;
|
||||
unsigned char isacsx_timr2;
|
||||
unsigned char dummy_66;
|
||||
unsigned char dummy_67;
|
||||
unsigned char dummy_68;
|
||||
unsigned char dummy_69;
|
||||
unsigned char dummy_6a;
|
||||
unsigned char dummy_6b;
|
||||
unsigned char dummy_6c;
|
||||
unsigned char dummy_6d;
|
||||
unsigned char dummy_6e;
|
||||
unsigned char dummy_6f;
|
||||
} isacsx_w;
|
||||
} isacsx_rw;
|
||||
} isacsx_reg_t;
|
||||
|
||||
#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
|
||||
|
||||
/* ISACSX read registers */
|
||||
|
||||
#define i_istad isacsx_rw.isacsx_r.isacsx_istad
|
||||
#define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
|
||||
#define i_stard isacsx_rw.isacsx_r.isacsx_stard
|
||||
#define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
|
||||
#define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
|
||||
#define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
|
||||
#define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
|
||||
#define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
|
||||
#define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
|
||||
#define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
|
||||
#define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
|
||||
#define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
|
||||
#define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
|
||||
#define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
|
||||
#define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
|
||||
#define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
|
||||
#define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
|
||||
#define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
|
||||
#define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
|
||||
#define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
|
||||
#define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
|
||||
#define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
|
||||
#define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
|
||||
#define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
|
||||
#define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
|
||||
#define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
|
||||
#define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
|
||||
#define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
|
||||
#define i_sta isacsx_rw.isacsx_r.isacsx_sta
|
||||
#define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
|
||||
#define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
|
||||
#define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
|
||||
#define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
|
||||
#define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
|
||||
#define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
|
||||
#define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
|
||||
#define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
|
||||
#define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
|
||||
#define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
|
||||
#define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
|
||||
#define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
|
||||
#define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
|
||||
#define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
|
||||
#define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
|
||||
#define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
|
||||
#define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
|
||||
#define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
|
||||
#define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
|
||||
#define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
|
||||
#define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
|
||||
#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
|
||||
#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
|
||||
#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
|
||||
#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
|
||||
#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
|
||||
#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
|
||||
#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
|
||||
#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
|
||||
#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
|
||||
#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
|
||||
#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
|
||||
#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
|
||||
#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
|
||||
#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
|
||||
#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
|
||||
#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
|
||||
#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
|
||||
#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
|
||||
#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
|
||||
#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
|
||||
#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
|
||||
#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
|
||||
#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
|
||||
#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
|
||||
#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
|
||||
#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
|
||||
#define i_sti isacsx_rw.isacsx_r.isacsx_sti
|
||||
#define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
|
||||
#define i_msti isacsx_rw.isacsx_r.isacsx_msti
|
||||
#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
|
||||
#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
|
||||
#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
|
||||
#define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
|
||||
#define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
|
||||
#define i_mor isacsx_rw.isacsx_r.isacsx_mor
|
||||
#define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
|
||||
#define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
|
||||
#define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
|
||||
#define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
|
||||
#define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
|
||||
#define i_msta isacsx_rw.isacsx_r.isacsx_msta
|
||||
#define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
|
||||
#define i_ista isacsx_rw.isacsx_r.isacsx_ista
|
||||
#define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
|
||||
#define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
|
||||
#define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
|
||||
#define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
|
||||
#define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
|
||||
#define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
|
||||
#define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
|
||||
#define i_id isacsx_rw.isacsx_r.isacsx_id
|
||||
#define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
|
||||
#define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
|
||||
#define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
|
||||
|
||||
/* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
|
||||
/* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
|
||||
|
||||
#define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
|
||||
#define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
|
||||
#define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
|
||||
#define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
|
||||
#define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
|
||||
#define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
|
||||
#define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
|
||||
#define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
|
||||
#define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
|
||||
#define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
|
||||
#define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
|
||||
#define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
|
||||
#define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
|
||||
#define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
|
||||
#define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
|
||||
#define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
|
||||
#define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
|
||||
#define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
|
||||
#define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
|
||||
#define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
|
||||
#define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
|
||||
#define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
|
||||
#define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
|
||||
#define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
|
||||
#define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
|
||||
#define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
|
||||
#define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
|
||||
#define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
|
||||
#define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
|
||||
#define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
|
||||
#define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
|
||||
#define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
|
||||
#define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
|
||||
#define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
|
||||
#define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
|
||||
#define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
|
||||
#define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
|
||||
#define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
|
||||
#define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
|
||||
#define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
|
||||
#define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
|
||||
#define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
|
||||
#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
|
||||
#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
|
||||
#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
|
||||
#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
|
||||
#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
|
||||
#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
|
||||
#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
|
||||
#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
|
||||
#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
|
||||
#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
|
||||
#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
|
||||
#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
|
||||
#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
|
||||
#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
|
||||
#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
|
||||
#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
|
||||
#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
|
||||
#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
|
||||
#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
|
||||
#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
|
||||
#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
|
||||
#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
|
||||
#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
|
||||
#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
|
||||
#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
|
||||
#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
|
||||
#define i_asti isacsx_rw.isacsx_r.isacsx_asti
|
||||
#define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
|
||||
#define i_msti isacsx_rw.isacsx_r.isacsx_msti
|
||||
#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
|
||||
#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
|
||||
#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
|
||||
#define i_mox isacsx_rw.isacsx_w.isacsx_mox
|
||||
#define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
|
||||
#define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
|
||||
#define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
|
||||
#define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
|
||||
#define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
|
||||
#define i_mask isacsx_rw.isacsx_w.isacsx_mask
|
||||
#define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
|
||||
#define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
|
||||
#define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
|
||||
#define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
|
||||
#define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
|
||||
#define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
|
||||
#define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
|
||||
#define i_sres isacsx_rw.isacsx_w.isacsx_sres
|
||||
#define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
|
||||
#define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
|
||||
#define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
|
||||
|
||||
#define ISACSX_ISTAD_RME 0x80
|
||||
#define ISACSX_ISTAD_RPF 0x40
|
||||
#define ISACSX_ISTAD_RFO 0x20
|
||||
#define ISACSX_ISTAD_XPR 0x10
|
||||
#define ISACSX_ISTAD_XMR 0x08
|
||||
#define ISACSX_ISTAD_XDU 0x04
|
||||
|
||||
#define ISACSX_MASKD_RME 0x80
|
||||
#define ISACSX_MASKD_RPF 0x40
|
||||
#define ISACSX_MASKD_RFO 0x20
|
||||
#define ISACSX_MASKD_XPR 0x10
|
||||
#define ISACSX_MASKD_XMR 0x08
|
||||
#define ISACSX_MASKD_XDU 0x04
|
||||
/* these must always be set */
|
||||
#define ISACSX_MASKD_LOW 0x03
|
||||
#define ISACSX_MASKD_ALL 0xff
|
||||
|
||||
#define ISACSX_STARD_XDOV 0x80
|
||||
#define ISACSX_STARD_XFW 0x40
|
||||
#define ISACSX_STARD_RAC1 0x08
|
||||
#define ISACSX_STARD_XAC1 0x02
|
||||
|
||||
#define ISACSX_CMDRD_RMC 0x80
|
||||
#define ISACSX_CMDRD_RRES 0x40
|
||||
#define ISACSX_CMDRD_STI 0x10
|
||||
#define ISACSX_CMDRD_XTF 0x08
|
||||
#define ISACSX_CMDRD_XME 0x02
|
||||
#define ISACSX_CMDRD_XRES 0x01
|
||||
|
||||
#define ISACSX_MODED_MDS2 0x80
|
||||
#define ISACSX_MODED_MDS1 0x40
|
||||
#define ISACSX_MODED_MDS0 0x20
|
||||
#define ISACSX_MODED_RAC 0x08
|
||||
#define ISACSX_MODED_DIM2 0x04
|
||||
#define ISACSX_MODED_DIM1 0x02
|
||||
#define ISACSX_MODED_DIM0 0x01
|
||||
|
||||
/* default */
|
||||
#define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */
|
||||
#define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */
|
||||
/* default */
|
||||
#define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */
|
||||
#define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */
|
||||
#define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */
|
||||
#define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */
|
||||
#define ISACSX_EXMD1_SRA 0x10
|
||||
#define ISACSX_EXMD1_XCRC 0x08
|
||||
#define ISACSX_EXMD1_RCRC 0x04
|
||||
#define ISACSX_EXMD1_ITF 0x01
|
||||
|
||||
#define ISACSX_RSTAD_VFR 0x80
|
||||
#define ISACSX_RSTAD_RDO 0x40
|
||||
#define ISACSX_RSTAD_CRC 0x20
|
||||
#define ISACSX_RSTAD_RAB 0x10
|
||||
#define ISACSX_RSTAD_SA1 0x08
|
||||
#define ISACSX_RSTAD_SA0 0x04
|
||||
#define ISACSX_RSTAD_CR 0x02
|
||||
#define ISACSX_RSTAD_TA 0x01
|
||||
|
||||
#define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */
|
||||
|
||||
#define ISACSX_RBCHD_OV 0x10
|
||||
/* the other 4 bits are the high bits of the receive byte count */
|
||||
|
||||
#define ISACSX_CIR0_CIC0 0x08
|
||||
/* CODR0 >> 4 */
|
||||
#define ISACSX_CIR0_IPU 0x07
|
||||
#define ISACSX_CIR0_IDR 0x00
|
||||
#define ISACSX_CIR0_ISD 0x02
|
||||
#define ISACSX_CIR0_IDIS 0x03
|
||||
#define ISACSX_CIR0_IEI 0x06
|
||||
#define ISACSX_CIR0_IRSY 0x04
|
||||
#define ISACSX_CIR0_IARD 0x08
|
||||
#define ISACSX_CIR0_ITI 0x0a
|
||||
#define ISACSX_CIR0_IATI 0x0b
|
||||
#define ISACSX_CIR0_IAI8 0x0c
|
||||
#define ISACSX_CIR0_IAI10 0x0d
|
||||
#define ISACSX_CIR0_IDID 0x0f
|
||||
|
||||
#define ISACSX_IOM_CR_SPU 0x80
|
||||
#define ISACSX_IOM_CR_CI_CS 0x20
|
||||
#define ISACSX_IOM_CR_TIC_DIS 0x10
|
||||
#define ISACSX_IOM_CR_EN_BCL 0x08
|
||||
#define ISACSX_IOM_CR_CLKM 0x04
|
||||
#define ISACSX_IOM_CR_DIS_OD 0x02
|
||||
#define ISACSX_IOM_CR_DIS_IOM 0x01
|
||||
|
||||
#define ISACSX_CI_MASK 0x0f
|
||||
|
||||
#define ISACSX_CIX0_BAC 0x01
|
||||
/* in IOM-2 mode the low bits are always 1 */
|
||||
#define ISACSX_CIX0_LOW 0x0e
|
||||
/* C/I codes from bits 7-4 (>> 4 & 0xf) */
|
||||
/* the commands */
|
||||
#define ISACSX_CIX0_CTIM 0
|
||||
#define ISACSX_CIX0_CRS 0x01
|
||||
/* test mode only */
|
||||
#define ISACSX_CIX0_CSSSP 0x02
|
||||
/* test mode only */
|
||||
#define ISACSX_CIX0_CSSCP 0x03
|
||||
#define ISACSX_CIX0_CAR8 0x08
|
||||
#define ISACSX_CIX0_CAR10 0x09
|
||||
#define ISACSX_CIX0_CARL 0x0a
|
||||
#define ISACSX_CIX0_CDIU 0x0f
|
||||
|
||||
/* Interrupt, General Configuration Registers */
|
||||
|
||||
#define ISACSX_ISTA_ST 0x20
|
||||
#define ISACSX_ISTA_CIC 0x10
|
||||
#define ISACSX_ISTA_AUX 0x08
|
||||
#define ISACSX_ISTA_TRAN 0x04
|
||||
#define ISACSX_ISTA_MOS 0x02
|
||||
#define ISACSX_ISTA_ICD 0x01
|
||||
|
||||
#define ISACSX_MASK_ST 0x20
|
||||
#define ISACSX_MASK_CIC 0x10
|
||||
#define ISACSX_MASK_AUX 0x08
|
||||
#define ISACSX_MASK_TRAN 0x04
|
||||
#define ISACSX_MASK_MOS 0x02
|
||||
#define ISACSX_MASK_ICD 0x01
|
||||
|
||||
#define ISACSX_AUXI_EAW 0x20
|
||||
#define ISACSX_AUXI_WOV 0x10
|
||||
#define ISACSX_AUXI_TIN2 0x08
|
||||
#define ISACSX_AUXI_TIN1 0x04
|
||||
|
||||
#define ISACSX_AUXM_EAW 0x20
|
||||
#define ISACSX_AUXM_WOV 0x10
|
||||
#define ISACSX_AUXM_TIN2 0x08
|
||||
#define ISACSX_AUXM_TIN1 0x04
|
||||
|
||||
#define ISACSX_MODE1_WTC1 0x10
|
||||
#define ISACSX_MODE1_WTC2 0x08
|
||||
#define ISACSX_MODE1_CFS 0x04
|
||||
#define ISACSX_MODE1_RSS2 0x02
|
||||
#define ISACSX_MODE1_RSS1 0x01
|
||||
|
||||
#define ISACSX_MODE2_INT_POL 0x08
|
||||
#define ISACSX_MODE2_PPSDX 0x01
|
||||
|
||||
#define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
|
||||
|
||||
#endif /* I4B_ISACSX_H_ */
|
||||
244
sys/i4b/layer1/ifpi2/i4b_ifpi2_l1.c
Normal file
244
sys/i4b/layer1/ifpi2/i4b_ifpi2_l1.c
Normal file
@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
|
||||
* Copyright (c) 2001 Gary Jennejohn. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*---------------------------------------------------------------------------
|
||||
*
|
||||
* i4b_ifpi2_l1.c - AVM Fritz PCI Version 2 layer 1 handler
|
||||
* ---------------------------------------------
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "ifpi2.h"
|
||||
#include "pci.h"
|
||||
|
||||
#if (NIFPI2 > 0) && (NPCI > 0)
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/mbuf.h>
|
||||
#include <sys/socket.h>
|
||||
|
||||
|
||||
#include <net/if.h>
|
||||
|
||||
#include <machine/i4b_debug.h>
|
||||
#include <machine/i4b_ioctl.h>
|
||||
#include <machine/i4b_trace.h>
|
||||
|
||||
#include <i4b/layer1/isic/i4b_isic.h>
|
||||
#include <i4b/layer1/isic/i4b_isac.h>
|
||||
|
||||
#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
|
||||
|
||||
#include <i4b/layer1/i4b_l1.h>
|
||||
|
||||
#include <i4b/include/i4b_mbuf.h>
|
||||
#include <i4b/include/i4b_global.h>
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
*
|
||||
* L2 -> L1: PH-DATA-REQUEST
|
||||
* =========================
|
||||
*
|
||||
* parms:
|
||||
* unit physical interface unit number
|
||||
* m mbuf containing L2 frame to be sent out
|
||||
* freeflag MBUF_FREE: free mbuf here after having sent
|
||||
* it out
|
||||
* MBUF_DONTFREE: mbuf is freed by Layer 2
|
||||
* returns:
|
||||
* ==0 fail, nothing sent out
|
||||
* !=0 ok, frame sent out
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
int
|
||||
ifpi2_ph_data_req(int unit, struct mbuf *m, int freeflag)
|
||||
{
|
||||
u_char cmd;
|
||||
int s;
|
||||
struct l1_softc *sc = ifpi2_scp[unit];
|
||||
|
||||
#ifdef NOTDEF
|
||||
NDBGL1(L1_PRIM, "PH-DATA-REQ, unit %d, freeflag=%d", unit, freeflag);
|
||||
#endif
|
||||
|
||||
if(m == NULL) /* failsafe */
|
||||
return (0);
|
||||
|
||||
s = SPLI4B();
|
||||
|
||||
if(sc->sc_I430state == ST_F3) /* layer 1 not running ? */
|
||||
{
|
||||
NDBGL1(L1_I_ERR, "still in state F3!");
|
||||
ifpi2_ph_activate_req(unit);
|
||||
}
|
||||
|
||||
if(sc->sc_state & ISAC_TX_ACTIVE)
|
||||
{
|
||||
if(sc->sc_obuf2 == NULL)
|
||||
{
|
||||
sc->sc_obuf2 = m; /* save mbuf ptr */
|
||||
|
||||
if(freeflag)
|
||||
sc->sc_freeflag2 = 1; /* IRQ must mfree */
|
||||
else
|
||||
sc->sc_freeflag2 = 0; /* IRQ must not mfree */
|
||||
|
||||
NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", ifpi2_printstate(sc));
|
||||
|
||||
if(sc->sc_trace & TRACE_D_TX)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
hdr.unit = L0IFPIUNIT(unit);
|
||||
hdr.type = TRC_CH_D;
|
||||
hdr.dir = FROM_TE;
|
||||
hdr.count = ++sc->sc_trace_dcount;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
|
||||
}
|
||||
splx(s);
|
||||
return(1);
|
||||
}
|
||||
|
||||
NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", ifpi2_printstate(sc));
|
||||
|
||||
if(freeflag == MBUF_FREE)
|
||||
i4b_Dfreembuf(m);
|
||||
|
||||
splx(s);
|
||||
return (0);
|
||||
}
|
||||
|
||||
if(sc->sc_trace & TRACE_D_TX)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
hdr.unit = L0IFPIUNIT(unit);
|
||||
hdr.type = TRC_CH_D;
|
||||
hdr.dir = FROM_TE;
|
||||
hdr.count = ++sc->sc_trace_dcount;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
|
||||
}
|
||||
|
||||
sc->sc_state |= ISAC_TX_ACTIVE; /* set transmitter busy flag */
|
||||
|
||||
NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set");
|
||||
|
||||
sc->sc_freeflag = 0; /* IRQ must NOT mfree */
|
||||
|
||||
ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */
|
||||
|
||||
if(m->m_len > ISAC_FIFO_LEN) /* message > 32 bytes ? */
|
||||
{
|
||||
sc->sc_obuf = m; /* save mbuf ptr */
|
||||
sc->sc_op = m->m_data + ISAC_FIFO_LEN; /* ptr for irq hdl */
|
||||
sc->sc_ol = m->m_len - ISAC_FIFO_LEN; /* length for irq hdl */
|
||||
|
||||
if(freeflag)
|
||||
sc->sc_freeflag = 1; /* IRQ must mfree */
|
||||
|
||||
cmd = ISAC_CMDR_XTF;
|
||||
}
|
||||
else
|
||||
{
|
||||
sc->sc_obuf = NULL;
|
||||
sc->sc_op = NULL;
|
||||
sc->sc_ol = 0;
|
||||
|
||||
if(freeflag)
|
||||
i4b_Dfreembuf(m);
|
||||
|
||||
cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME;
|
||||
}
|
||||
|
||||
ISAC_WRITE(I_CMDR, cmd);
|
||||
ISACCMDRWRDELAY();
|
||||
|
||||
splx(s);
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
*
|
||||
* L2 -> L1: PH-ACTIVATE-REQUEST
|
||||
* =============================
|
||||
*
|
||||
* parms:
|
||||
* unit physical interface unit number
|
||||
*
|
||||
* returns:
|
||||
* ==0
|
||||
* !=0
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
int
|
||||
ifpi2_ph_activate_req(int unit)
|
||||
{
|
||||
struct l1_softc *sc = ifpi2_scp[unit];
|
||||
NDBGL1(L1_PRIM, "PH-ACTIVATE-REQ, unit %d", unit);
|
||||
ifpi2_next_state(sc, EV_PHAR);
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* command from the upper layers
|
||||
*---------------------------------------------------------------------------*/
|
||||
int
|
||||
ifpi2_mph_command_req(int unit, int command, void *parm)
|
||||
{
|
||||
struct l1_softc *sc = ifpi2_scp[unit];
|
||||
|
||||
switch(command)
|
||||
{
|
||||
case CMR_DOPEN: /* daemon running */
|
||||
NDBGL1(L1_PRIM, "unit %d, command = CMR_DOPEN", unit);
|
||||
sc->sc_enabled = 1;
|
||||
break;
|
||||
|
||||
case CMR_DCLOSE: /* daemon not running */
|
||||
NDBGL1(L1_PRIM, "unit %d, command = CMR_DCLOSE", unit);
|
||||
sc->sc_enabled = 0;
|
||||
break;
|
||||
|
||||
case CMR_SETTRACE:
|
||||
NDBGL1(L1_PRIM, "unit %d, command = CMR_SETTRACE, parm = %d", unit, (unsigned int)parm);
|
||||
sc->sc_trace = (unsigned int)parm;
|
||||
break;
|
||||
|
||||
default:
|
||||
NDBGL1(L1_ERROR, "ERROR, unknown command = %d, unit = %d, parm = %d", command, unit, (unsigned int)parm);
|
||||
break;
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
#endif /* NIFPI2 > 0 */
|
||||
516
sys/i4b/layer1/ifpi2/i4b_ifpi2_l1fsm.c
Normal file
516
sys/i4b/layer1/ifpi2/i4b_ifpi2_l1fsm.c
Normal file
@ -0,0 +1,516 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*---------------------------------------------------------------------------
|
||||
*
|
||||
* i4b_ifpi2_l1fsm.c - AVM Fritz PCI layer 1 I.430 state machine
|
||||
* ------------------------------------------------------------
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "ifpi2.h"
|
||||
#include "pci.h"
|
||||
|
||||
#if (NIFPI2 > 0) && (NPCI > 0)
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
|
||||
|
||||
#include <net/if.h>
|
||||
|
||||
#include <machine/i4b_debug.h>
|
||||
#include <machine/i4b_ioctl.h>
|
||||
#include <machine/i4b_trace.h>
|
||||
|
||||
#include <i4b/layer1/isic/i4b_isic.h>
|
||||
|
||||
#include <i4b/layer1/i4b_l1.h>
|
||||
|
||||
#include <i4b/include/i4b_global.h>
|
||||
|
||||
#include <i4b/include/i4b_mbuf.h>
|
||||
|
||||
#include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
|
||||
|
||||
#if DO_I4B_DEBUG
|
||||
static char *state_text[N_STATES] = {
|
||||
"F3 Deactivated",
|
||||
"F4 Awaiting Signal",
|
||||
"F5 Identifying Input",
|
||||
"F6 Synchronized",
|
||||
"F7 Activated",
|
||||
"F8 Lost Framing",
|
||||
"Illegal State"
|
||||
};
|
||||
|
||||
static char *event_text[N_EVENTS] = {
|
||||
"EV_PHAR PH_ACT_REQ",
|
||||
"EV_T3 Timer 3 expired",
|
||||
"EV_INFO0 INFO0 received",
|
||||
"EV_RSY Level Detected",
|
||||
"EV_INFO2 INFO2 received",
|
||||
"EV_INFO48 INFO4 received",
|
||||
"EV_INFO410 INFO4 received",
|
||||
"EV_DR Deactivate Req",
|
||||
"EV_PU Power UP",
|
||||
"EV_DIS Disconnected",
|
||||
"EV_EI Error Ind",
|
||||
"Illegal Event"
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Function prototypes */
|
||||
|
||||
static void timer3_expired (struct l1_softc *sc);
|
||||
static void T3_start (struct l1_softc *sc);
|
||||
static void T3_stop (struct l1_softc *sc);
|
||||
static void F_T3ex (struct l1_softc *sc);
|
||||
static void timer4_expired (struct l1_softc *sc);
|
||||
static void T4_start (struct l1_softc *sc);
|
||||
static void T4_stop (struct l1_softc *sc);
|
||||
static void F_AI8 (struct l1_softc *sc);
|
||||
static void F_AI10 (struct l1_softc *sc);
|
||||
static void F_I01 (struct l1_softc *sc);
|
||||
static void F_I02 (struct l1_softc *sc);
|
||||
static void F_I03 (struct l1_softc *sc);
|
||||
static void F_I2 (struct l1_softc *sc);
|
||||
static void F_ill (struct l1_softc *sc);
|
||||
static void F_NULL (struct l1_softc *sc);
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* I.430 Timer T3 expire function
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
timer3_expired(struct l1_softc *sc)
|
||||
{
|
||||
if(sc->sc_I430T3)
|
||||
{
|
||||
NDBGL1(L1_T_ERR, "state = %s", ifpi2_printstate(sc));
|
||||
sc->sc_I430T3 = 0;
|
||||
|
||||
/* XXX try some recovery here XXX */
|
||||
|
||||
ifpi2_recover(sc);
|
||||
|
||||
sc->sc_init_tries++; /* increment retry count */
|
||||
|
||||
/*XXX*/ if(sc->sc_init_tries > 4)
|
||||
{
|
||||
int s = SPLI4B();
|
||||
|
||||
sc->sc_init_tries = 0;
|
||||
|
||||
if(sc->sc_obuf2 != NULL)
|
||||
{
|
||||
i4b_Dfreembuf(sc->sc_obuf2);
|
||||
sc->sc_obuf2 = NULL;
|
||||
}
|
||||
if(sc->sc_obuf != NULL)
|
||||
{
|
||||
i4b_Dfreembuf(sc->sc_obuf);
|
||||
sc->sc_obuf = NULL;
|
||||
sc->sc_freeflag = 0;
|
||||
sc->sc_op = NULL;
|
||||
sc->sc_ol = 0;
|
||||
}
|
||||
|
||||
splx(s);
|
||||
|
||||
i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_NOL1ACC, 0, NULL);
|
||||
}
|
||||
|
||||
ifpi2_next_state(sc, EV_T3);
|
||||
}
|
||||
else
|
||||
{
|
||||
NDBGL1(L1_T_ERR, "expired without starting it ....");
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* I.430 Timer T3 start
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
T3_start(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
|
||||
sc->sc_I430T3 = 1;
|
||||
sc->sc_T3_callout = timeout((TIMEOUT_FUNC_T)timer3_expired,(struct l1_softc *)sc, 2*hz);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* I.430 Timer T3 stop
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
T3_stop(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
|
||||
|
||||
sc->sc_init_tries = 0; /* init connect retry count */
|
||||
|
||||
if(sc->sc_I430T3)
|
||||
{
|
||||
sc->sc_I430T3 = 0;
|
||||
untimeout((TIMEOUT_FUNC_T)timer3_expired,(struct l1_softc *)sc, sc->sc_T3_callout);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* I.430 Timer T3 expiry
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_T3ex(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_T3ex executing");
|
||||
if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
|
||||
i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* Timer T4 expire function
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
timer4_expired(struct l1_softc *sc)
|
||||
{
|
||||
if(sc->sc_I430T4)
|
||||
{
|
||||
NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
|
||||
sc->sc_I430T4 = 0;
|
||||
i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_PDEACT, 0, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
NDBGL1(L1_T_ERR, "expired without starting it ....");
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* Timer T4 start
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
T4_start(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
|
||||
sc->sc_I430T4 = 1;
|
||||
sc->sc_T4_callout = timeout((TIMEOUT_FUNC_T)timer4_expired,(struct l1_softc *)sc, hz);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* Timer T4 stop
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
T4_stop(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_T_MSG, "state = %s", ifpi2_printstate(sc));
|
||||
|
||||
if(sc->sc_I430T4)
|
||||
{
|
||||
sc->sc_I430T4 = 0;
|
||||
untimeout((TIMEOUT_FUNC_T)timer4_expired,(struct l1_softc *)sc, sc->sc_T4_callout);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received AI8
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_AI8(struct l1_softc *sc)
|
||||
{
|
||||
T4_stop(sc);
|
||||
|
||||
NDBGL1(L1_F_MSG, "FSM function F_AI8 executing");
|
||||
|
||||
if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
|
||||
i4b_l1_ph_activate_ind(L0IFPI2UNIT(sc->sc_unit));
|
||||
|
||||
T3_stop(sc);
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO4_8;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received AI10
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_AI10(struct l1_softc *sc)
|
||||
{
|
||||
T4_stop(sc);
|
||||
|
||||
NDBGL1(L1_F_MSG, "FSM function F_AI10 executing");
|
||||
|
||||
if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
|
||||
i4b_l1_ph_activate_ind(L0IFPI2UNIT(sc->sc_unit));
|
||||
|
||||
T3_stop(sc);
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO4_10;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received INFO 0 in states F3 .. F5
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_I01(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_I01 executing");
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO0;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received INFO 0 in state F6
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_I02(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_I02 executing");
|
||||
|
||||
if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
|
||||
i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO0;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received INFO 0 in state F7 or F8
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_I03(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_I03 executing");
|
||||
|
||||
if(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)
|
||||
i4b_l1_ph_deactivate_ind(L0IFPI2UNIT(sc->sc_unit));
|
||||
|
||||
T4_start(sc);
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO0;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: activate request
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_AR(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_AR executing");
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO1_8;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_TE;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
|
||||
ifpi2_isacsx_l1_cmd(sc, CMD_AR8);
|
||||
|
||||
T3_start(sc);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* FSM function: received INFO2
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_I2(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_I2 executing");
|
||||
|
||||
if(sc->sc_trace & TRACE_I)
|
||||
{
|
||||
i4b_trace_hdr_t hdr;
|
||||
char info = INFO2;
|
||||
|
||||
hdr.unit = L0IFPI2UNIT(sc->sc_unit);
|
||||
hdr.type = TRC_CH_I;
|
||||
hdr.dir = FROM_NT;
|
||||
hdr.count = 0;
|
||||
MICROTIME(hdr.time);
|
||||
i4b_l1_trace_ind(&hdr, 1, &info);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* illegal state default action
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_ill(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_ERR, "FSM function F_ill executing");
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* No action
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
F_NULL(struct l1_softc *sc)
|
||||
{
|
||||
NDBGL1(L1_F_MSG, "FSM function F_NULL executing");
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* layer 1 state transition table
|
||||
*---------------------------------------------------------------------------*/
|
||||
struct ifpi2_state_tab {
|
||||
void (*func) (struct l1_softc *sc); /* function to execute */
|
||||
int newstate; /* next state */
|
||||
} ifpi2_state_tab[N_EVENTS][N_STATES] = {
|
||||
|
||||
/* STATE: F3 F4 F5 F6 F7 F8 ILLEGAL STATE */
|
||||
/* -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
|
||||
/* EV_PHAR x*/ {{F_AR, ST_F4}, {F_NULL, ST_F4}, {F_NULL, ST_F5}, {F_NULL, ST_F6}, {F_ill, ST_ILL}, {F_NULL, ST_F8}, {F_ill, ST_ILL}},
|
||||
/* EV_T3 x*/ {{F_NULL, ST_F3}, {F_T3ex, ST_F3}, {F_T3ex, ST_F3}, {F_T3ex, ST_F3}, {F_NULL, ST_F7}, {F_NULL, ST_F8}, {F_ill, ST_ILL}},
|
||||
/* EV_INFO0 */ {{F_I01, ST_F3}, {F_I01, ST_F4}, {F_I01, ST_F5}, {F_I02, ST_F3}, {F_I03, ST_F3}, {F_I03, ST_F3}, {F_ill, ST_ILL}},
|
||||
/* EV_RSY x*/ {{F_NULL, ST_F3}, {F_NULL, ST_F5}, {F_NULL, ST_F5}, {F_NULL, ST_F8}, {F_NULL, ST_F8}, {F_NULL, ST_F8}, {F_ill, ST_ILL}},
|
||||
/* EV_INFO2 */ {{F_I2, ST_F6}, {F_I2, ST_F6}, {F_I2, ST_F6}, {F_I2, ST_F6}, {F_I2, ST_F6}, {F_I2, ST_F6}, {F_ill, ST_ILL}},
|
||||
/* EV_INFO48*/ {{F_AI8, ST_F7}, {F_AI8, ST_F7}, {F_AI8, ST_F7}, {F_AI8, ST_F7}, {F_NULL, ST_F7}, {F_AI8, ST_F7}, {F_ill, ST_ILL}},
|
||||
/* EV_INFO41*/ {{F_AI10, ST_F7}, {F_AI10, ST_F7}, {F_AI10, ST_F7}, {F_AI10, ST_F7}, {F_NULL, ST_F7}, {F_AI10, ST_F7}, {F_ill, ST_ILL}},
|
||||
/* EV_DR */ {{F_NULL, ST_F3}, {F_NULL, ST_F4}, {F_NULL, ST_F5}, {F_NULL, ST_F6}, {F_NULL, ST_F7}, {F_NULL, ST_F8}, {F_ill, ST_ILL}},
|
||||
/* EV_PU */ {{F_NULL, ST_F3}, {F_NULL, ST_F4}, {F_NULL, ST_F5}, {F_NULL, ST_F6}, {F_NULL, ST_F7}, {F_NULL, ST_F8}, {F_ill, ST_ILL}},
|
||||
/* EV_DIS */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}},
|
||||
/* EV_EI */ {{F_NULL, ST_F3}, {F_NULL, ST_F3}, {F_NULL, ST_F3}, {F_NULL, ST_F3}, {F_NULL, ST_F3}, {F_NULL, ST_F3}, {F_ill, ST_ILL}},
|
||||
/* EV_ILL */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}}
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
* event handler
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
ifpi2_next_state(struct l1_softc *sc, int event)
|
||||
{
|
||||
int currstate, newstate;
|
||||
|
||||
if(event >= N_EVENTS)
|
||||
panic("i4b_l1fsm.c: event >= N_EVENTS\n");
|
||||
|
||||
currstate = sc->sc_I430state;
|
||||
|
||||
if(currstate >= N_STATES)
|
||||
panic("i4b_l1fsm.c: currstate >= N_STATES\n");
|
||||
|
||||
newstate = ifpi2_state_tab[event][currstate].newstate;
|
||||
|
||||
if(newstate >= N_STATES)
|
||||
panic("i4b_l1fsm.c: newstate >= N_STATES\n");
|
||||
|
||||
NDBGL1(L1_F_MSG, "FSM event [%s]: [%s => %s]", event_text[event],
|
||||
state_text[currstate],
|
||||
state_text[newstate]);
|
||||
|
||||
(*ifpi2_state_tab[event][currstate].func)(sc);
|
||||
|
||||
if(newstate == ST_ILL)
|
||||
{
|
||||
newstate = ST_F3;
|
||||
NDBGL1(L1_F_ERR, "FSM Illegal State ERROR, oldstate = %s, newstate = %s, event = %s!",
|
||||
state_text[currstate],
|
||||
state_text[newstate],
|
||||
event_text[event]);
|
||||
}
|
||||
|
||||
sc->sc_I430state = newstate;
|
||||
}
|
||||
|
||||
#if DO_I4B_DEBUG
|
||||
/*---------------------------------------------------------------------------*
|
||||
* return pointer to current state description
|
||||
*---------------------------------------------------------------------------*/
|
||||
char *
|
||||
ifpi2_printstate(struct l1_softc *sc)
|
||||
{
|
||||
return((char *) state_text[sc->sc_I430state]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NIFPI2 > 0 */
|
||||
1439
sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c
Normal file
1439
sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user