Add the sekelton of support for the Power Management Controller.
This commit is contained in:
Warner Losh
parent
72ec44a573
commit
c44fe487c2
419
sys/arm/at91/at91_pmc.c
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419
sys/arm/at91/at91_pmc.c
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@ -0,0 +1,419 @@
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/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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static struct at91_pmc_softc {
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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struct resource *mem_res; /* Memory resource */
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device_t dev;
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int main_clock_hz;
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uint32_t pllb_init;
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} *pmc_softc;
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static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
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static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
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static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
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static struct at91_pmc_clock slck = {
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.name = "slck", // 32,768 Hz slow clock
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.hz = 32768,
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.refcnt = 1,
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.id = 0,
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.primary = 1,
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};
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static struct at91_pmc_clock main_ck = {
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.name = "main", // Main clock
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.refcnt = 0,
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.id = 1,
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.primary = 1,
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.pmc_mask = PMC_IER_MOSCS,
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};
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static struct at91_pmc_clock plla = {
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.name = "plla", // PLLA Clock, used for CPU clocking
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.parent = &main_ck,
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.refcnt = 1,
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.id = 0,
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.primary = 1,
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.pll = 1,
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.pmc_mask = PMC_IER_LOCKA,
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};
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static struct at91_pmc_clock pllb = {
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.name = "pllb", // PLLB Clock, used for USB functions
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.parent = &main_ck,
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.refcnt = 0,
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.id = 0,
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.primary = 1,
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.pll = 1,
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.pmc_mask = PMC_IER_LOCKB,
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.set_mode = &at91_pmc_set_pllb_mode,
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};
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static struct at91_pmc_clock udpck = {
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.name = "udpck",
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.parent = &pllb,
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.pmc_mask = PMC_SCER_UDP,
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.set_mode = at91_pmc_set_sys_mode
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};
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static struct at91_pmc_clock uhpck = {
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.name = "uhpck",
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.parent = &pllb,
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.pmc_mask = PMC_SCER_UHP,
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.set_mode = at91_pmc_set_sys_mode
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};
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static struct at91_pmc_clock mck = {
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.name = "mck",
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.pmc_mask = PMC_IER_MCKRDY,
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.refcnt = 0,
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};
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static struct at91_pmc_clock udc_clk = {
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.name = "udc_clk",
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.parent = &mck,
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.pmc_mask = 1 << AT91RM92_IRQ_UDP,
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.set_mode = &at91_pmc_set_periph_mode
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};
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static struct at91_pmc_clock ohci_clk = {
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.name = "ohci_clk",
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.parent = &mck,
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.pmc_mask = 1 << AT91RM92_IRQ_UDP,
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.set_mode = &at91_pmc_set_periph_mode
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};
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static struct at91_pmc_clock *const clock_list[] = {
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&slck,
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&main_ck,
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&plla,
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&pllb,
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&udpck,
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&uhpck,
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&mck,
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&udc_clk,
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&ohci_clk
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};
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static inline uint32_t
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RD4(struct at91_pmc_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->mem_res, off);
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}
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static inline void
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WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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uint32_t value;
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printf("Turning PLLB %#x %s\n", sc->pllb_init, on ? "on" : "off");
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if (on) {
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on = PMC_IER_LOCKB;
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value = sc->pllb_init;
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} else {
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value = 0;
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}
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WR4(sc, CKGR_PLLBR, value);
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while ((RD4(sc, PMC_SR) & PMC_IER_LOCKB) != on)
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continue;
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printf("Done!\n");
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}
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static void
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at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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printf("Turning SC %#x %s\n", clk->pmc_mask, on ? "on" : "off");
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WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
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if (on)
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while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
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continue;
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else
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while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
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continue;
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printf("Done SCSR is now: %#x!\n", RD4(sc, PMC_SCSR));
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}
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static void
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at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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printf("Turning PC %#x %s\n", clk->pmc_mask, on ? "on" : "off");
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WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
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if (on)
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while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
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continue;
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else
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while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
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continue;
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printf("Done PCSR is now: %#x!\n", RD4(sc, PMC_PCSR));
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}
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struct at91_pmc_clock *
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at91_pmc_clock_ref(const char *name)
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{
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int i;
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for (i = 0; i < sizeof(clock_list) / sizeof(clock_list[0]); i++)
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if (strcmp(name, clock_list[i]->name) == 0)
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return (clock_list[i]);
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return (NULL);
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}
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void
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at91_pmc_clock_deref(struct at91_pmc_clock *clk)
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{
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}
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void
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at91_pmc_clock_enable(struct at91_pmc_clock *clk)
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{
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/* XXX LOCKING? XXX */
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printf("Enable %s\n", clk->name);
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if (clk->parent)
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at91_pmc_clock_enable(clk->parent);
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if (clk->refcnt++ == 0 && clk->set_mode)
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clk->set_mode(clk, 1);
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}
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void
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at91_pmc_clock_disable(struct at91_pmc_clock *clk)
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{
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/* XXX LOCKING? XXX */
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if (--clk->refcnt == 0 && clk->set_mode)
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clk->set_mode(clk, 0);
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if (clk->parent)
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at91_pmc_clock_disable(clk->parent);
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}
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static int
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at91_pmc_pll_rate(int freq, uint32_t reg, int is_pllb)
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{
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uint32_t mul, div;
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div = reg & 0xff;
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mul = (reg >> 16) & 0x7ff;
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if (div != 0 && mul != 0) {
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freq /= div;
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freq *= mul + 1;
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} else {
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freq = 0;
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}
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if (is_pllb && (reg & (1 << 28)))
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freq >>= 1;
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return (freq);
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}
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static uint32_t
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at91_pmc_pll_calc(uint32_t main_freq, uint32_t out_freq)
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{
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uint32_t i, div = 0, mul = 0, diff = 1 << 30;
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unsigned ret = (out_freq > PMC_PLL_FAST_THRESH) ? 0xbe00 : 0x3e00;
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if (out_freq > PMC_PLL_MAX_OUT_FREQ)
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goto fail;
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for (i = 1; i < 256; i++) {
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int32_t diff1;
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uint32_t input, mul1;
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input = main_freq / i;
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if (input < PMC_PLL_MIN_IN_FREQ)
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break;
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if (input > PMC_PLL_MAX_IN_FREQ)
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continue;
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mul1 = out_freq / input;
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if (mul1 > PMC_PLL_MULT_MAX)
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continue;
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if (mul1 < PMC_PLL_MULT_MIN)
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break;
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diff1 = out_freq - input * mul1;
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if (diff1 < 0)
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diff1 = -diff1;
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if (diff > diff1) {
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diff = diff1;
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div = i;
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mul = mul1;
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if (diff == 0)
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break;
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}
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}
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if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
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goto fail;
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return ret | ((mul - 1) << 16) | div;
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fail:
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return 0;
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}
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static void
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at91_pmc_init_clock(struct at91_pmc_softc *sc, int main_clock)
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{
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uint32_t mckr;
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int freq;
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sc->main_clock_hz = main_clock;
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main_ck.hz = main_clock;
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plla.hz = at91_pmc_pll_rate(main_clock, RD4(sc, CKGR_PLLAR), 0);
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/*
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* Initialize the usb clock. This sets up pllb, but disables the
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* actual clock.
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*/
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sc->pllb_init = at91_pmc_pll_calc(main_clock, 48000000 * 2) |0x10000000;
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pllb.hz = at91_pmc_pll_rate(main_clock, sc->pllb_init, 1);
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WR4(sc, PMC_PCDR, (1 << AT91RM92_IRQ_UHP) | (1 << AT91RM92_IRQ_UDP));
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WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
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WR4(sc, CKGR_PLLBR, 0);
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WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
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/*
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* MCK and PCU derive from one of the primary clocks. Initialize
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* this relationship.
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*/
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mckr = RD4(sc, PMC_MCKR);
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mck.parent = clock_list[mckr & 0x3];
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mck.parent->refcnt++;
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freq = mck.parent->hz;
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freq /= 1 << ((mckr >> 2) & 3);
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mck.hz = freq / (1 + ((mckr >> 8) & 3));
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device_printf(sc->dev,
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"main clock: %d Hz PLLA: %d MHz CPU: %d MHz main %d MHz\n",
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sc->main_clock_hz,
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at91_pmc_pll_rate(main_clock, RD4(sc, CKGR_PLLAR), 0) / 1000000,
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freq / 1000000, mck.hz / 1000000);
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WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
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PMC_SCER_PCK3);
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/* XXX kludge, turn on all peripherals */
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WR4(sc, PMC_PCER, 0xffffffff);
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/* Disable all interrupts for PMC */
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WR4(sc, PMC_IDR, 0xffffffff);
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}
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static void
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at91_pmc_deactivate(device_t dev)
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{
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struct at91_pmc_softc *sc;
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sc = device_get_softc(dev);
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bus_generic_detach(sc->dev);
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if (sc->mem_res)
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bus_release_resource(dev, SYS_RES_IOPORT,
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rman_get_rid(sc->mem_res), sc->mem_res);
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sc->mem_res = 0;
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return;
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}
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static int
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at91_pmc_activate(device_t dev)
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{
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struct at91_pmc_softc *sc;
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int rid;
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sc = device_get_softc(dev);
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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goto errout;
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return (0);
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errout:
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at91_pmc_deactivate(dev);
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return (ENOMEM);
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}
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static int
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at91_pmc_probe(device_t dev)
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{
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device_set_desc(dev, "PMC");
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return (0);
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}
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static int
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at91_pmc_attach(device_t dev)
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{
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int err;
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pmc_softc = device_get_softc(dev);
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pmc_softc->dev = dev;
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if ((err = at91_pmc_activate(dev)) != 0)
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return err;
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at91_pmc_init_clock(pmc_softc, 10000000);
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return (0);
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}
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static device_method_t at91_pmc_methods[] = {
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DEVMETHOD(device_probe, at91_pmc_probe),
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DEVMETHOD(device_attach, at91_pmc_attach),
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{0, 0},
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};
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static driver_t at91_pmc_driver = {
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"at91_pmc",
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at91_pmc_methods,
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sizeof(struct at91_pmc_softc),
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};
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static devclass_t at91_pmc_devclass;
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DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass, 0, 0);
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120
sys/arm/at91/at91_pmcreg.h
Normal file
120
sys/arm/at91/at91_pmcreg.h
Normal file
@ -0,0 +1,120 @@
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/*-
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* Copyright (c) 2005 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PMCREG_H
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#define ARM_AT91_AT91_PMCREG_H
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/* Registers */
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#define PMC_SCER 0x00 /* System Clock Enable Register */
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#define PMC_SCDR 0x04 /* System Clock Disable Register */
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#define PMC_SCSR 0x08 /* System Clock Status Register */
|
||||
/* 0x0c reserved */
|
||||
#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
|
||||
#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
|
||||
#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
|
||||
/* 0x1c reserved */
|
||||
#define CKGR_MOR 0x20 /* Main Oscillator Register */
|
||||
#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */
|
||||
#define CKGR_PLLAR 0x28 /* PLL A Register */
|
||||
#define CKGR_PLLBR 0x2c /* PLL B Register */
|
||||
#define PMC_MCKR 0x30 /* Master Clock Register */
|
||||
/* 0x34 reserved */
|
||||
/* 0x38 reserved */
|
||||
/* 0x3c reserved */
|
||||
#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */
|
||||
#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */
|
||||
#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */
|
||||
#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */
|
||||
/* 0x50 reserved */
|
||||
/* 0x54 reserved */
|
||||
/* 0x58 reserved */
|
||||
/* 0x5c reserved */
|
||||
#define PMC_IER 0x60 /* Interrupt Enable Register */
|
||||
#define PMC_IDR 0x64 /* Interrupt Disable Register */
|
||||
#define PMC_SR 0x68 /* Status Register */
|
||||
#define PMC_IMR 0x6c /* Interrupt Mask Register */
|
||||
|
||||
/* PMC System Clock Enable Register */
|
||||
/* PMC System Clock Disable Register */
|
||||
/* PMC System Clock StatusRegister */
|
||||
#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */
|
||||
#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */
|
||||
#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */
|
||||
#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */
|
||||
#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */
|
||||
#define PMC_SCER_PCK1 (1UL << 10) /* PCK1: Programmable Clock out en */
|
||||
#define PMC_SCER_PCK2 (1UL << 11) /* PCK2: Programmable Clock out en */
|
||||
#define PMC_SCER_PCK3 (1UL << 12) /* PCK3: Programmable Clock out en */
|
||||
|
||||
/* PMC Peripheral Clock Enable Register */
|
||||
/* PMC Peripheral Clock Disable Register */
|
||||
/* PMC Peripheral Clock Status Register */
|
||||
/* Each bit here is 1 << peripheral number to enable/disable/status */
|
||||
|
||||
/* PMC Clock Generator Main Oscillator Register */
|
||||
#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */
|
||||
#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */
|
||||
#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */
|
||||
|
||||
/* PMC Clock Generator Main Clock Frequency Register */
|
||||
#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */
|
||||
#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */
|
||||
|
||||
/* PMC Interrupt Enable Register */
|
||||
/* PMC Interrupt Disable Register */
|
||||
/* PMC Status Register */
|
||||
/* PMC Interrupt Mask Register */
|
||||
#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */
|
||||
#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */
|
||||
#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */
|
||||
#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */
|
||||
#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */
|
||||
#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */
|
||||
#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */
|
||||
#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */
|
||||
|
||||
/*
|
||||
* PLL input frequency spec sheet says it must be between 1MHz and 32MHz,
|
||||
* but it works down as low as 100kHz, a frequency necessary for some
|
||||
* output frequencies to work.
|
||||
*/
|
||||
#define PMC_PLL_MIN_IN_FREQ 100000
|
||||
#define PMC_PLL_MAX_IN_FREQ 32000000
|
||||
|
||||
/*
|
||||
* PLL Max output frequency is 240MHz. The errata says 180MHz is the max
|
||||
* for some revisions of this part. Be more permissive and optimistic.
|
||||
*/
|
||||
#define PMC_PLL_MAX_OUT_FREQ 240000000
|
||||
|
||||
#define PMC_PLL_MULT_MIN 2
|
||||
#define PMC_PLL_MULT_MAX 2048
|
||||
|
||||
#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */
|
||||
|
||||
#define PMC_PLL_FAST_THRESH 155000000
|
||||
|
||||
#endif /* ARM_AT91_AT91_PMCREG_H */
|
||||
49
sys/arm/at91/at91_pmcvar.h
Normal file
49
sys/arm/at91/at91_pmcvar.h
Normal file
@ -0,0 +1,49 @@
|
||||
/*-
|
||||
* Copyright (c) 2005 M. Warner Losh. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
#ifndef ARM_AT91_AT91_PMCVAR_H
|
||||
#define ARM_AT91_AT91_PMCVAR_H
|
||||
|
||||
struct at91_pmc_clock
|
||||
{
|
||||
const char *name;
|
||||
uint32_t hz;
|
||||
struct at91_pmc_clock *parent;
|
||||
uint32_t pmc_mask;
|
||||
void (*set_mode)(struct at91_pmc_clock *, int);
|
||||
uint32_t refcnt;
|
||||
unsigned id:2;
|
||||
unsigned primary:1;
|
||||
unsigned pll:1;
|
||||
unsigned programmable:1;
|
||||
};
|
||||
|
||||
struct at91_pmc_clock *at91_pmc_clock_ref(const char *name);
|
||||
void at91_pmc_clock_deref(struct at91_pmc_clock *);
|
||||
void at91_pmc_clock_enable(struct at91_pmc_clock *);
|
||||
void at91_pmc_clock_disable(struct at91_pmc_clock *);
|
||||
|
||||
#endif /* ARM_AT91_AT91_PMCVAR_H */
|
||||
Loading…
Reference in New Issue
Block a user