Reimplement spl*() as function calls. Implement software interrupts.
This commit is contained in:
Doug Rabson
parent
9945598607
commit
c48c13cb5a
@ -23,7 +23,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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* $Id: ipl_funcs.c,v 1.1 1998/06/10 10:52:49 dfr Exp $
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*/
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#include <sys/types.h>
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@ -33,15 +33,108 @@
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#include <net/netisr.h>
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unsigned int netisr;
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void (*netisrs[32]) __P((void));
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u_int64_t ipending;
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int cpl;
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static void atomic_setbit(u_int64_t* p, u_int64_t bit)
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{
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u_int64_t temp;
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__asm__ __volatile__ (
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"1:\tldq_l %0,%2\n\t" /* load current mask value, asserting lock */
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"or %3,%0,%0\n\t" /* add our bits */
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"stq_c %0,%1\n\t" /* attempt to store */
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"beq %0,2f\n\t" /* if the store failed, spin */
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"br 3f\n" /* it worked, exit */
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"2:\tbr 1b\n" /* *p not updated, loop */
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"3:\tmb\n" /* it worked */
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: "=&r"(temp), "=m" (*p)
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: "m"(*p), "r"(bit)
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: "memory");
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}
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static u_int64_t atomic_readandclear(u_int64_t* p)
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{
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u_int64_t v, temp;
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__asm__ __volatile__ (
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"wmb\n" /* ensure pending writes have drained */
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"1:\tldq_l %0,%3\n\t" /* load current value, asserting lock */
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"ldiq %1,0\n\t" /* value to store */
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"stq_c %1,%2\n\t" /* attempt to store */
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"beq %1,2f\n\t" /* if the store failed, spin */
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"br 3f\n" /* it worked, exit */
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"2:\tbr 1b\n" /* *p not updated, loop */
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"3:\tmb\n" /* it worked */
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: "=&r"(v), "=&r"(temp), "=m" (*p)
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: "m"(*p)
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: "memory");
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return v;
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}
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void
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do_sir()
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{
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u_int64_t pend = atomic_readandclear(&ipending);
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#if 0
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/*
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* Later - no users of these yet.
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*/
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if (pend & (1 << SWI_TTY))
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swi_tty();
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if (pend & (1 << SWI_NET))
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swi_net();
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#endif
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if (pend & (1 << SWI_CLOCK))
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softclock();
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}
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void (*netisrs[32]) __P((void));
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u_int64_t ssir;
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#define GENSETSOFT(name, bit) \
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\
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void name(void) \
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{ \
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atomic_setbit(&ipending, (1 << bit)); \
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}
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GENSETSOFT(setsofttty, SWI_TTY)
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GENSETSOFT(setsoftnet, SWI_NET)
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GENSETSOFT(setsoftcamnet, SWI_CAMNET)
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GENSETSOFT(setsoftcambio, SWI_CAMBIO)
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GENSETSOFT(setsoftvm, SWI_VM)
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GENSETSOFT(setsoftclock, SWI_CLOCK)
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#define SPLDOWN(name, pri) \
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\
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int name(void) \
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{ \
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int s = alpha_pal_swpipl(ALPHA_PSL_IPL_##pri); \
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cpl = ALPHA_PSL_IPL_##pri; \
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return s; \
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}
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SPLDOWN(splsoftclock, SOFT)
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SPLDOWN(splsoftnet, SOFT)
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#define SPLUP(name, pri) \
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\
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int name(void) \
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{ \
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if (ALPHA_PSL_IPL_##pri > cpl) { \
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int s = alpha_pal_swpipl(ALPHA_PSL_IPL_##pri); \
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cpl = ALPHA_PSL_IPL_##pri; \
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return s; \
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} else \
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return cpl; \
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}
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SPLUP(splnet, IO)
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SPLUP(splbio, IO)
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SPLUP(splimp, IO)
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SPLUP(spltty, IO)
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SPLUP(splvm, IO)
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SPLUP(splclock, CLOCK)
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SPLUP(splstatclock, CLOCK)
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SPLUP(splhigh, HIGH)
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void
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spl0()
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@ -49,4 +142,16 @@ spl0()
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/* XXX soft interrupts here */
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alpha_pal_swpipl(ALPHA_PSL_IPL_0);
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cpl = ALPHA_PSL_IPL_0;
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}
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void
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splx(int s)
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{
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if (s) {
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alpha_pal_swpipl(s);
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cpl = s;
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} else
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spl0();
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}
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@ -1,4 +1,4 @@
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/* $Id$ */
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/* $Id: swtch.s,v 1.1 1998/06/10 10:53:23 dfr Exp $ */
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/* $NetBSD: locore.s,v 1.47 1998/03/22 07:26:32 thorpej Exp $ */
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/*
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@ -278,7 +278,7 @@ LEAF(switch_trampoline, 0)
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* exception_return: return from trap, exception, or syscall
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*/
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BSS(ssir, 8)
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IMPORT(ipending, 8)
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IMPORT(astpending, 8)
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LEAF(exception_return, 1) /* XXX should be NESTED */
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@ -290,7 +290,7 @@ Ler1: LDGP(pv)
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bne t0, Lrestoreregs /* != 0: can't do AST or SIR */
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/* see if we can do an SIR */
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ldq t1, ssir /* SIR pending? */
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ldq t1, ipending /* SIR pending? */
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beq t1, Lchkast /* no, try an AST*/
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/* We've got a SIR. */
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@ -23,53 +23,46 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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* $Id: ipl.h,v 1.1 1998/06/10 10:55:05 dfr Exp $
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*/
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#ifndef _MACHINE_IPL_H_
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#define _MACHINE_IPL_H_
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#include <machine/alpha_cpu.h>
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/* IPL-lowering/restoring macros */
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#define splx(s) \
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((s) == ALPHA_PSL_IPL_0 ? spl0() : alpha_pal_swpipl(s))
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#define splsoft() alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT)
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#define splsoftclock() splsoft()
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#define splsoftnet() splsoft()
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/* IPL-raising functions/macros */
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static __inline int _splraise __P((int)) __attribute__ ((unused));
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static __inline int
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_splraise(s)
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int s;
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{
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int cur = alpha_pal_rdps() & ALPHA_PSL_IPL_MASK;
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return (s > cur ? alpha_pal_swpipl(s) : cur);
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}
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#define splnet() _splraise(ALPHA_PSL_IPL_IO)
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#define splbio() _splraise(ALPHA_PSL_IPL_IO)
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#define splimp() _splraise(ALPHA_PSL_IPL_IO)
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#define spltty() _splraise(ALPHA_PSL_IPL_IO)
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#define splvm() _splraise(ALPHA_PSL_IPL_IO)
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#define splclock() _splraise(ALPHA_PSL_IPL_CLOCK)
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#define splstatclock() _splraise(ALPHA_PSL_IPL_CLOCK)
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#define splhigh() _splraise(ALPHA_PSL_IPL_HIGH)
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/*
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* simulated software interrupt register
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* Software interrupt bit numbers
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*/
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extern u_int64_t ssir;
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#define SWI_TTY 0
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#define SWI_NET 1
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#define SWI_CAMNET 2
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#define SWI_CAMBIO 3
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#define SWI_VM 4
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#define SWI_CLOCK 5
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#define SIR_NET 0x1
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#define SIR_CLOCK 0x2
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extern int splsoftclock(void);
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extern int splsoftnet(void);
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extern int splnet(void);
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extern int splbio(void);
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extern int splimp(void);
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extern int spltty(void);
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extern int splvm(void);
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extern int splclock(void);
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extern int splstatclock(void);
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extern int splhigh(void);
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#define setsoftnet() ssir |= SIR_NET
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#define setsoftclock() ssir |= SIR_CLOCK
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extern void setsofttty(void);
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extern void setsoftnet(void);
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extern void setsoftcamnet(void);
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extern void setsoftcambio(void);
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extern void setsoftvm(void);
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extern void setsoftclock(void);
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extern void spl0(void);
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extern void splx(int);
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#if 0
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/* XXX bogus */
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extern unsigned cpl; /* current priority level mask */
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#endif
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#endif /* !_MACHINE_MD_VAR_H_ */
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