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arch(7): small corrections for RISC-V

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Document that RISC-V supports multiple page sizes: 4K, 2M, and 1G.

RISC-V's long double is always 128-bits wide, therefore quad precision.

Mention __riscv_float_abi_soft, which can be used to differentiate between
riscv64 and riscv64sf in userland code.

MFC after:	3 days
This commit is contained in:
Mitchell Horne 2020-06-23 17:17:13 +00:00
parent 9f7e5bdad1
commit c4ef7cdb4d
1 changed files with 6 additions and 6 deletions
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12
share/man/man7/arch.7
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@ -26,7 +26,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd March 28, 2020
.Dd June 23, 2020
.Dt ARCH 7
.Os
.Sh NAME
@ -256,8 +256,8 @@ is 8 bytes on all supported architectures except i386.
.It powerpc Ta 4K
.It powerpcspe Ta 4K
.It powerpc64 Ta 4K
.It riscv64 Ta 4K
.It riscv64sf Ta 4K
.It riscv64 Ta 4K, 2M, 1G
.It riscv64sf Ta 4K, 2M, 1G
.El
.Ss Floating Point
.Bl -column -offset indent "Architecture" "float, double" "long double"
@ -279,8 +279,8 @@ is 8 bytes on all supported architectures except i386.
.It powerpc Ta hard Ta hard, double precision
.It powerpcspe Ta hard Ta hard, double precision
.It powerpc64 Ta hard Ta hard, double precision
.It riscv64 Ta hard Ta hard, double precision
.It riscv64sf Ta soft Ta soft, double precision
.It riscv64 Ta hard Ta hard, quad precision
.It riscv64sf Ta soft Ta soft, quad precision
.El
.Ss Default Tool Chain
.Fx
@ -358,7 +358,7 @@ Architecture-specific macros:
.It powerpcspe Ta Dv __powerpc__, Dv __SPE__
.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64, Dv __riscv_float_abi_soft
.El
.Pp
Compilers may define additional variants of architecture-specific macros.