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Update PCI drivers to no longer look at the MEMIO-enabled bit in the PCI

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command register.  The lazy BAR allocation code in FreeBSD sometimes
disables this bit when it detects a range conflict, and will re-enable
it on demand when a driver allocates the BAR.  Thus, the bit is no longer
a reliable indication of capability, and should not be checked.  This
results in the elimination of a lot of code from drivers, and also gives
the opportunity to simplify a lot of drivers to use a helper API to set
the busmaster enable bit.

This changes fixes some recent reports of disk controllers and their
associated drives/enclosures disappearing during boot.

Submitted by:	jhb
Reviewed by:	jfv, marius, achadd, achim
MFC after:	1 day
This commit is contained in:
Scott Long 2013-08-12 23:30:01 +00:00
parent 4dc63104ae
commit c68534f1d5
63 changed files with 110 additions and 522 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sys/dev/aacraid/aacraid_pci.c
View File

@ -169,18 +169,12 @@ aacraid_pci_attach(device_t dev)
/*
* Verify that the adapter is correctly set up in PCI space.
*/
command = pci_read_config(sc->aac_dev, PCIR_COMMAND, 2);
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
pci_enable_busmaster(dev);
command = pci_read_config(sc->aac_dev, PCIR_COMMAND, 2);
if (!(command & PCIM_CMD_BUSMASTEREN)) {
device_printf(sc->aac_dev, "can't enable bus-master feature\n");
goto out;
}
if ((command & PCIM_CMD_MEMEN) == 0) {
device_printf(sc->aac_dev, "memory window not available\n");
goto out;
}
/*
* Detect the hardware interface version, set up the bus interface

15
sys/dev/advansys/adw_pci.c
View File

@ -199,14 +199,13 @@ adw_pci_attach(device_t dev)
{
struct adw_softc *adw;
struct adw_pci_identity *entry;
u_int32_t command;
u_int16_t command;
struct resource *regs;
int regs_type;
int regs_id;
int error;
int zero;
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
entry = adw_find_pci_device(dev);
if (entry == NULL)
return (ENXIO);
@ -214,14 +213,11 @@ adw_pci_attach(device_t dev)
regs_type = 0;
regs_id = 0;
#ifdef ADW_ALLOW_MEMIO
if ((command & PCIM_CMD_MEMEN) != 0) {
regs_type = SYS_RES_MEMORY;
regs_id = ADW_PCI_MEMBASE;
regs = bus_alloc_resource_any(dev, regs_type,
&regs_id, RF_ACTIVE);
}
regs_type = SYS_RES_MEMORY;
regs_id = ADW_PCI_MEMBASE;
regs = bus_alloc_resource_any(dev, regs_type, &regs_id, RF_ACTIVE);
#endif
if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = ADW_PCI_IOBASE;
regs = bus_alloc_resource_any(dev, regs_type,
@ -296,6 +292,7 @@ adw_pci_attach(device_t dev)
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/2);
if ((command & PCIM_CMD_PERRESPEN) == 0)
adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)

16
sys/dev/aic7xxx/ahc_pci.c
View File

@ -139,12 +139,10 @@ int
ahc_pci_map_registers(struct ahc_softc *ahc)
{
struct resource *regs;
u_int command;
int regs_type;
int regs_id;
int allow_memio;
command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
regs = NULL;
regs_type = 0;
regs_id = 0;
@ -166,7 +164,7 @@ ahc_pci_map_registers(struct ahc_softc *ahc)
#endif
}
if ((allow_memio != 0) && (command & PCIM_CMD_MEMEN) != 0) {
if (allow_memio != 0) {
regs_type = SYS_RES_MEMORY;
regs_id = AHC_PCI_MEMADDR;
@ -190,16 +188,11 @@ ahc_pci_map_registers(struct ahc_softc *ahc)
bus_release_resource(ahc->dev_softc, regs_type,
regs_id, regs);
regs = NULL;
} else {
command &= ~PCIM_CMD_PORTEN;
aic_pci_write_config(ahc->dev_softc,
PCIR_COMMAND,
command, /*bytes*/1);
}
}
}
if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = AHC_PCI_IOADDR;
regs = bus_alloc_resource_any(ahc->dev_softc, regs_type,
@ -217,11 +210,6 @@ ahc_pci_map_registers(struct ahc_softc *ahc)
bus_release_resource(ahc->dev_softc, regs_type,
regs_id, regs);
regs = NULL;
} else {
command &= ~PCIM_CMD_MEMEN;
aic_pci_write_config(ahc->dev_softc,
PCIR_COMMAND,
command, /*bytes*/1);
}
}
}

15
sys/dev/aic7xxx/ahd_pci.c
View File

@ -143,13 +143,11 @@ ahd_pci_map_registers(struct ahd_softc *ahd)
{
struct resource *regs;
struct resource *regs2;
u_int command;
int regs_type;
int regs_id;
int regs_id2;
int allow_memio;
command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
regs = NULL;
regs2 = NULL;
regs_type = 0;
@ -165,8 +163,7 @@ ahd_pci_map_registers(struct ahd_softc *ahd)
allow_memio = 1;
}
if ((command & PCIM_CMD_MEMEN) != 0
&& (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0
if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0
&& allow_memio != 0) {
regs_type = SYS_RES_MEMORY;
@ -199,15 +196,10 @@ ahd_pci_map_registers(struct ahd_softc *ahd)
regs_id, regs);
regs = NULL;
AHD_CORRECTABLE_ERROR(ahd);
} else {
command &= ~PCIM_CMD_PORTEN;
aic_pci_write_config(ahd->dev_softc,
PCIR_COMMAND,
command, /*bytes*/1);
}
}
}
if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = AHD_PCI_IOADDR0;
regs = bus_alloc_resource_any(ahd->dev_softc, regs_type,
@ -233,9 +225,6 @@ ahd_pci_map_registers(struct ahd_softc *ahd)
}
ahd->tags[1] = rman_get_bustag(regs2);
ahd->bshs[1] = rman_get_bushandle(regs2);
command &= ~PCIM_CMD_MEMEN;
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
command, /*bytes*/1);
ahd->platform_data->regs_res_type[1] = regs_type;
ahd->platform_data->regs_res_id[1] = regs_id2;
ahd->platform_data->regs[1] = regs2;

23
sys/dev/amr/amr_pci.c
View File

@ -184,7 +184,6 @@ amr_pci_attach(device_t dev)
struct amr_softc *sc;
struct amr_ident *id;
int rid, rtype, error;
u_int32_t command;
debug_called(1);
@ -204,24 +203,8 @@ amr_pci_attach(device_t dev)
if ((id = amr_find_ident(dev)) == NULL)
return (ENXIO);
command = pci_read_config(dev, PCIR_COMMAND, 1);
if (id->flags & AMR_ID_QUARTZ) {
/*
* Make sure we are going to be able to talk to this board.
*/
if ((command & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "memory window not available\n");
return (ENXIO);
}
sc->amr_type |= AMR_TYPE_QUARTZ;
} else {
/*
* Make sure we are going to be able to talk to this board.
*/
if ((command & PCIM_CMD_PORTEN) == 0) {
device_printf(dev, "I/O window not available\n");
return (ENXIO);
}
}
if ((amr_force_sg32 == 0) && (id->flags & AMR_ID_DO_SG64) &&
@ -231,11 +214,7 @@ amr_pci_attach(device_t dev)
}
/* force the busmaster enable bit on */
if (!(command & PCIM_CMD_BUSMASTEREN)) {
device_printf(dev, "busmaster bit not set, enabling\n");
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
}
pci_enable_busmaster(dev);
/*
* Allocate the PCI register window.

14
sys/dev/an/if_an_pci.c
View File

@ -141,7 +141,6 @@ static int
an_attach_pci(dev)
device_t dev;
{
u_int32_t command;
struct an_softc *sc;
int flags, error = 0;
@ -153,19 +152,6 @@ an_attach_pci(dev)
sc->mpi350 = 1;
sc->port_rid = PCIR_BAR(0);
} else {
/*
* Map control/status registers.
*/
command = pci_read_config(dev, PCIR_COMMAND, 4);
command |= PCIM_CMD_PORTEN;
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
if (!(command & PCIM_CMD_PORTEN)) {
device_printf(dev, "failed to enable I/O ports!\n");
error = ENXIO;
goto fail;
}
sc->port_rid = AN_PCI_LOIO;
}
error = an_alloc_port(dev, sc->port_rid, 1);

3
sys/dev/arcmsr/arcmsr.c
View File

@ -4101,8 +4101,7 @@ static u_int32_t arcmsr_initialize(device_t dev)
pci_command |= PCIM_CMD_BUSMASTEREN;
pci_command |= PCIM_CMD_PERRESPEN;
pci_command |= PCIM_CMD_MWRICEN;
/* Enable Busmaster/Mem */
pci_command |= PCIM_CMD_MEMEN;
/* Enable Busmaster */
pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
switch(acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {

4
sys/dev/asr/asr.c
View File

@ -2428,9 +2428,7 @@ asr_attach(device_t dev)
return(ENXIO);
}
/* Enable if not formerly enabled */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, sizeof(char)) |
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN, sizeof(char));
pci_enable_busmaster(dev);
sc->ha_pciBusNum = pci_get_bus(dev);
sc->ha_pciDeviceNum = (pci_get_slot(dev) << 3) | pci_get_function(dev);

5
sys/dev/ata/ata-pci.c
View File

@ -98,11 +98,8 @@ ata_pci_attach(device_t dev)
ctlr->dev = dev;
/* if needed try to enable busmastering */
pci_enable_busmaster(dev);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
}
/* if busmastering mode "stuck" use it */
if ((cmd & PCIM_CMD_BUSMASTEREN) == PCIM_CMD_BUSMASTEREN) {

5
sys/dev/bktr/bktr_os.c
View File

@ -318,7 +318,6 @@ bktr_attach( device_t dev )
{
u_long latency;
u_long fun;
u_long val;
unsigned int rev;
unsigned int unit;
int error = 0;
@ -336,9 +335,7 @@ bktr_attach( device_t dev )
/*
* Enable bus mastering and Memory Mapped device
*/
val = pci_read_config(dev, PCIR_COMMAND, 4);
val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, val, 4);
pci_enable_busmaster(dev);
/*
* Map control/status registers.

19
sys/dev/buslogic/bt_pci.c
View File

@ -57,24 +57,19 @@ __FBSDID("$FreeBSD$");
static int
bt_pci_alloc_resources(device_t dev)
{
int command, type = 0, rid, zero;
int type = 0, rid, zero;
struct resource *regs = 0;
struct resource *irq = 0;
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
#if 0
/* XXX Memory Mapped I/O seems to cause problems */
if (command & PCIM_CMD_MEMEN) {
type = SYS_RES_MEMORY;
rid = BT_PCI_MEMADDR;
regs = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE);
}
type = SYS_RES_MEMORY;
rid = BT_PCI_MEMADDR;
regs = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE);
#else
if (!regs && (command & PCIM_CMD_PORTEN)) {
type = SYS_RES_IOPORT;
rid = BT_PCI_IOADDR;
regs = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE);
}
type = SYS_RES_IOPORT;
rid = BT_PCI_IOADDR;
regs = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE);
#endif
if (!regs)
return (ENOMEM);

16
sys/dev/dpt/dpt_pci.c
View File

@ -77,23 +77,17 @@ dpt_pci_attach (device_t dev)
dpt_softc_t * dpt;
int error = 0;
u_int32_t command;
dpt = device_get_softc(dev);
dpt->dev = dev;
dpt_alloc(dev);
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
#ifdef DPT_ALLOW_MMIO
if ((command & PCIM_CMD_MEMEN) != 0) {
dpt->io_rid = DPT_PCI_MEMADDR;
dpt->io_type = SYS_RES_MEMORY;
dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
&dpt->io_rid, RF_ACTIVE);
}
dpt->io_rid = DPT_PCI_MEMADDR;
dpt->io_type = SYS_RES_MEMORY;
dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
&dpt->io_rid, RF_ACTIVE);
#endif
if (dpt->io_res == NULL && (command & PCIM_CMD_PORTEN) != 0) {
if (dpt->io_res == NULL) {
dpt->io_rid = DPT_PCI_IOADDR;
dpt->io_type = SYS_RES_IOPORT;
dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,

10
sys/dev/e1000/if_em.c
View File

@ -2442,16 +2442,8 @@ em_identify_hardware(struct adapter *adapter)
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
(adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
device_printf(dev, "Memory Access and/or Bus Master bits "
"were not set!\n");
adapter->hw.bus.pci_cmd_word |=
(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND,
adapter->hw.bus.pci_cmd_word, 2);
}
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);

10
sys/dev/e1000/if_igb.c
View File

@ -2410,16 +2410,8 @@ igb_identify_hardware(struct adapter *adapter)
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
(adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
INIT_DEBUGOUT("Memory Access and/or Bus Master "
"bits were not set!\n");
adapter->hw.bus.pci_cmd_word |=
(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND,
adapter->hw.bus.pci_cmd_word, 2);
}
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);

10
sys/dev/e1000/if_lem.c
View File

@ -2119,16 +2119,8 @@ lem_identify_hardware(struct adapter *adapter)
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
(adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
device_printf(dev, "Memory Access and/or Bus Master bits "
"were not set!\n");
adapter->hw.bus.pci_cmd_word |=
(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND,
adapter->hw.bus.pci_cmd_word, 2);
}
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);

12
sys/dev/fatm/if_fatm.c
View File

@ -2829,21 +2829,13 @@ fatm_attach(device_t dev)
ifp->if_linkmiblen = sizeof(IFP2IFATM(sc->ifp)->mib);
/*
* Enable memory and bustmaster
* Enable busmaster
*/
cfg = pci_read_config(dev, PCIR_COMMAND, 2);
cfg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cfg, 2);
pci_enable_busmaster(dev);
/*
* Map memory
*/
cfg = pci_read_config(dev, PCIR_COMMAND, 2);
if (!(cfg & PCIM_CMD_MEMEN)) {
if_printf(ifp, "failed to enable memory mapping\n");
error = ENXIO;
goto fail;
}
sc->memid = 0x10;
sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid,
RF_ACTIVE);

2
sys/dev/firewire/fwohci_pci.c
View File

@ -242,7 +242,7 @@ fwohci_pci_init(device_t self)
uint16_t cmd;
cmd = pci_read_config(self, PCIR_COMMAND, 2);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
cmd |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
#if 1 /* for broken hardware */
cmd &= ~PCIM_CMD_MWRICEN;
#endif

2
sys/dev/fxp/if_fxp.c
View File

@ -452,7 +452,6 @@ fxp_attach(device_t dev)
* Enable bus mastering.
*/
pci_enable_busmaster(dev);
val = pci_read_config(dev, PCIR_COMMAND, 2);
/*
* Figure out which we should try first - memory mapping or i/o mapping?
@ -610,6 +609,7 @@ fxp_attach(device_t dev)
* is a valid cacheline size (8 or 16 dwords), then tell
* the board to turn on MWI.
*/
val = pci_read_config(dev, PCIR_COMMAND, 2);
if (val & PCIM_CMD_MWRICEN &&
pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
sc->flags |= FXP_FLAG_MWI_ENABLE;

8
sys/dev/hatm/if_hatm.c
View File

@ -1686,7 +1686,7 @@ hatm_attach(device_t dev)
* 4.2 BIOS Configuration
*/
v = pci_read_config(dev, PCIR_COMMAND, 2);
v |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
v |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
pci_write_config(dev, PCIR_COMMAND, v, 2);
/*
@ -1702,12 +1702,6 @@ hatm_attach(device_t dev)
/*
* Map memory
*/
v = pci_read_config(dev, PCIR_COMMAND, 2);
if (!(v & PCIM_CMD_MEMEN)) {
device_printf(dev, "failed to enable memory\n");
error = ENXIO;
goto failed;
}
sc->memid = PCIR_BAR(0);
sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid,
RF_ACTIVE);

25
sys/dev/ips/ips_pci.c
View File

@ -59,7 +59,6 @@ static int ips_pci_probe(device_t dev)
static int ips_pci_attach(device_t dev)
{
u_int32_t command;
ips_softc_t *sc;
@ -95,22 +94,18 @@ static int ips_pci_attach(device_t dev)
} else
goto error;
/* make sure busmastering is on */
command = pci_read_config(dev, PCIR_COMMAND, 1);
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 1);
pci_enable_busmaster(dev);
/* seting up io space */
sc->iores = NULL;
if(command & PCIM_CMD_MEMEN){
PRINTF(10, "trying MEMIO\n");
if(pci_get_device(dev) == IPS_COPPERHEAD_DEVICE_ID)
sc->rid = PCIR_BAR(1);
else
sc->rid = PCIR_BAR(0);
sc->iotype = SYS_RES_MEMORY;
sc->iores = bus_alloc_resource_any(dev, sc->iotype,
&sc->rid, RF_ACTIVE);
}
if(!sc->iores && command & PCIM_CMD_PORTEN){
PRINTF(10, "trying MEMIO\n");
if(pci_get_device(dev) == IPS_COPPERHEAD_DEVICE_ID)
sc->rid = PCIR_BAR(1);
else
sc->rid = PCIR_BAR(0);
sc->iotype = SYS_RES_MEMORY;
sc->iores = bus_alloc_resource_any(dev, sc->iotype, &sc->rid,
RF_ACTIVE);
if(!sc->iores){
PRINTF(10, "trying PORTIO\n");
sc->rid = PCIR_BAR(0);
sc->iotype = SYS_RES_IOPORT;

12
sys/dev/isp/isp_pci.c
View File

@ -706,13 +706,10 @@ isp_pci_attach(device_t dev)
pcs->irq = pcs->regs = NULL;
pcs->rgd = pcs->rtp = pcs->iqd = 0;
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if (cmd & m1) {
pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
}
if (pcs->regs == NULL && (cmd & m2)) {
pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
if (pcs->regs == NULL) {
pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
@ -891,6 +888,7 @@ isp_pci_attach(device_t dev)
/*
* Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
*/
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
if (IS_2300(isp)) { /* per QLogic errata */
cmd &= ~PCIM_CMD_INVEN;

4
sys/dev/iwn/if_iwn.c
View File

@ -483,12 +483,12 @@ iwn_attach(device_t dev)
pci_write_config(dev, 0x41, 0, 1);
/* Hardware bug workaround. */
reg = pci_read_config(dev, PCIR_COMMAND, 1);
reg = pci_read_config(dev, PCIR_COMMAND, 2);
if (reg & PCIM_CMD_INTxDIS) {
DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
__func__);
reg &= ~PCIM_CMD_INTxDIS;
pci_write_config(dev, PCIR_COMMAND, reg, 1);
pci_write_config(dev, PCIR_COMMAND, reg, 2);
}
/* Enable bus-mastering. */

10
sys/dev/ixgb/if_ixgb.c
View File

@ -1210,15 +1210,9 @@ ixgb_identify_hardware(struct adapter * adapter)
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
pci_enable_busmaster(dev);
adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
(adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
device_printf(dev,
"Memory Access and/or Bus Master bits were not set!\n");
adapter->hw.pci_cmd_word |=
(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND, adapter->hw.pci_cmd_word, 2);
}
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);
adapter->hw.device_id = pci_get_device(dev);

8
sys/dev/ixgbe/ixv.c
View File

@ -1561,14 +1561,8 @@ ixv_identify_hardware(struct adapter *adapter)
** Make sure BUSMASTER is set, on a VM under
** KVM it may not be and will break things.
*/
pci_enable_busmaster(dev);
pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
if (!((pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
(pci_cmd_word & PCIM_CMD_MEMEN))) {
INIT_DEBUGOUT("Memory Access and/or Bus Master "
"bits were not set!\n");
pci_cmd_word |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
}
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);

16
sys/dev/mfi/mfi_pci.c
View File

@ -187,7 +187,6 @@ mfi_pci_attach(device_t dev)
{
struct mfi_softc *sc;
struct mfi_ident *m;
uint32_t command;
int count, error;
sc = device_get_softc(dev);
@ -196,19 +195,8 @@ mfi_pci_attach(device_t dev)
m = mfi_find_ident(dev);
sc->mfi_flags = m->flags;
/* Verify that the adapter can be set up in PCI space */
command = pci_read_config(dev, PCIR_COMMAND, 2);
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
if ((command & PCIM_CMD_BUSMASTEREN) == 0) {
device_printf(dev, "Can't enable PCI busmaster\n");
return (ENXIO);
}
if ((command & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "PCI memory window not available\n");
return (ENXIO);
}
/* Ensure busmastering is enabled */
pci_enable_busmaster(dev);
/* Allocate PCI registers */
if ((sc->mfi_flags & MFI_FLAGS_1064R) ||

16
sys/dev/mly/mly.c
View File

@ -333,7 +333,6 @@ static int
mly_pci_attach(struct mly_softc *sc)
{
int i, error;
u_int32_t command;
debug_called(1);
@ -342,21 +341,8 @@ mly_pci_attach(struct mly_softc *sc)
/*
* Verify that the adapter is correctly set up in PCI space.
*
* XXX we shouldn't do this; the PCI code should.
*/
command = pci_read_config(sc->mly_dev, PCIR_COMMAND, 2);
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(sc->mly_dev, PCIR_COMMAND, command, 2);
command = pci_read_config(sc->mly_dev, PCIR_COMMAND, 2);
if (!(command & PCIM_CMD_BUSMASTEREN)) {
mly_printf(sc, "can't enable busmaster feature\n");
goto fail;
}
if ((command & PCIM_CMD_MEMEN) == 0) {
mly_printf(sc, "memory window not available\n");
goto fail;
}
pci_enable_busmaster(sc->mly_dev);
/*
* Allocate the PCI register window.

4
sys/dev/mn/if_mn.c
View File

@ -1346,9 +1346,9 @@ mn_attach (device_t self)
return(ENXIO);
}
u = pci_read_config(self, PCIR_COMMAND, 1);
u = pci_read_config(self, PCIR_COMMAND, 2);
printf("%x\n", u);
pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2);
#if 0
pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
#endif

14
sys/dev/mps/mps_pci.c
View File

@ -183,7 +183,6 @@ mps_pci_attach(device_t dev)
{
struct mps_softc *sc;
struct mps_ident *m;
uint16_t command;
int error;
sc = device_get_softc(dev);
@ -193,18 +192,7 @@ mps_pci_attach(device_t dev)
sc->mps_flags = m->flags;
/* Twiddle basic PCI config bits for a sanity check */
command = pci_read_config(dev, PCIR_COMMAND, 2);
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
if ((command & PCIM_CMD_BUSMASTEREN) == 0) {
mps_printf(sc, "Cannot enable PCI busmaster\n");
return (ENXIO);
}
if ((command & PCIM_CMD_MEMEN) == 0) {
mps_printf(sc, "PCI memory window not available\n");
return (ENXIO);
}
pci_enable_busmaster(dev);
/* Allocate the System Interface Register Set */
sc->mps_regs_rid = PCIR_BAR(1);

7
sys/dev/mpt/mpt_pci.c
View File

@ -389,16 +389,11 @@ mpt_pci_attach(device_t dev)
/* Print INFO level (if any) if bootverbose is set */
mpt->verbose += (bootverbose != 0)? 1 : 0;
}
/* Make sure memory access decoders are enabled */
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if ((cmd & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "Memory accesses disabled");
return (ENXIO);
}
/*
* Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
*/
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
cmd |=
PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;

33
sys/dev/mwl/if_mwl_pci.c
View File

@ -120,29 +120,6 @@ mwl_pci_probe(device_t dev)
return ENXIO;
}
static u_int32_t
mwl_pci_setup(device_t dev)
{
u_int32_t cmd;
/*
* Enable memory mapping and bus mastering.
*/
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cmd, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
if ((cmd & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "failed to enable memory mapping\n");
return 0;
}
if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
device_printf(dev, "failed to enable bus mastering\n");
return 0;
}
return 1;
}
static int
mwl_pci_attach(device_t dev)
{
@ -152,11 +129,8 @@ mwl_pci_attach(device_t dev)
sc->sc_dev = dev;
/*
* Enable memory mapping and bus mastering.
*/
if (!mwl_pci_setup(dev))
return 0;
pci_enable_busmaster(dev);
/*
* Setup memory-mapping of PCI registers.
*/
@ -285,8 +259,7 @@ mwl_pci_resume(device_t dev)
{
struct mwl_pci_softc *psc = device_get_softc(dev);
if (!mwl_pci_setup(dev))
return ENXIO;
pci_enable_busmaster(dev);
mwl_resume(&psc->sc_sc);

5
sys/dev/mxge/if_mxge.c
View File

@ -3827,7 +3827,7 @@ mxge_setup_cfg_space(mxge_softc_t *sc)
{
device_t dev = sc->dev;
int reg;
uint16_t cmd, lnk, pectl;
uint16_t lnk, pectl;
/* find the PCIe link width and set max read request to 4KB*/
if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
@ -3847,9 +3847,6 @@ mxge_setup_cfg_space(mxge_softc_t *sc)
/* Enable DMA and Memory space access */
pci_enable_busmaster(dev);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
cmd |= PCIM_CMD_MEMEN;
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
}
static uint32_t

5
sys/dev/pccbb/pccbb_pci.c
View File

@ -471,10 +471,7 @@ cbb_chipinit(struct cbb_softc *sc)
pci_write_config(sc->dev, PCIR_SUBBUS_2, sc->subbus, 1);
/* Enable memory access */
PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
| PCIM_CMD_MEMEN
| PCIM_CMD_PORTEN
| PCIM_CMD_BUSMASTEREN, 2);
pci_enable_busmaster(sc->dev);
/* disable Legacy IO */
switch (sc->chipset) {

4
sys/dev/pst/pst-pci.c
View File

@ -88,9 +88,7 @@ iop_pci_attach(device_t dev)
RF_SHAREABLE | RF_ACTIVE);
/* now setup the infrastructure to talk to the device */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 1) |
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN, 1);
pci_enable_busmaster(dev);
sc->ibase = rman_get_virtual(sc->r_mem);
sc->reg = (struct i2o_registers *)sc->ibase;

8
sys/dev/rp/rp_pci.c
View File

@ -151,7 +151,6 @@ rp_pciattach(device_t dev)
CONTROLLER_t *ctlp;
int unit;
int retval;
u_int32_t stcmd;
ctlp = device_get_softc(dev);
bzero(ctlp, sizeof(*ctlp));
@ -161,13 +160,6 @@ rp_pciattach(device_t dev)
ctlp->aiop2off = rp_pci_aiop2off;
ctlp->ctlmask = rp_pci_ctlmask;
/* Wake up the device. */
stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
if ((stcmd & PCIM_CMD_PORTEN) == 0) {
stcmd |= (PCIM_CMD_PORTEN);
pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
}
/* The IO ports of AIOPs for a PCI controller are continuous. */
ctlp->io_num = 1;
ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);

17
sys/dev/safe/safe.c
View File

@ -220,28 +220,15 @@ safe_attach(device_t dev)
{
struct safe_softc *sc = device_get_softc(dev);
u_int32_t raddr;
u_int32_t cmd, i, devinfo;
u_int32_t i, devinfo;
int rid;
bzero(sc, sizeof (*sc));
sc->sc_dev = dev;
/* XXX handle power management */
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cmd, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
if (!(cmd & PCIM_CMD_MEMEN)) {
device_printf(dev, "failed to enable memory mapping\n");
goto bad;
}
if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
device_printf(dev, "failed to enable bus mastering\n");
goto bad;
}
pci_enable_busmaster(dev);
/*
* Setup memory-mapping of PCI registers.

5
sys/dev/sound/pci/als4000.c
View File

@ -806,16 +806,13 @@ static int
als_pci_attach(device_t dev)
{
struct sc_info *sc;
u_int32_t data;
char status[SND_STATUSLEN];
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_als4000 softc");
sc->dev = dev;
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
pci_enable_busmaster(dev);
/*
* By default the power to the various components on the
* ALS4000 is entirely controlled by the pci powerstate. We

6
sys/dev/sound/pci/aureal.c
View File

@ -550,7 +550,6 @@ au_pci_probe(device_t dev)
static int
au_pci_attach(device_t dev)
{
u_int32_t data;
struct au_info *au;
int type[10];
int regid[10];
@ -565,10 +564,7 @@ au_pci_attach(device_t dev)
au = malloc(sizeof(*au), M_DEVBUF, M_WAITOK | M_ZERO);
au->unit = device_get_unit(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
j=0;
/* XXX dfr: is this strictly necessary? */

6
sys/dev/sound/pci/cmi.c
View File

@ -935,15 +935,11 @@ static int
cmi_attach(device_t dev)
{
struct sc_info *sc;
u_int32_t data;
char status[SND_STATUSLEN];
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
sc->dev = dev;
sc->regid = PCIR_BAR(0);

5
sys/dev/sound/pci/cs4281.c
View File

@ -760,16 +760,13 @@ cs4281_pci_attach(device_t dev)
{
struct sc_info *sc;
struct ac97_info *codec = NULL;
u_int32_t data;
char status[SND_STATUSLEN];
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
sc->dev = dev;
sc->type = pci_get_devid(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
pci_enable_busmaster(dev);
#if __FreeBSD_version > 500000
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {

8
sys/dev/sound/pci/csa.c
View File

@ -242,7 +242,6 @@ csa_probe(device_t dev)
static int
csa_attach(device_t dev)
{
u_int32_t stcmd;
sc_p scp;
csa_res *resp;
struct sndcard_func *func;
@ -254,12 +253,7 @@ csa_attach(device_t dev)
bzero(scp, sizeof(*scp));
scp->dev = dev;
/* Wake up the device. */
stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
}
pci_enable_busmaster(dev);
/* Allocate the resources. */
resp = &scp->res;

6
sys/dev/sound/pci/ds1.c
View File

@ -941,7 +941,6 @@ ds_pci_probe(device_t dev)
static int
ds_pci_attach(device_t dev)
{
u_int32_t data;
u_int32_t subdev, i;
struct sc_info *sc;
struct ac97_info *codec = NULL;
@ -954,10 +953,7 @@ ds_pci_attach(device_t dev)
sc->type = ds_finddev(pci_get_devid(dev), subdev);
sc->rev = pci_get_revid(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
sc->regid = PCIR_BAR(0);
sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,

6
sys/dev/sound/pci/emu10k1.c
View File

@ -2067,7 +2067,6 @@ emu_pci_attach(device_t dev)
{
struct ac97_info *codec = NULL;
struct sc_info *sc;
u_int32_t data;
int i, gotmic;
char status[SND_STATUSLEN];
@ -2081,10 +2080,7 @@ emu_pci_attach(device_t dev)
sc->nchans = sc->audigy ? 8 : 4;
sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK;
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
i = PCIR_BAR(0);
sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);

6
sys/dev/sound/pci/emu10kx.c
View File

@ -3040,7 +3040,6 @@ emu_pci_attach(device_t dev)
#if 0
struct emu_midiinfo *midiinfo;
#endif
uint32_t data;
int i;
int device_flags;
char status[255];
@ -3182,11 +3181,6 @@ emu_pci_attach(device_t dev)
if (sc->opcode_shift == 0)
goto bad;
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
i = PCIR_BAR(0);

6
sys/dev/sound/pci/envy24.c
View File

@ -2547,7 +2547,6 @@ envy24_alloc_resource(struct sc_info *sc)
static int
envy24_pci_attach(device_t dev)
{
u_int32_t data;
struct sc_info *sc;
char status[SND_STATUSLEN];
int err = 0;
@ -2567,10 +2566,7 @@ envy24_pci_attach(device_t dev)
sc->dev = dev;
/* initialize PCI interface */
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
/* allocate resources */
err = envy24_alloc_resource(sc);

6
sys/dev/sound/pci/envy24ht.c
View File

@ -2450,7 +2450,6 @@ envy24ht_alloc_resource(struct sc_info *sc)
static int
envy24ht_pci_attach(device_t dev)
{
u_int32_t data;
struct sc_info *sc;
char status[SND_STATUSLEN];
int err = 0;
@ -2471,10 +2470,7 @@ envy24ht_pci_attach(device_t dev)
sc->dev = dev;
/* initialize PCI interface */
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
/* allocate resources */
err = envy24ht_alloc_resource(sc);

9
sys/dev/sound/pci/es137x.c
View File

@ -1704,7 +1704,6 @@ es_init_sysctls(device_t dev)
static int
es_pci_attach(device_t dev)
{
uint32_t data;
struct es_info *es = NULL;
int mapped, i, numplay, dac_cfg;
char status[SND_STATUSLEN];
@ -1719,11 +1718,7 @@ es_pci_attach(device_t dev)
mapped = 0;
pci_enable_busmaster(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
if (mapped == 0 && (data & PCIM_CMD_MEMEN)) {
if (mapped == 0) {
es->regid = MEM_MAP_REG;
es->regtype = SYS_RES_MEMORY;
es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,
@ -1731,7 +1726,7 @@ es_pci_attach(device_t dev)
if (es->reg)
mapped++;
}
if (mapped == 0 && (data & PCIM_CMD_PORTEN)) {
if (mapped == 0) {
es->regid = PCIR_BAR(0);
es->regtype = SYS_RES_IOPORT;
es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,

6
sys/dev/sound/pci/fm801.c
View File

@ -573,7 +573,6 @@ fm801_init(struct fm801_info *fm801)
static int
fm801_pci_attach(device_t dev)
{
u_int32_t data;
struct ac97_info *codec = 0;
struct fm801_info *fm801;
int i;
@ -583,10 +582,7 @@ fm801_pci_attach(device_t dev)
fm801 = malloc(sizeof(*fm801), M_DEVBUF, M_WAITOK | M_ZERO);
fm801->type = pci_get_devid(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
for (i = 0; (mapped == 0) && (i < PCI_MAXMAPS_0); i++) {
fm801->regid = PCIR_BAR(i);

17
sys/dev/sound/pci/hdspe.c
View File

@ -242,20 +242,6 @@ hdspe_probe(device_t dev)
return (ENXIO);
}
static int
set_pci_config(device_t dev)
{
uint32_t data;
pci_enable_busmaster(dev);
data = pci_get_revid(dev);
data |= PCIM_CMD_PORTEN;
pci_write_config(dev, PCIR_COMMAND, data, 2);
return 0;
}
static int
hdspe_init(struct sc_info *sc)
{
@ -307,13 +293,12 @@ hdspe_attach(device_t dev)
device_printf(dev, "hdspe_attach()\n");
#endif
set_pci_config(dev);
sc = device_get_softc(dev);
sc->lock = snd_mtxcreate(device_get_nameunit(dev),
"snd_hdspe softc");
sc->dev = dev;
pci_enable_busmaster(dev);
rev = pci_get_revid(dev);
switch (rev) {
case PCI_REVISION_AIO:

9
sys/dev/sound/pci/maestro.c
View File

@ -1844,15 +1844,10 @@ agg_attach(device_t dev)
ess->curpwr = PCI_POWERSTATE_D3;
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
/* Allocate resources. */
if (data & PCIM_CMD_PORTEN)
reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &regid,
RF_ACTIVE);
reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &regid, RF_ACTIVE);
if (reg != NULL) {
ess->reg = reg;
ess->regid = regid;

5
sys/dev/sound/pci/maestro3.c
View File

@ -1317,7 +1317,6 @@ m3_pci_attach(device_t dev)
{
struct sc_info *sc;
struct ac97_info *codec = NULL;
u_int32_t data;
char status[SND_STATUSLEN];
struct m3_card_type *card;
int i, len, dacn, adcn;
@ -1351,9 +1350,7 @@ m3_pci_attach(device_t dev)
adcn = M3_RCHANS;
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
pci_enable_busmaster(dev);
sc->regid = PCIR_BAR(0);
sc->regtype = SYS_RES_MEMORY;

15
sys/dev/sound/pci/neomagic.c
View File

@ -599,7 +599,7 @@ nm_pci_probe(device_t dev)
{
struct sc_info *sc = NULL;
char *s = NULL;
u_int32_t subdev, i, data;
u_int32_t subdev, i;
subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
switch (pci_get_devid(dev)) {
@ -616,11 +616,6 @@ nm_pci_probe(device_t dev)
return ENXIO;
}
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, data |
PCIM_CMD_PORTEN | PCIM_CMD_MEMEN |
PCIM_CMD_BUSMASTEREN, 2);
sc->regid = PCIR_BAR(1);
sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->regid,
@ -628,7 +623,6 @@ nm_pci_probe(device_t dev)
if (!sc->reg) {
device_printf(dev, "unable to map register space\n");
pci_write_config(dev, PCIR_COMMAND, data, 2);
free(sc, M_DEVBUF);
return ENXIO;
}
@ -645,7 +639,6 @@ nm_pci_probe(device_t dev)
DEB(device_printf(dev, "subdev = 0x%x - badcard?\n",
subdev));
}
pci_write_config(dev, PCIR_COMMAND, data, 2);
bus_release_resource(dev, SYS_RES_MEMORY, sc->regid,
sc->reg);
free(sc, M_DEVBUF);
@ -670,7 +663,6 @@ nm_pci_probe(device_t dev)
static int
nm_pci_attach(device_t dev)
{
u_int32_t data;
struct sc_info *sc;
struct ac97_info *codec = 0;
char status[SND_STATUSLEN];
@ -679,10 +671,7 @@ nm_pci_attach(device_t dev)
sc->dev = dev;
sc->type = pci_get_devid(dev);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
sc->bufid = PCIR_BAR(0);
sc->buf = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->bufid,

12
sys/dev/sound/pci/solo.c
View File

@ -949,15 +949,9 @@ static int
ess_resume(device_t dev)
{
uint16_t ddma;
uint32_t data;
struct ess_info *sc = pcm_getdevinfo(dev);
ess_lock(sc);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
ddma = rman_get_start(sc->vc) | 1;
pci_write_config(dev, ESS_PCI_LEGACYCONTROL, 0x805f, 2);
pci_write_config(dev, ESS_PCI_DDMACONTROL, ddma, 2);
@ -988,13 +982,9 @@ ess_attach(device_t dev)
struct ess_info *sc;
char status[SND_STATUSLEN];
u_int16_t ddma;
u_int32_t data;
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
if (ess_alloc_resources(sc, dev))
goto no;

7
sys/dev/sound/pci/t4dwave.c
View File

@ -822,7 +822,6 @@ tr_pci_probe(device_t dev)
static int
tr_pci_attach(device_t dev)
{
u_int32_t data;
struct tr_info *tr;
struct ac97_info *codec = 0;
bus_addr_t lowaddr;
@ -831,6 +830,7 @@ tr_pci_attach(device_t dev)
#ifdef __sparc64__
device_t *children;
int nchildren;
u_int32_t data;
#endif
tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
@ -857,10 +857,7 @@ tr_pci_attach(device_t dev)
}
}
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
tr->regid = PCIR_BAR(0);
tr->regtype = SYS_RES_IOPORT;

6
sys/dev/sound/pci/via82c686.c
View File

@ -485,11 +485,7 @@ via_attach(device_t dev)
via->lock = snd_mtxcreate(device_get_nameunit(dev),
"snd_via82c686 softc");
/* Get resources */
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
/* Wake up and reset AC97 if necessary */
data = pci_read_config(dev, VIA_AC97STATUS, 1);

5
sys/dev/sound/pci/vibes.c
View File

@ -728,10 +728,7 @@ sv_attach(device_t dev) {
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
sc->dev = dev;
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
pci_enable_busmaster(dev);
#if __FreeBSD_version > 500000
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {

4
sys/dev/stge/if_stge.c
View File

@ -453,11 +453,11 @@ stge_attach(device_t dev)
pci_enable_busmaster(dev);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
val = pci_read_config(dev, PCIR_BAR(1), 4);
if ((val & 0x01) != 0)
if (PCI_BAR_IO(val))
sc->sc_spec = stge_res_spec_mem;
else {
val = pci_read_config(dev, PCIR_BAR(0), 4);
if ((val & 0x01) == 0) {
if (!PCI_BAR_IO(val)) {
device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
error = ENXIO;
goto fail;

18
sys/dev/sym/sym_hipd.c
View File

@ -8528,11 +8528,9 @@ sym_pci_attach(device_t dev)
/*
* Alloc/get/map/retrieve everything that deals with MMIO.
*/
if ((command & PCIM_CMD_MEMEN) != 0) {
int regs_id = SYM_PCI_MMIO;
np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&regs_id, RF_ACTIVE);
}
i = SYM_PCI_MMIO;
np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
RF_ACTIVE);
if (!np->mmio_res) {
device_printf(dev, "failed to allocate MMIO resources\n");
goto attach_failed;
@ -8555,11 +8553,8 @@ sym_pci_attach(device_t dev)
* User want us to use normal IO with PCI.
* Alloc/get/map/retrieve everything that deals with IO.
*/
if ((command & PCI_COMMAND_IO_ENABLE) != 0) {
int regs_id = SYM_PCI_IO;
np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&regs_id, RF_ACTIVE);
}
i = SYM_PCI_IO;
np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);
if (!np->io_res) {
device_printf(dev, "failed to allocate IO resources\n");
goto attach_failed;
@ -8571,8 +8566,7 @@ sym_pci_attach(device_t dev)
* If the chip has RAM.
* Alloc/get/map/retrieve the corresponding resources.
*/
if ((np->features & (FE_RAM|FE_RAM8K)) &&
(command & PCIM_CMD_MEMEN) != 0) {
if (np->features & (FE_RAM|FE_RAM8K)) {
int regs_id = SYM_PCI_RAM;
if (np->features & FE_64BIT)
regs_id = SYM_PCI_RAM64;

7
sys/dev/tdfx/tdfx_pci.c
View File

@ -145,7 +145,6 @@ tdfx_attach(device_t dev) {
* small, whole number.
*/
struct tdfx_softc *tdfx_info;
u_long val;
/* rid value tells bus_alloc_resource where to find the addresses of ports or
* of memory ranges in the PCI config space*/
int rid = PCIR_BAR(0);
@ -153,12 +152,6 @@ tdfx_attach(device_t dev) {
/* Increment the card counter (for the ioctl code) */
tdfx_count++;
/* Enable MemMap on Voodoo */
val = pci_read_config(dev, PCIR_COMMAND, 2);
val |= (PCIM_CMD_MEMEN);
pci_write_config(dev, PCIR_COMMAND, val, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
/* Fill the soft config struct with info about this device*/
tdfx_info = device_get_softc(dev);
tdfx_info->dev = dev;

17
sys/dev/twa/tw_osl_freebsd.c
View File

@ -284,7 +284,6 @@ static TW_INT32
twa_attach(device_t dev)
{
struct twa_softc *sc = device_get_softc(dev);
TW_UINT32 command;
TW_INT32 bar_num;
TW_INT32 bar0_offset;
TW_INT32 bar_size;
@ -323,22 +322,8 @@ twa_attach(device_t dev)
OID_AUTO, "driver_version", CTLFLAG_RD,
TW_OSL_DRIVER_VERSION_STRING, 0, "TWA driver version");
/* Make sure we are going to be able to talk to this board. */
command = pci_read_config(dev, PCIR_COMMAND, 2);
if ((command & PCIM_CMD_PORTEN) == 0) {
tw_osli_printf(sc, "error = %d",
TW_CL_SEVERITY_ERROR_STRING,
TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER,
0x2001,
"Register window not available",
ENXIO);
tw_osli_free_resources(sc);
return(ENXIO);
}
/* Force the busmaster enable bit on, in case the BIOS forgot. */
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
pci_enable_busmaster(dev);
/* Allocate the PCI register window. */
if ((error = tw_cl_get_pci_bar_info(sc->device_id, TW_CL_BAR_TYPE_MEM,

17
sys/dev/tws/tws.c
View File

@ -183,7 +183,7 @@ static int
tws_attach(device_t dev)
{
struct tws_softc *sc = device_get_softc(dev);
u_int32_t cmd, bar;
u_int32_t bar;
int error=0,i;
/* no tracing yet */
@ -224,14 +224,7 @@ tws_attach(device_t dev)
OID_AUTO, "driver_version", CTLFLAG_RD,
TWS_DRIVER_VERSION_STRING, 0, "TWS driver version");
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if ( (cmd & PCIM_CMD_PORTEN) == 0) {
tws_log(sc, PCI_COMMAND_READ);
goto attach_fail_1;
}
/* Force the busmaster enable bit on. */
cmd |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
pci_enable_busmaster(dev);
bar = pci_read_config(dev, TWS_PCI_BAR0, 4);
TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0);
@ -461,13 +454,9 @@ static int
tws_setup_irq(struct tws_softc *sc)
{
int messages;
u_int16_t cmd;
cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
switch(sc->intr_type) {
case TWS_INTx :
cmd = cmd & ~0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 0;
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
@ -479,8 +468,6 @@ tws_setup_irq(struct tws_softc *sc)
device_printf(sc->tws_dev, "Using legacy INTx\n");
break;
case TWS_MSI :
cmd = cmd | 0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 1;
messages = 1;

17
sys/dev/ubsec/ubsec.c
View File

@ -267,7 +267,7 @@ ubsec_attach(device_t dev)
{
struct ubsec_softc *sc = device_get_softc(dev);
struct ubsec_dma *dmap;
u_int32_t cmd, i;
u_int32_t i;
int rid;
bzero(sc, sizeof (*sc));
@ -312,20 +312,7 @@ ubsec_attach(device_t dev)
UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
}
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cmd, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
if (!(cmd & PCIM_CMD_MEMEN)) {
device_printf(dev, "failed to enable memory mapping\n");
goto bad;
}
if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
device_printf(dev, "failed to enable bus mastering\n");
goto bad;
}
pci_enable_busmaster(dev);
/*
* Setup memory-mapping of PCI registers.

12
sys/dev/wi/if_wi_pci.c
View File

@ -137,23 +137,13 @@ static int
wi_pci_attach(device_t dev)
{
struct wi_softc *sc;
u_int32_t command, wanted;
u_int32_t command;
u_int16_t reg;
int error;
int timeout;
sc = device_get_softc(dev);
command = pci_read_config(dev, PCIR_COMMAND, 4);
wanted = PCIM_CMD_PORTEN|PCIM_CMD_MEMEN;
command |= wanted;
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
if ((command & wanted) != wanted) {
device_printf(dev, "wi_pci_attach() failed to enable pci!\n");
return (ENXIO);
}
if (sc->wi_bus_type != WI_BUS_PCI_NATIVE) {
error = wi_alloc(dev, WI_PCI_IORES);
if (error)

4
sys/pci/ncr.c
View File

@ -3622,8 +3622,8 @@ ncr_attach (device_t dev)
pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);
}
if (!(command & (1<<4))) {
command |= (1<<4);
if (!(command & PCIM_CMD_MWRICEN)) {
command |= PCIM_CMD_MWRICEN;
printf("%s: setting PCI command write and invalidate.\n",
ncr_name(np));
pci_write_config(dev, PCIR_COMMAND, command, 2);