Remove more unused code and declarations, and add dire warnings to the 64-bit
atomic ops used by 32-bit kernels.
This commit is contained in:
Juli Mallett
parent
b6f97155cc
commit
c8b31c8f20
@ -217,7 +217,6 @@ do { \
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struct mips_cpuinfo;
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void mips_config_cache(struct mips_cpuinfo *);
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void mips_dcache_compute_align(void);
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#include <machine/cache_mipsNN.h>
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#endif /* _MACHINE_CACHE_H_ */
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@ -468,6 +468,5 @@ void insl(uint32_t *, uint32_t *,int);
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void outsb(uint8_t *, const uint8_t *,int);
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void outsw(uint16_t *, const uint16_t *,int);
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void outsl(uint32_t *, const uint32_t *,int);
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u_int loadandclear(volatile u_int *addr);
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#endif /* !_MACHINE_CPUFUNC_H_ */
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@ -124,10 +124,4 @@ struct trapframe {
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register_t fdummy;
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};
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/* REVISIT */
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struct frame *get_current_fp(void);
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#define get_next_fp(fp) (0)
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#define get_return_ptr(fp) (0)
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void get_stack_trace(u_int32_t depth, u_int32_t *trace);
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#endif /* !_MACHINE_FRAME_H_ */
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@ -54,12 +54,9 @@ extern vm_offset_t kernel_kseg0_end;
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void MipsSaveCurFPState(struct thread *);
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void fork_trampoline(void);
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void cpu_swapin(struct proc *);
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uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t);
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void MipsSwitchFPState(struct thread *, struct trapframe *);
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u_long kvtop(void *addr);
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int is_cacheable_mem(vm_paddr_t addr);
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void mips_generic_reset(void);
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void mips_wait(void);
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#define MIPS_DEBUG 0
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@ -163,7 +163,6 @@ void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr);
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void pmap_kremove(vm_offset_t va);
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void *pmap_kenter_temporary(vm_paddr_t pa, int i);
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void pmap_kenter_temporary_free(vm_paddr_t pa);
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int pmap_compute_pages_to_dump(void);
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void pmap_flush_pvcache(vm_page_t m);
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int pmap_emulate_modified(pmap_t pmap, vm_offset_t va);
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void pmap_grow_direct_page_cache(void);
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@ -80,11 +80,6 @@ struct mdproc {
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};
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#ifdef _KERNEL
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struct thread;
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void mips_cpu_switch(struct thread *, struct thread *, struct mtx *);
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void mips_cpu_throw(struct thread *, struct thread *);
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struct syscall_args {
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u_int code;
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struct sysent *callp;
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@ -397,17 +397,6 @@ mips_postboot_fixup(void)
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#endif
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}
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/*
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* Many SoCs have a means to reset the core itself. Others do not, or
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* the method is unknown to us. For those cases, we jump to the mips
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* reset vector and hope for the best. This works well in practice.
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*/
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void
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mips_generic_reset()
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{
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((void(*)(void))MIPS_RESET_EXC_VEC)();
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}
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#ifdef SMP
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void
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mips_pcpu_tlb_init(struct pcpu *pcpu)
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@ -940,154 +940,6 @@ LEAF(ffs)
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nop
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END(ffs)
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LEAF(get_current_fp)
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j ra
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move v0, s8
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END(get_current_fp)
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LEAF(loadandclear)
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.set noreorder
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1:
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ll v0, 0(a0)
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move t0, zero
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sc t0, 0(a0)
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beq t0, zero, 1b
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nop
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j ra
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nop
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END(loadandclear)
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#if 0
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/*
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* u_int32_t atomic_cmpset_32(u_int32_t *p, u_int32_t cmpval, u_int32_t newval)
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* Atomically compare the value stored at p with cmpval
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* and if the two values are equal, update value *p with
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* newval. Return zero if compare failed, non-zero otherwise
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*
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*/
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LEAF(atomic_cmpset_32)
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.set noreorder
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1:
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ll t0, 0(a0)
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move v0, zero
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bne t0, a1, 2f
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move t1, a2
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sc t1, 0(a0)
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beq t1, zero, 1b
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or v0, v0, 1
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2:
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j ra
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nop
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END(atomic_cmpset_32)
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/**
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* u_int32_t
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* atomic_readandclear_32(u_int32_t *a)
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* {
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* u_int32_t retval;
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* retval = *a;
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* *a = 0;
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* }
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*/
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LEAF(atomic_readandclear_32)
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.set noreorder
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1:
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ll t0, 0(a0)
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move t1, zero
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move v0, t0
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sc t1, 0(a0)
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beq t1, zero, 1b
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nop
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j ra
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nop
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END(atomic_readandclear_32)
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/**
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* void
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* atomic_set_32(u_int32_t *a, u_int32_t b)
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* {
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* *a |= b;
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* }
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*/
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LEAF(atomic_set_32)
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.set noreorder
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1:
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ll t0, 0(a0)
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or t0, t0, a1
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sc t0, 0(a0)
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beq t0, zero, 1b
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nop
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j ra
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nop
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END(atomic_set_32)
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/**
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* void
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* atomic_add_32(uint32_t *a, uint32_t b)
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* {
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* *a += b;
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* }
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*/
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LEAF(atomic_add_32)
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.set noreorder
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srl a0, a0, 2 # round down address to be 32-bit aligned
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sll a0, a0, 2
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1:
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ll t0, 0(a0)
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addu t0, t0, a1
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sc t0, 0(a0)
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beq t0, zero, 1b
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nop
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j ra
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nop
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END(atomic_add_32)
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/**
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* void
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* atomic_clear_32(u_int32_t *a, u_int32_t b)
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* {
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* *a &= ~b;
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* }
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*/
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LEAF(atomic_clear_32)
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.set noreorder
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srl a0, a0, 2 # round down address to be 32-bit aligned
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sll a0, a0, 2
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nor a1, zero, a1
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1:
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ll t0, 0(a0)
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and t0, t0, a1 # t1 has the new lower 16 bits
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sc t0, 0(a0)
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beq t0, zero, 1b
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nop
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j ra
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nop
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END(atomic_clear_32)
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/**
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* void
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* atomic_subtract_32(uint16_t *a, uint16_t b)
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* {
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* *a -= b;
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* }
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*/
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LEAF(atomic_subtract_32)
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.set noreorder
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srl a0, a0, 2 # round down address to be 32-bit aligned
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sll a0, a0, 2
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1:
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ll t0, 0(a0)
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subu t0, t0, a1
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sc t0, 0(a0)
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beq t0, zero, 1b
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nop
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j ra
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nop
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END(atomic_subtract_32)
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#endif
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/**
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* void
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* atomic_set_16(u_int16_t *a, u_int16_t b)
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@ -1259,6 +1111,15 @@ END(atomic_subtract_8)
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* NOPs in it for all processors. XXX
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*
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* Maybe it would be better to just leave this undefined in that case.
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*
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* XXX These routines are not safe in the case of a TLB miss on a1 or
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* a0 unless the trapframe is 64-bit, which it just isn't with O32.
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* If we take any exception, not just an interrupt, the upper
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* 32-bits will be clobbered. Use only N32 and N64 kernels if you
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* want to use 64-bit registers while interrupts are enabled or
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* with memory operations. Since this isn't even using load-linked
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* and store-conditional, perhaps it should just use two registers
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* instead, as is right and good with the O32 ABI.
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*/
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LEAF(atomic_store_64)
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mfc0 t1, MIPS_COP_0_STATUS
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@ -1455,58 +1316,6 @@ LEAF(casuptr)
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j ra
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END(casuptr)
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#ifdef CPU_CNMIPS
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/*
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* void octeon_enable_shadow(void)
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* turns on access to CC and CCRes
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*/
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LEAF(octeon_enable_shadow)
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li t1, 0x0000000f
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mtc0 t1, MIPS_COP_0_INFO
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jr ra
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nop
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END(octeon_enable_shadow)
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LEAF(octeon_get_shadow)
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mfc0 v0, MIPS_COP_0_INFO
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jr ra
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nop
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END(octeon_get_shadow)
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/*
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* octeon_set_control(addr, uint32_t val)
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*/
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LEAF(octeon_set_control)
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.set push
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or t1, a1, zero
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/* dmfc0 a1, 9, 7*/
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.word 0x40254807
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sd a1, 0(a0)
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or a1, t1, zero
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/* dmtc0 a1, 9, 7*/
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.word 0x40a54807
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jr ra
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nop
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.set pop
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END(octeon_set_control)
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/*
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* octeon_get_control(addr)
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*/
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LEAF(octeon_get_control)
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.set push
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.set mips64r2
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/* dmfc0 a1, 9, 7 */
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.word 0x40254807
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sd a1, 0(a0)
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jr ra
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nop
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.set pop
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END(octeon_get_control)
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#endif
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LEAF(mips3_ld)
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.set push
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.set noreorder
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@ -478,19 +478,6 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
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* that are needed.
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*/
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}
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/*
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* Convert kernel VA to physical address
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*/
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u_long
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kvtop(void *addr)
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{
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vm_offset_t va;
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va = pmap_kextract((vm_offset_t)addr);
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if (va == 0)
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panic("kvtop: zero page frame");
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return((intptr_t)va);
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}
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/*
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* Implement the pre-zeroed page mechanism.
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