Remove alpha reminiscence from altq.
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c90d5f1c37
@ -485,20 +485,6 @@ tbr_timeout(arg)
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CALLOUT_RESET(&tbr_callout, 1, tbr_timeout, (void *)0);
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else
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tbr_timer = 0; /* don't need tbr_timer anymore */
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#if defined(__alpha__) && !defined(ALTQ_NOPCC)
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{
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/*
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* XXX read out the machine dependent clock once a second
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* to detect counter wrap-around.
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*/
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static u_int cnt;
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if (++cnt >= hz) {
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(void)read_machclk();
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cnt = 0;
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}
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}
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#endif /* __alpha__ && !ALTQ_NOPCC */
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}
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/*
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@ -896,16 +882,9 @@ int machclk_usepcc;
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u_int32_t machclk_freq;
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u_int32_t machclk_per_tick;
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#ifdef __alpha__
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#ifdef __FreeBSD__
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extern u_int32_t cycles_per_sec; /* alpha cpu clock frequency */
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#elif defined(__NetBSD__) || defined(__OpenBSD__)
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extern u_int64_t cycles_per_usec; /* alpha cpu clock frequency */
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#endif
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#endif /* __alpha__ */
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#if defined(__i386__) && defined(__NetBSD__)
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extern u_int64_t cpu_tsc_freq;
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#endif /* __alpha__ */
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#endif
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#if (__FreeBSD_version >= 700035)
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/* Update TSC freq with the value indicated by the caller. */
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@ -938,8 +917,7 @@ init_machclk_setup(void)
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machclk_usepcc = 1;
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#if (!defined(__alpha__) && !defined(__amd64__) && !defined(__i386__)) || \
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defined(ALTQ_NOPCC)
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#if (!defined(__amd64__) && !defined(__i386__)) || defined(ALTQ_NOPCC)
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machclk_usepcc = 0;
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#endif
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#if defined(__FreeBSD__) && defined(SMP)
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@ -989,13 +967,7 @@ init_machclk(void)
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#elif defined(__OpenBSD__) && (defined(I586_CPU) || defined(I686_CPU))
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machclk_freq = pentium_mhz * 1000000;
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#endif
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#elif defined(__alpha__)
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#ifdef __FreeBSD__
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machclk_freq = cycles_per_sec;
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#elif defined(__NetBSD__) || defined(__OpenBSD__)
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machclk_freq = (u_int32_t)(cycles_per_usec * 1000000);
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#endif
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#endif /* __alpha__ */
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/*
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* if we don't know the clock frequency, measure it.
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@ -1043,23 +1015,6 @@ read_machclk(void)
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if (machclk_usepcc) {
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#if defined(__amd64__) || defined(__i386__)
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val = rdtsc();
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#elif defined(__alpha__)
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static u_int32_t last_pcc, upper;
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u_int32_t pcc;
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/*
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* for alpha, make a 64bit counter value out of the 32bit
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* alpha processor cycle counter.
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* read_machclk must be called within a half of its
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* wrap-around cycle (about 5 sec for 400MHz cpu) to properly
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* detect a counter wrap-around.
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* tbr_timeout calls read_machclk once a second.
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*/
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pcc = (u_int32_t)alpha_rpcc();
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if (pcc <= last_pcc)
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upper++;
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last_pcc = pcc;
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val = ((u_int64_t)upper << 32) + pcc;
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#else
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panic("read_machclk");
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#endif
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