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Teach PowerPC CPU identification routines to recognize e500 cores. Fix style

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issues in this area.

Approved by:	cognet (mentor)
MFp4:		e500
This commit is contained in:
Rafal Jaworowski 2008-02-25 00:09:23 +00:00
parent b390c31130
commit cb9bdc649d
3 changed files with 115 additions and 91 deletions
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11
sys/powerpc/include/hid.h
View File

@ -65,9 +65,9 @@
#define HID0_SGE 0x00000080 /* Enable store gathering */ #define HID0_SGE 0x00000080 /* Enable store gathering */
#define HID0_DCFA 0x00000040 /* Data cache flush assist */ #define HID0_DCFA 0x00000040 /* Data cache flush assist */
#define HID0_BTIC 0x00000020 /* Enable BTIC */ #define HID0_BTIC 0x00000020 /* Enable BTIC */
#define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */ #define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */
#define HID0_ABE 0x00000008 /* Enable address broadcast */ #define HID0_ABE 0x00000008 /* Enable address broadcast */
#define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */ #define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */
#define HID0_BHT 0x00000004 /* Enable branch history table */ #define HID0_BHT 0x00000004 /* Enable branch history table */
#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ #define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */
@ -85,6 +85,13 @@
"\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \ "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \
"\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI" "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
#define HID0_E500_BITMASK \
"\20" \
"\040EMCP\037b1\036b2\035b3\034b4\033b5\032b6\031b7" \
"\030DOZE\027NAP\026SLEEP\025b11\024b12\023b13\022b14\021b15" \
"\020b16\017TBEN\016SEL_TBCLK\015b19\014b20\013b21\012b22\011b23" \
"\010EN_MAS7_UPDATE\007DCFA\006b26\005b27\004b28\003b29\002b30\001NOPTI"
/* /*
* HID0 bit definitions per cpu model * HID0 bit definitions per cpu model
* *

2
sys/powerpc/include/spr.h
View File

@ -125,6 +125,8 @@
#define MPC7448 0x8004 #define MPC7448 0x8004
#define MPC7410 0x800c #define MPC7410 0x800c
#define MPC8245 0x8081 #define MPC8245 0x8081
#define FSL_E500v1 0x8020
#define FSL_E500v2 0x8021
#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */

193
sys/powerpc/powerpc/cpu.c
View File

@ -97,6 +97,8 @@ static const struct cputab models[] = {
{ "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN }, { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN },
{ "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN }, { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN },
{ "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN }, { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN },
{ "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN },
{ "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN },
{ "Unknown PowerPC CPU", 0, REVFMT_HEX } { "Unknown PowerPC CPU", 0, REVFMT_HEX }
}; };
@ -121,13 +123,18 @@ cpu_setup(u_int cpuid)
vers = pvr >> 16; vers = pvr >> 16;
rev = pvr; rev = pvr;
switch (vers) { switch (vers) {
case MPC7410: case MPC7410:
min = (pvr >> 0) & 0xff; min = (pvr >> 0) & 0xff;
maj = min <= 4 ? 1 : 2; maj = min <= 4 ? 1 : 2;
break; break;
default: case FSL_E500v1:
maj = (pvr >> 8) & 0xf; case FSL_E500v2:
min = (pvr >> 0) & 0xf; maj = (pvr >> 4) & 0xf;
min = (pvr >> 0) & 0xf;
break;
default:
maj = (pvr >> 8) & 0xf;
min = (pvr >> 0) & 0xf;
} }
for (cp = models; cp->version != 0; cp++) { for (cp = models; cp->version != 0; cp++) {
@ -146,15 +153,15 @@ cpu_setup(u_int cpuid)
printf("cpu%d: %s revision ", cpuid, name); printf("cpu%d: %s revision ", cpuid, name);
switch (revfmt) { switch (revfmt) {
case REVFMT_MAJMIN: case REVFMT_MAJMIN:
printf("%u.%u", maj, min); printf("%u.%u", maj, min);
break; break;
case REVFMT_HEX: case REVFMT_HEX:
printf("0x%04x", rev); printf("0x%04x", rev);
break; break;
case REVFMT_DEC: case REVFMT_DEC:
printf("%u", rev); printf("%u", rev);
break; break;
} }
hid0 = mfspr(SPR_HID0); hid0 = mfspr(SPR_HID0);
@ -163,96 +170,104 @@ cpu_setup(u_int cpuid)
* Configure power-saving mode. * Configure power-saving mode.
*/ */
switch (vers) { switch (vers) {
case MPC603: case MPC603:
case MPC603e: case MPC603e:
case MPC603ev: case MPC603ev:
case MPC604ev: case MPC604ev:
case MPC750: case MPC750:
case IBM750FX: case IBM750FX:
case MPC7400: case MPC7400:
case MPC7410: case MPC7410:
case MPC8240: case MPC8240:
case MPC8245: case MPC8245:
/* Select DOZE mode. */ /* Select DOZE mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
hid0 |= HID0_DOZE | HID0_DPM; hid0 |= HID0_DOZE | HID0_DPM;
#ifdef notyet #ifdef notyet
powersave = 1; powersave = 1;
#endif #endif
break; break;
case MPC7448: case MPC7448:
case MPC7447A: case MPC7447A:
case MPC7457: case MPC7457:
case MPC7455: case MPC7455:
case MPC7450: case MPC7450:
/* Enable the 7450 branch caches */ /* Enable the 7450 branch caches */
hid0 |= HID0_SGE | HID0_BTIC; hid0 |= HID0_SGE | HID0_BTIC;
hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
|| (pvr >> 16) == MPC7457) || (pvr >> 16) == MPC7457)
hid0 &= ~HID0_BTIC; hid0 &= ~HID0_BTIC;
/* Select NAP mode. */ /* Select NAP mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
hid0 |= HID0_NAP | HID0_DPM; hid0 |= HID0_NAP | HID0_DPM;
#ifdef notyet #ifdef notyet
powersave = 0; /* but don't use it */ powersave = 0; /* but don't use it */
#endif #endif
break; break;
default: default:
/* No power-saving mode is available. */ ; /* No power-saving mode is available. */ ;
} }
switch (vers) { switch (vers) {
case IBM750FX: case IBM750FX:
case MPC750: case MPC750:
hid0 &= ~HID0_DBP; /* XXX correct? */ hid0 &= ~HID0_DBP; /* XXX correct? */
hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
break; break;
case MPC7400: case MPC7400:
case MPC7410: case MPC7410:
hid0 &= ~HID0_SPD; hid0 &= ~HID0_SPD;
hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
hid0 |= HID0_EIEC; hid0 |= HID0_EIEC;
break; break;
case FSL_E500v1:
case FSL_E500v2:
hid0 |= HID0_EMCP;
break;
} }
mtspr(SPR_HID0, hid0); mtspr(SPR_HID0, hid0);
switch (vers) { switch (vers) {
case MPC7447A: case MPC7447A:
case MPC7448: case MPC7448:
case MPC7450: case MPC7450:
case MPC7455: case MPC7455:
case MPC7457: case MPC7457:
bitmask = HID0_7450_BITMASK; bitmask = HID0_7450_BITMASK;
break; break;
default: case FSL_E500v1:
bitmask = HID0_BITMASK; case FSL_E500v2:
break; bitmask = HID0_E500_BITMASK;
break;
default:
bitmask = HID0_BITMASK;
break;
} }
switch (vers) { switch (vers) {
case MPC750: case MPC750:
case IBM750FX: case IBM750FX:
case MPC7400: case MPC7400:
case MPC7410: case MPC7410:
case MPC7447A: case MPC7447A:
case MPC7448: case MPC7448:
case MPC7450: case MPC7450:
case MPC7455: case MPC7455:
case MPC7457: case MPC7457:
cpu_print_speed(); cpu_print_speed();
printf("\n"); printf("\n");
cpu_config_l2cr(cpuid, vers); cpu_config_l2cr(cpuid, vers);
break; break;
default:
default: printf("\n");
printf("\n"); break;
break;
} }
printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask); printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask);
@ -325,7 +340,7 @@ cpu_config_l2cr(u_int cpuid, uint16_t vers)
printf("cpu%d: ", cpuid); printf("cpu%d: ", cpuid);
if (l2cr & L2CR_L2E) { if (l2cr & L2CR_L2E) {
if (vers == MPC7450 || if (vers == MPC7450 ||
vers == MPC7455 || vers == MPC7455 ||
vers == MPC7457) { vers == MPC7457) {
u_int l3cr; u_int l3cr;