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Fix interrupt clear in pl011 uart receive function

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Clear the interrupt state before reading the input char from the
input FIFO. In the current code there is a window between the read
to the data register and the write to the the ICR, during which an
input char will not cause an interrupt.

This fixes the issue by which the serial port input on QEMU freezes
when using the emulated pl011 serial port.
This commit is contained in:
Jayachandran C. 2016-11-29 04:32:14 +00:00
parent 31ad7c11b3
commit cbee50f1df
1 changed files with 2 additions and 2 deletions
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4
sys/dev/uart/uart_dev_pl011.c
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@ -443,6 +443,8 @@ uart_pl011_bus_receive(struct uart_softc *sc)
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
break;
}
__uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
xc = __uart_getreg(bas, UART_DR);
rx = xc & 0xff;
@ -451,8 +453,6 @@ uart_pl011_bus_receive(struct uart_softc *sc)
if (xc & DR_PE)
rx |= UART_STAT_PARERR;
__uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
uart_rx_put(sc, rx);
ints = __uart_getreg(bas, UART_MIS);
}