diff --git a/sys/arm/arm/cpufunc_asm.S b/sys/arm/arm/cpufunc_asm.S index 20f2efb91185..7d56d84adfdc 100644 --- a/sys/arm/arm/cpufunc_asm.S +++ b/sys/arm/arm/cpufunc_asm.S @@ -134,26 +134,6 @@ END(cpufunc_control) /* Random odd functions */ -/* - * Function to get the offset of a stored program counter from the - * instruction doing the store. This offset is defined to be the same - * for all STRs and STMs on a given implementation. Code based on - * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work - * in 26-bit modes as well. - */ -ENTRY(get_pc_str_offset) - mov ip, sp - stmfd sp!, {fp, ip, lr, pc} - sub fp, ip, #4 - sub sp, sp, #4 - mov r1, pc /* R1 = addr of following STR */ - mov r0, r0 - str pc, [sp] /* [SP] = . + offset */ - ldr r0, [sp] - sub r0, r0, r1 - ldmdb fp, {fp, sp, pc} -END(get_pc_str_offset) - /* Allocate and lock a cacheline for the specified address. */ #define CPWAIT_BRANCH \ diff --git a/sys/arm/arm/cpufunc_asm_arm11.S b/sys/arm/arm/cpufunc_asm_arm11.S deleted file mode 100644 index 50d6eaa30bc8..000000000000 --- a/sys/arm/arm/cpufunc_asm_arm11.S +++ /dev/null @@ -1,46 +0,0 @@ -/* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */ - -/* - * Copyright (c) 2002, 2005 ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM11 assembly functions for CPU / MMU / TLB specific operations - * - * XXX We make no attempt at present to take advantage of the v6 memory - * architecture or physically tagged cache. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * Other functions - */ -ENTRY(arm11_drain_writebuf) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mov pc, lr -END(arm11_drain_writebuf) diff --git a/sys/arm/arm/cpufunc_asm_armv6.S b/sys/arm/arm/cpufunc_asm_armv6.S deleted file mode 100644 index 02b8a0cd0390..000000000000 --- a/sys/arm/arm/cpufunc_asm_armv6.S +++ /dev/null @@ -1,64 +0,0 @@ -/* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */ - -/* - * Copyright (c) 2002, 2005 ARM Limited - * Portions Copyright (c) 2007 Microsoft - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARMv6 assembly functions for manipulating caches. - * These routines can be used by any core that supports the mcrr address - * range operations. - */ - -/* - * $FreeBSD$ - */ - -#include - - .arch armv6 - -/* - * Cache operations. - */ - -#ifdef ELF_TRAMPOLINE -/* LINTSTUB: void armv6_idcache_wbinv_all(void); */ -ENTRY_NP(armv6_idcache_wbinv_all) - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache purging code. - */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - - /* Purge Dcache. */ - mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_idcache_wbinv_all) -#endif /* ELF_TRAMPOLINE */ diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index c6f14fe78da8..62ee8f089cc7 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -37,91 +37,8 @@ __FBSDID("$FreeBSD$"); .cpu cortex-a8 -#ifdef ELF_TRAMPOLINE -.Lcoherency_level: - .word _C_LABEL(arm_cache_loc) -.Lcache_type: - .word _C_LABEL(arm_cache_type) -.Lway_mask: - .word 0x3ff -.Lmax_index: - .word 0x7fff - -/* Based on algorithm from ARM Architecture Reference Manual */ -ENTRY(armv7_dcache_wbinv_all) - stmdb sp!, {r4, r5, r6, r7, r8, r9} - - /* Get cache level */ - ldr r0, .Lcoherency_level - ldr r3, [r0] - cmp r3, #0 - beq Finished - /* For each cache level */ - mov r8, #0 -Loop1: - /* Get cache type for given level */ - mov r2, r8, lsl #2 - add r2, r2, r2 - ldr r0, .Lcache_type - ldr r1, [r0, r2] - - /* Get line size */ - and r2, r1, #7 - add r2, r2, #4 - - /* Get number of ways */ - ldr r4, .Lway_mask - ands r4, r4, r1, lsr #3 - clz r5, r4 - - /* Get max index */ - ldr r7, .Lmax_index - ands r7, r7, r1, lsr #13 -Loop2: - mov r9, r4 -Loop3: - mov r6, r8, lsl #1 - orr r6, r6, r9, lsl r5 - orr r6, r6, r7, lsl r2 - - /* Clean and invalidate data cache by way/index */ - mcr CP15_DCCISW(r6) - subs r9, r9, #1 - bge Loop3 - subs r7, r7, #1 - bge Loop2 -Skip: - add r8, r8, #1 - cmp r3, r8 - bne Loop1 -Finished: - dsb - ldmia sp!, {r4, r5, r6, r7, r8, r9} - RET -END(armv7_dcache_wbinv_all) - -ENTRY(armv7_idcache_wbinv_all) - stmdb sp!, {lr} - bl armv7_dcache_wbinv_all -#ifdef SMP - mcr CP15_ICIALLUIS -#else - mcr CP15_ICIALLU -#endif - dsb - isb - ldmia sp!, {lr} - RET -END(armv7_idcache_wbinv_all) -#endif - ENTRY(armv7_cpu_sleep) dsb /* data synchronization barrier */ wfi /* wait for interrupt */ RET END(armv7_cpu_sleep) - -ENTRY(armv7_drain_writebuf) - dsb - RET -END(armv7_drain_writebuf) diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 666ff6055fa8..2ed841a1bfdd 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -275,14 +275,9 @@ void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); void sheeva_l2cache_wbinv_all (void); #endif -#if defined(CPU_MV_PJ4B) -void armv6_idcache_wbinv_all (void); -#endif #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) -void armv7_idcache_wbinv_all (void); void armv7_cpu_sleep (int); void armv7_setup (void); -void armv7_drain_writebuf (void); void cortexa_setup (void); #endif @@ -292,8 +287,6 @@ void pj4bv7_setup (void); #endif #if defined(CPU_ARM1176) -void arm11_drain_writebuf (void); - void arm11x6_setup (void); void arm11x6_sleep (int); /* no ref. for errata */ #endif @@ -458,12 +451,6 @@ intr_restore(register_t s) void set_stackptr (u_int mode, u_int address); u_int get_stackptr (u_int mode); -/* - * Miscellany - */ - -int get_pc_str_offset (void); - /* * CPU functions from locore.S */ diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm index ba01cdc40831..2f6138d737d3 100644 --- a/sys/conf/Makefile.arm +++ b/sys/conf/Makefile.arm @@ -76,9 +76,7 @@ FILES_CPU_FUNC = \ $S/$M/$M/cpufunc_asm_arm9.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ - $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv6.S \ - $S/$M/$M/cpufunc_asm_armv7.S + $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S .if ${MACHINE_ARCH:Marmv[67]*} == "" && defined(KERNPHYSADDR) KERNEL_EXTRA=trampoline diff --git a/sys/conf/files.arm b/sys/conf/files.arm index 9117f5c51024..303297177e81 100644 --- a/sys/conf/files.arm +++ b/sys/conf/files.arm @@ -31,11 +31,9 @@ arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e -arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176 arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_81342 arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e -arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_fa526.S optional cpu_fa526 arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b