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amdsbwd: always enable watchdog register decoding

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This seems to be required even if the watchdog is accessed via the common
MMIO space.

Tested on:
- Ryzen 3 3200U APU;
- Ryzen 7 5800X CPU with X570 chipset.

MFC after:	2 weeks
This commit is contained in:
Andriy Gapon 2020-05-27 13:15:54 +03:00
parent 1de4665dfc
commit cca0d3bbd8
1 changed files with 11 additions and 12 deletions
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23
sys/dev/amdsbwd/amdsbwd.c
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@ -381,24 +381,23 @@ amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
uint8_t val;
char buf[36];
/*
* Enable decoding of watchdog MMIO address.
*/
val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
val |= AMDFCH41_WDT_EN;
pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
#ifdef AMDSBWD_DEBUG
val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val);
#endif
val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
if ((val & AMDFCH41_MMIO_EN) != 0) {
/* Fixed offset for the watchdog within ACPI MMIO range. */
amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
*addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
} else {
/*
* Enable decoding of watchdog MMIO address.
*/
val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
val |= AMDFCH41_WDT_EN;
pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
#ifdef AMDSBWD_DEBUG
val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
val);
#endif
/* Special fixed MMIO range for the watchdog. */
*addr = AMDFCH41_WDT_FIXED_ADDR;
}