NXP: Add ls1028a SPI clock driver
Provide driver for LS1028A and LX2160 SPI clock modules. Obtained from: Semihalf Sponsored by: Alstom Differential revision: https://reviews.freebsd.org/D32689
This commit is contained in:
Wojciech Macek
parent
aeda852782
commit
ccfa9ac5ac
310
sys/arm64/qoriq/clk/ls1028a_flexspi_clk.c
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310
sys/arm64/qoriq/clk/ls1028a_flexspi_clk.c
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@ -0,0 +1,310 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/kobj.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clkdev_if.h"
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#include "syscon_if.h"
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struct ls1028a_flexspi_clk_softc {
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device_t dev;
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struct clkdom *clkdom;
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uint64_t reg_offset;
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struct syscon *syscon;
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struct clk_div_def clk_def;
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struct mtx mtx;
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};
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static struct clk_div_table ls1028a_flexspi_div_tbl[] = {
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{ .value = 0, .divider = 1, },
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{ .value = 1, .divider = 2, },
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{ .value = 2, .divider = 3, },
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{ .value = 3, .divider = 4, },
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{ .value = 4, .divider = 5, },
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{ .value = 5, .divider = 6, },
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{ .value = 6, .divider = 7, },
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{ .value = 7, .divider = 8, },
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{ .value = 11, .divider = 12, },
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{ .value = 15, .divider = 16, },
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{ .value = 16, .divider = 20, },
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{ .value = 17, .divider = 24, },
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{ .value = 18, .divider = 28, },
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{ .value = 19, .divider = 32, },
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{ .value = 20, .divider = 80, },
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{}
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};
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static struct clk_div_table lx2160a_flexspi_div_tbl[] = {
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{ .value = 1, .divider = 2, },
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{ .value = 3, .divider = 4, },
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{ .value = 5, .divider = 6, },
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{ .value = 7, .divider = 8, },
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{ .value = 11, .divider = 12, },
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{ .value = 15, .divider = 16, },
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{ .value = 16, .divider = 20, },
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{ .value = 17, .divider = 24, },
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{ .value = 18, .divider = 28, },
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{ .value = 19, .divider = 32, },
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{ .value = 20, .divider = 80, },
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{}
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};
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static struct ofw_compat_data compat_data[] = {
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{ "fsl,ls1028a-flexspi-clk", (uintptr_t)ls1028a_flexspi_div_tbl },
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{ "fsl,lx2160a-flexspi-clk", (uintptr_t)lx2160a_flexspi_div_tbl },
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{ NULL, 0 }
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};
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static int
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ls1028a_flexspi_clk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
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device_set_desc(dev, "NXP FlexSPI clock driver");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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ls1028a_flexspi_clk_attach(device_t dev)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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const char *oclkname = NULL;
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const char *pclkname[1];
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uint32_t acells;
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uint32_t scells;
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pcell_t cells[4];
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phandle_t node;
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uint64_t reg_size;
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int ret;
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clk_t clk;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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/* Parse address-cells and size-cells from the parent node as a fallback */
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if (OF_getencprop(node, "#address-cells", &acells,
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sizeof(acells)) == -1) {
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if (OF_getencprop(OF_parent(node), "#address-cells", &acells,
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sizeof(acells)) == -1) {
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acells = 2;
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}
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}
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if (OF_getencprop(node, "#size-cells", &scells,
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sizeof(scells)) == -1) {
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if (OF_getencprop(OF_parent(node), "#size-cells", &scells,
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sizeof(scells)) == -1) {
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scells = 1;
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}
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}
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ret = OF_getencprop(node, "reg", cells, (acells + scells) * sizeof(pcell_t));
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if (ret < 0) {
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device_printf(dev, "ERROR: failed to read REG property\n");
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return (ENOMEM);
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}
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sc->reg_offset = (uint64_t)cells[0];
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if (acells == 2)
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sc->reg_offset = (sc->reg_offset << 32) | (uint64_t)cells[1];
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reg_size = (uint64_t)cells[acells];
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if (scells == 2)
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reg_size = (reg_size << 32) | (uint64_t)cells[acells + 1];
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if (reg_size != 4) {
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device_printf(dev, "ERROR, expected only single register\n");
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return (EINVAL);
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}
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if (sc->reg_offset >> 32UL) {
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device_printf(dev, "ERROR, only 32-bit address offset is supported\n");
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return (EINVAL);
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}
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/* Get syscon handle */
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ret = SYSCON_GET_HANDLE(dev, &sc->syscon);
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if ((ret != 0) || (sc->syscon == NULL)) {
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device_printf(dev, "ERROR: failed to get syscon\n");
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return (EFAULT);
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}
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/* Initialize access mutex */
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mtx_init(&sc->mtx, "FSL clock mtx", NULL, MTX_DEF);
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/* Get clock names */
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ret = clk_get_by_ofw_index(dev, node, 0, &clk);
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if (ret) {
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device_printf(dev, "ERROR: failed to get parent clock\n");
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return (EINVAL);
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}
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pclkname[0] = clk_get_name(clk);
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ret = clk_parse_ofw_clk_name(dev, node, &oclkname);
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if (ret) {
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device_printf(dev, "ERROR: failed to get output clock name\n");
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return (EINVAL);
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}
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#ifdef DEBUG
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device_printf(dev, "INFO: pclkname %s, oclkname %s\n", pclkname[0], oclkname);
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#endif
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/* Fixup CLK structure */
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sc->clk_def.clkdef.name = oclkname;
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sc->clk_def.clkdef.parent_names = (const char **)pclkname;
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sc->clk_def.offset = (uint32_t)sc->reg_offset;
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sc->clk_def.clkdef.id = 1;
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sc->clk_def.clkdef.parent_cnt = 1;
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sc->clk_def.clkdef.flags = 0;
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sc->clk_def.div_flags = CLK_DIV_WITH_TABLE;
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sc->clk_def.i_shift = 0;
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sc->clk_def.i_width = 5;
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sc->clk_def.div_table = (struct clk_div_table*)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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/* Create clock */
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sc->clkdom = clkdom_create(dev);
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if (sc->clkdom == NULL)
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panic("clkdom == NULL");
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ret = clknode_div_register(sc->clkdom, &sc->clk_def);
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if (ret) {
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device_printf(dev, "ERROR: unable to register clock\n");
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return (EINVAL);
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}
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clkdom_finit(sc->clkdom);
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if (bootverbose)
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clkdom_dump(sc->clkdom);
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return (0);
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}
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static int
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ls1028a_flexspi_clk_detach(device_t dev)
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{
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/* Clock detaching is not supported */
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return (EACCES);
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}
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static int
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ls1028a_flexspi_clk_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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sc = device_get_softc(dev);
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*val = SYSCON_READ_4(sc->syscon, addr);
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return (0);
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}
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static int
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ls1028a_flexspi_clk_write_4(device_t dev, bus_addr_t addr, uint32_t val)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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int ret;
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sc = device_get_softc(dev);
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ret = SYSCON_WRITE_4(sc->syscon, addr, val);
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return (ret);
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}
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static int
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ls1028a_flexspi_clk_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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int ret;
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sc = device_get_softc(dev);
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ret = SYSCON_MODIFY_4(sc->syscon, addr, clr, set);
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return (ret);
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}
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static void
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ls1028a_flexspi_clk_device_lock(device_t dev)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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}
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static void
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ls1028a_flexspi_clk_device_unlock(device_t dev)
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{
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struct ls1028a_flexspi_clk_softc *sc;
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sc = device_get_softc(dev);
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mtx_unlock(&sc->mtx);
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}
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static device_method_t ls1028a_flexspi_clk_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ls1028a_flexspi_clk_probe),
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DEVMETHOD(device_attach, ls1028a_flexspi_clk_attach),
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DEVMETHOD(device_detach, ls1028a_flexspi_clk_detach),
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DEVMETHOD(clkdev_read_4, ls1028a_flexspi_clk_read_4),
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DEVMETHOD(clkdev_write_4, ls1028a_flexspi_clk_write_4),
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DEVMETHOD(clkdev_modify_4, ls1028a_flexspi_clk_modify_4),
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DEVMETHOD(clkdev_device_lock, ls1028a_flexspi_clk_device_lock),
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DEVMETHOD(clkdev_device_unlock, ls1028a_flexspi_clk_device_unlock),
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DEVMETHOD_END
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};
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static devclass_t ls1028a_flexspi_clk_devclass;
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static DEFINE_CLASS_0(fspi_clk, ls1028a_flexspi_clk_driver, ls1028a_flexspi_clk_methods,
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sizeof(struct ls1028a_flexspi_clk_softc));
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EARLY_DRIVER_MODULE(ls1028a_flexspi_clk, simple_mfd, ls1028a_flexspi_clk_driver,
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ls1028a_flexspi_clk_devclass, NULL, NULL, BUS_PASS_TIMER);
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@ -521,6 +521,7 @@ arm64/qoriq/qoriq_dw_pci.c optional pci fdt SOC_NXP_LS
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arm64/qoriq/qoriq_therm.c optional pci fdt SOC_NXP_LS
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arm64/qoriq/qoriq_therm_if.m optional pci fdt SOC_NXP_LS
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arm64/qoriq/clk/ls1028a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/ls1028a_flexspi_clk.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/lx2160a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS
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