From cec3c5649c47f6440f2d10724219033140f98c41 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 1 Sep 2020 22:02:32 +0000 Subject: [PATCH] oce: clean up empty lines in .c and .h files --- sys/dev/oce/oce_hw.c | 30 +++------- sys/dev/oce/oce_hw.h | 49 +--------------- sys/dev/oce/oce_if.c | 119 +++++++++------------------------------ sys/dev/oce/oce_if.h | 18 ------ sys/dev/oce/oce_mbox.c | 72 ++++++----------------- sys/dev/oce/oce_queue.c | 100 ++++---------------------------- sys/dev/oce/oce_sysctl.c | 50 +++------------- sys/dev/oce/oce_user.h | 1 - sys/dev/oce/oce_util.c | 21 +------ 9 files changed, 77 insertions(+), 383 deletions(-) diff --git a/sys/dev/oce/oce_hw.c b/sys/dev/oce/oce_hw.c index c2474e06a270..aa187e76e86b 100644 --- a/sys/dev/oce/oce_hw.c +++ b/sys/dev/oce/oce_hw.c @@ -40,7 +40,6 @@ /* $FreeBSD$ */ - #include "oce_if.h" static int oce_POST(POCE_SOFTC sc); @@ -98,7 +97,7 @@ oce_hw_init(POCE_SOFTC sc) rc = oce_POST(sc); if (rc) return rc; - + /* create the bootstrap mailbox */ rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0); if (rc) { @@ -115,30 +114,27 @@ oce_hw_init(POCE_SOFTC sc) if (rc) goto error; - rc = oce_get_fw_version(sc); if (rc) goto error; - rc = oce_get_fw_config(sc); if (rc) goto error; - sc->macaddr.size_of_struct = 6; rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK, &sc->macaddr); if (rc) goto error; - + if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) { rc = oce_mbox_check_native_mode(sc); if (rc) goto error; } else sc->be3_native = 0; - + return rc; error: @@ -147,8 +143,6 @@ error: return rc; } - - /** * @brief Releases the obtained pci resources * @param sc software handle to the device @@ -194,9 +188,6 @@ oce_hw_pci_free(POCE_SOFTC sc) } } - - - /** * @brief Function to get the PCI capabilities * @param sc software handle to the device @@ -284,7 +275,7 @@ oce_hw_pci_alloc(POCE_SOFTC sc) if (intf.bits.sli_valid != OCE_INTF_VALID_SIG) goto error; - + if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) { device_printf(sc->dev, "Adapter doesnt support SLI4\n"); goto error; @@ -329,7 +320,6 @@ error: return ENXIO; } - /** * @brief Function for device shutdown * @param sc software handle to the device @@ -363,7 +353,6 @@ oce_hw_shutdown(POCE_SOFTC sc) oce_dma_free(sc, &sc->bsmbx); } - /** * @brief Function for creating nw interface. * @param sc software handle to the device @@ -480,7 +469,7 @@ oce_hw_start(POCE_SOFTC sc) rc = oce_get_link_status(sc, &link); if (rc) return 1; - + if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) { sc->link_status = NTWK_LOGICAL_LINK_UP; if_link_state_change(sc->ifp, LINK_STATE_UP); @@ -493,7 +482,7 @@ oce_hw_start(POCE_SOFTC sc) sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10; rc = oce_start_mq(sc->mq); - + /* we need to get MCC aync events. So enable intrs and arm first EQ, Other EQs will be armed after interface is UP */ @@ -508,7 +497,6 @@ oce_hw_start(POCE_SOFTC sc) return rc; } - /** * @brief Function for hardware enable interupts. * @param sc software handle to the device @@ -524,7 +512,6 @@ oce_hw_intr_enable(POCE_SOFTC sc) } - /** * @brief Function for hardware disable interupts * @param sc software handle to the device @@ -533,13 +520,12 @@ void oce_hw_intr_disable(POCE_SOFTC sc) { uint32_t reg; - + reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL); reg &= ~HOSTINTR_MASK; OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg); } - static u_int oce_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { @@ -554,7 +540,6 @@ oce_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) return (1); } - /** * @brief Function for hardware update multicast filter * @param sc software handle to the device @@ -589,4 +574,3 @@ oce_hw_update_multicast(POCE_SOFTC sc) oce_dma_free(sc, &dma); return rc; } - diff --git a/sys/dev/oce/oce_hw.h b/sys/dev/oce/oce_hw.h index ce41cdcabb5d..82023f3dfc70 100644 --- a/sys/dev/oce/oce_hw.h +++ b/sys/dev/oce/oce_hw.h @@ -61,7 +61,6 @@ #define INTR_EN 0x20000000 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ - /********* UE Status and Mask Registers ***/ #define PCICFG_UE_STATUS_LOW 0xA0 #define PCICFG_UE_STATUS_HIGH 0xA4 @@ -271,8 +270,6 @@ typedef union pci_sli_intf_u { } bits; } pci_sli_intf_t; - - /* physical address structure to be used in MBX */ struct phys_addr { /* dw0 */ @@ -281,8 +278,6 @@ struct phys_addr { uint32_t hi; }; - - typedef union pcicfg_intr_ctl_u { uint32_t dw0; struct { @@ -304,9 +299,6 @@ typedef union pcicfg_intr_ctl_u { } bits; } pcicfg_intr_ctl_t; - - - typedef union pcicfg_semaphore_u { uint32_t dw0; struct { @@ -320,9 +312,6 @@ typedef union pcicfg_semaphore_u { } bits; } pcicfg_semaphore_t; - - - typedef union pcicfg_soft_reset_u { uint32_t dw0; struct { @@ -344,9 +333,6 @@ typedef union pcicfg_soft_reset_u { } bits; } pcicfg_soft_reset_t; - - - typedef union pcicfg_online1_u { uint32_t dw0; struct { @@ -400,8 +386,6 @@ typedef union pcicfg_online1_u { } bits; } pcicfg_online1_t; - - typedef union mpu_ep_semaphore_u { uint32_t dw0; struct { @@ -427,9 +411,6 @@ typedef union mpu_ep_semaphore_u { } bits; } mpu_ep_semaphore_t; - - - typedef union mpu_ep_control_u { uint32_t dw0; struct { @@ -453,9 +434,6 @@ typedef union mpu_ep_control_u { } bits; } mpu_ep_control_t; - - - /* RX doorbell */ typedef union pd_rxulp_db_u { uint32_t dw0; @@ -474,7 +452,6 @@ typedef union pd_rxulp_db_u { } bits; } pd_rxulp_db_t; - /* TX doorbell */ typedef union pd_txulp_db_u { uint32_t dw0; @@ -777,7 +754,6 @@ struct oce_async_event_qnq { uint32_t code; } ; - typedef union oce_mq_ext_ctx_u { uint32_t dw[6]; struct { @@ -861,7 +837,6 @@ typedef union oce_mq_ext_ctx_u { } oce_mq_ext_ctx_t; - /* MQ mailbox structure */ struct oce_bmbx { struct oce_mbx mbx; @@ -1554,8 +1529,6 @@ struct mbx_create_common_mq_ex { } params; }; - - /* [53] OPCODE_COMMON_DESTROY_MQ */ struct mbx_destroy_common_mq { struct mbx_hdr hdr; @@ -1710,7 +1683,6 @@ struct mbx_common_query_fw_config { uint32_t port_id; /* used for stats retrieval */ uint32_t function_mode; struct { - uint32_t ulp_mode; uint32_t nic_wqid_base; uint32_t nic_wq_tot; @@ -1806,7 +1778,6 @@ enum CQFW_FUNCTION_MODES_SUPPORTED { FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ }; - struct mbx_common_config_vlan { struct mbx_hdr hdr; union { @@ -2098,7 +2069,6 @@ struct mbx_common_get_func_config { } params; }; - /* OPCODE_COMMON_GET_PROFILE_CONFIG */ struct mbx_common_get_profile_config { @@ -2150,7 +2120,6 @@ struct oce_nic_resc_desc { }; - struct flash_file_hdr { uint8_t sign[52]; uint8_t ufi_version[4]; @@ -2198,7 +2167,6 @@ struct flash_sec_info { struct flash_section_entry fsec_entry[32]; }; - enum LOWLEVEL_SUBSYSTEM_OPCODES { /* Opcodes used for lowlevel functions common to many subystems. * Some of these opcodes are used for diagnostic functions only. @@ -2896,8 +2864,6 @@ struct mbx_delete_nic_wq { } params; }; - - struct mbx_create_nic_rq { struct mbx_hdr hdr; union { @@ -2921,8 +2887,6 @@ struct mbx_create_nic_rq { } params; }; - - /* [10] NIC_DELETE_RQ */ struct mbx_delete_nic_rq { /* dw0 - dw3 */ @@ -2947,9 +2911,6 @@ struct mbx_delete_nic_rq { } params; }; - - - struct oce_port_rxf_stats_v0 { uint32_t rx_bytes_lsd; /* dword 0*/ uint32_t rx_bytes_msd; /* dword 1*/ @@ -3019,7 +2980,6 @@ struct oce_port_rxf_stats_v0 { uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ }; - struct oce_rxf_stats_v0 { struct oce_port_rxf_stats_v0 port[2]; uint32_t rx_drops_no_pbuf; /* dword 132*/ @@ -3090,7 +3050,6 @@ struct oce_port_rxf_stats_v2 { uint32_t rsvd7[19]; }; - struct oce_port_rxf_stats_v1 { uint32_t rsvd0[12]; uint32_t rx_crc_errors; @@ -3167,7 +3126,6 @@ struct oce_erx_stats_v1 { uint32_t rsvd[4]; }; - struct oce_erx_stats_v0 { uint32_t rx_drops_no_fragments[44]; uint32_t rsvd[4]; @@ -3186,7 +3144,6 @@ struct oce_hw_stats_v2 { uint32_t rsvd1[18]; }; - struct oce_hw_stats_v1 { struct oce_rxf_stats_v1 rxf; uint32_t rsvd0[OCE_TXP_SW_SZ]; @@ -3445,7 +3402,6 @@ struct mbx_get_queue_stats { } params; }; - /* [01] NIC_CONFIG_RSS */ #define OCE_HASH_TBL_SZ 10 #define OCE_CPU_TBL_SZ 128 @@ -3478,11 +3434,9 @@ struct mbx_config_nic_rss { } rsp; } params; }; - #pragma pack() - typedef uint32_t oce_stat_t; /* statistic counter */ enum OCE_RXF_PORT_STATS { @@ -3885,7 +3839,6 @@ struct mbx_nic_set_iface_lro_config { } params; }; - struct mbx_create_nic_rq_v2 { struct mbx_hdr hdr; union { @@ -4074,7 +4027,7 @@ struct nic_hwlro_singleton_cqe { uint32_t debug:7; uint32_t cqe_type:2; uint32_t valid:1; - + /* dw 3 */ uint32_t rss_hash_value; #endif diff --git a/sys/dev/oce/oce_if.c b/sys/dev/oce/oce_if.c index 1e7e5eb421e5..7c9b71089081 100644 --- a/sys/dev/oce/oce_if.c +++ b/sys/dev/oce/oce_if.c @@ -132,7 +132,6 @@ struct oce_common_cqe_info{ uint16_t vtag; }; - /* Driver entry points prototypes */ static int oce_probe(device_t dev); static int oce_attach(device_t dev); @@ -190,7 +189,6 @@ static void oce_get_config(POCE_SOFTC sc); static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete); static void oce_read_env_variables(POCE_SOFTC sc); - /* IP specific */ #if defined(INET6) || defined(INET) static int oce_init_lro(POCE_SOFTC sc); @@ -213,7 +211,6 @@ static driver_t oce_driver = { }; static devclass_t oce_devclass; - /* global vars */ const char component_revision[32] = {"///" COMPONENT_REVISION "///"}; @@ -225,7 +222,6 @@ uint32_t oce_rq_buf_size = 2048; TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled); TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss); - /* Supported devices table */ static uint32_t supportedDevices[] = { (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2, @@ -236,7 +232,6 @@ static uint32_t supportedDevices[] = { (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH }; - DRIVER_MODULE(oce, pci, oce_driver, oce_devclass, 0, 0); MODULE_PNP_INFO("W32:vendor/device", pci, oce, supportedDevices, nitems(supportedDevices)); @@ -244,7 +239,6 @@ MODULE_DEPEND(oce, pci, 1, 1, 1); MODULE_DEPEND(oce, ether, 1, 1, 1); MODULE_VERSION(oce, 1); - POCE_SOFTC softc_head = NULL; POCE_SOFTC softc_tail = NULL; @@ -302,7 +296,6 @@ oce_probe(device_t dev) return ENXIO; } - static int oce_attach(device_t dev) { @@ -414,7 +407,6 @@ pci_res_free: } - static int oce_detach(device_t dev) { @@ -441,7 +433,7 @@ oce_detach(device_t dev) UNLOCK(&sc->dev_lock); callout_drain(&sc->timer); - + if (sc->vlan_attach != NULL) EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach); if (sc->vlan_detach != NULL) @@ -458,18 +450,16 @@ oce_detach(device_t dev) return 0; } - static int oce_shutdown(device_t dev) { int rc; - + rc = oce_detach(dev); return rc; } - static int oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { @@ -481,7 +471,6 @@ oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) uint32_t u; switch (command) { - case SIOCGIFMEDIA: rc = ifmedia_ioctl(ifp, ifr, &sc->media, command); break; @@ -634,24 +623,22 @@ oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) return rc; } - static void oce_init(void *arg) { POCE_SOFTC sc = arg; - + LOCK(&sc->dev_lock); if (sc->ifp->if_flags & IFF_UP) { oce_if_deactivate(sc); oce_if_activate(sc); } - + UNLOCK(&sc->dev_lock); } - static int oce_multiq_start(struct ifnet *ifp, struct mbuf *m) { @@ -676,7 +663,6 @@ oce_multiq_start(struct ifnet *ifp, struct mbuf *m) } - static void oce_multiq_flush(struct ifnet *ifp) { @@ -691,8 +677,6 @@ oce_multiq_flush(struct ifnet *ifp) if_qflush(ifp); } - - /***************************************************************************** * Driver interrupt routines functions * *****************************************************************************/ @@ -708,7 +692,6 @@ oce_intr(void *arg, int pending) struct oce_cq *cq = NULL; int i, num_eqes = 0; - bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map, BUS_DMASYNC_POSTWRITE); do { @@ -722,7 +705,7 @@ oce_intr(void *arg, int pending) num_eqes++; } while (TRUE); - + if (!num_eqes) goto eq_arm; /* Spurious */ @@ -747,7 +730,6 @@ eq_arm: return; } - static int oce_setup_intr(POCE_SOFTC sc) { @@ -816,7 +798,6 @@ error: return rc; } - static int oce_fast_isr(void *arg) { @@ -835,7 +816,6 @@ oce_fast_isr(void *arg) return FILTER_HANDLED; } - static int oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending)) { @@ -885,12 +865,11 @@ oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending)) } - void oce_intr_free(POCE_SOFTC sc) { int i = 0; - + for (i = 0; i < sc->intr_count; i++) { if (sc->intrs[i].tag != NULL) @@ -912,8 +891,6 @@ oce_intr_free(POCE_SOFTC sc) } - - /****************************************************************************** * Media callbacks functions * ******************************************************************************/ @@ -923,15 +900,14 @@ oce_media_status(struct ifnet *ifp, struct ifmediareq *req) { POCE_SOFTC sc = (POCE_SOFTC) ifp->if_softc; - req->ifm_status = IFM_AVALID; req->ifm_active = IFM_ETHER; - + if (sc->link_status == 1) req->ifm_status |= IFM_ACTIVE; else return; - + switch (sc->link_speed) { case 1: /* 10 Mbps */ req->ifm_active |= IFM_10_T | IFM_FDX; @@ -965,18 +941,16 @@ oce_media_status(struct ifnet *ifp, struct ifmediareq *req) sc->speed = 0; break; } - + return; } - int oce_media_change(struct ifnet *ifp) { return 0; } - static void oce_is_pkt_dest_bmc(POCE_SOFTC sc, struct mbuf *m, boolean_t *os2bmc, struct mbuf **m_new) @@ -1050,8 +1024,6 @@ done: } } - - /***************************************************************************** * Transmit routines functions * *****************************************************************************/ @@ -1094,7 +1066,6 @@ oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index) device_printf(sc->dev, "Insertion unsuccessful\n"); return 0; } - } /* Lancer, SH ASIC has a bug wherein Packets that are 32 bytes or less @@ -1123,7 +1094,6 @@ tx_start: } } - pd = &wq->pckts[wq->pkt_desc_head]; retry: @@ -1252,7 +1222,7 @@ retry: m = m_new; goto tx_start; } - + return 0; free_ret: @@ -1261,7 +1231,6 @@ free_ret: return rc; } - static void oce_process_tx_completion(struct oce_wq *wq) { @@ -1280,7 +1249,6 @@ oce_process_tx_completion(struct oce_wq *wq) m_freem(m); pd->mbuf = NULL; - if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE) { if (wq->ring->num_used < (wq->ring->num_items / 2)) { sc->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE); @@ -1289,7 +1257,6 @@ oce_process_tx_completion(struct oce_wq *wq) } } - static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq) { @@ -1302,7 +1269,6 @@ oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq) } - #if defined(INET6) || defined(INET) static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp) @@ -1318,7 +1284,7 @@ oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp) struct tcphdr *th; uint16_t etype; int total_len = 0, ehdrlen = 0; - + m = *mpp; if (M_WRITABLE(m) == 0) { @@ -1362,13 +1328,13 @@ oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp) default: return NULL; } - + m = m_pullup(m, total_len); if (!m) return NULL; *mpp = m; return m; - + } #endif /* INET6 || INET */ @@ -1389,7 +1355,6 @@ oce_tx_task(void *arg, int npending) UNLOCK(&wq->tx_lock); } - void oce_start(struct ifnet *ifp) { @@ -1404,7 +1369,7 @@ oce_start(struct ifnet *ifp) if (!sc->link_status) return; - + while (true) { IF_DEQUEUE(&sc->ifp->if_snd, m); if (m == NULL) @@ -1425,7 +1390,6 @@ oce_start(struct ifnet *ifp) } } - /* Handle the Completion Queue for transmit */ uint16_t oce_wq_handler(void *arg) @@ -1460,12 +1424,11 @@ oce_wq_handler(void *arg) if (num_cqes) oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE); - + UNLOCK(&wq->tx_compl_lock); return num_cqes; } - static int oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq) { @@ -1505,9 +1468,6 @@ oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq) return 0; } - - - /***************************************************************************** * Receive routines functions * *****************************************************************************/ @@ -1730,7 +1690,7 @@ oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe) vtag = BSWAP_16(cqe->u0.s.vlan_tag); else vtag = cqe->u0.s.vlan_tag; - + cq_info.l4_cksum_pass = cqe->u0.s.l4_cksum_pass; cq_info.ip_cksum_pass = cqe->u0.s.ip_cksum_pass; cq_info.ipv6_frame = cqe->u0.s.ip_ver; @@ -1773,7 +1733,6 @@ oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe) (cqe->u0.s.l4_cksum_pass) && (!cqe->u0.s.ip_ver) && (rq->lro.lro_cnt != 0)) { - if (tcp_lro_rx(&rq->lro, m, 0) == 0) { rq->lro_pkts_queued ++; goto post_done; @@ -1781,7 +1740,7 @@ oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe) /* If LRO posting fails then try to post to STACK */ } #endif - + (*sc->ifp->if_input) (sc->ifp, m); #if defined(INET6) || defined(INET) post_done: @@ -1799,7 +1758,6 @@ exit: return; } - void oce_discard_rx_comp(struct oce_rq *rq, int num_frags) { @@ -1826,7 +1784,6 @@ oce_discard_rx_comp(struct oce_rq *rq, int num_frags) } } - static int oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) { @@ -1838,12 +1795,11 @@ oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) vtp = cqe_v1->u0.s.vlan_tag_present; } else vtp = cqe->u0.s.vlan_tag_present; - + return vtp; } - static int oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) { @@ -1857,7 +1813,7 @@ oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) return 0; } else ;/* For BE3 legacy and Lancer this is dummy */ - + return 1; } @@ -1874,11 +1830,10 @@ oce_rx_flush_lro(struct oce_rq *rq) tcp_lro_flush_all(lro); rq->lro_pkts_queued = 0; - + return; } - static int oce_init_lro(POCE_SOFTC sc) { @@ -1898,7 +1853,6 @@ oce_init_lro(POCE_SOFTC sc) return rc; } - void oce_free_lro(POCE_SOFTC sc) { @@ -1991,7 +1945,7 @@ oce_alloc_rx_bufs(struct oce_rq *rq, int count) } } } - + return 0; } @@ -2143,9 +2097,6 @@ oce_rq_handler(void *arg) } - - - /***************************************************************************** * Helper function prototypes in this file * *****************************************************************************/ @@ -2191,7 +2142,7 @@ oce_attach_ifp(POCE_SOFTC sc) sc->ifp->if_capabilities |= IFCAP_LRO; sc->ifp->if_capabilities |= IFCAP_VLAN_HWTSO; #endif - + sc->ifp->if_capenable = sc->ifp->if_capabilities; sc->ifp->if_baudrate = IF_Gbps(10); @@ -2200,11 +2151,10 @@ oce_attach_ifp(POCE_SOFTC sc) sc->ifp->if_hw_tsomaxsegsize = 4096; ether_ifattach(sc->ifp, sc->macaddr.mac_addr); - + return 0; } - static void oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) { @@ -2221,7 +2171,6 @@ oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) oce_vid_config(sc); } - static void oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) { @@ -2237,7 +2186,6 @@ oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) oce_vid_config(sc); } - /* * A max of 64 vlans can be configured in BE. If the user configures * more, place the card in vlan promiscuous mode. @@ -2266,14 +2214,12 @@ oce_vid_config(POCE_SOFTC sc) return status; } - static void oce_mac_addr_set(POCE_SOFTC sc) { uint32_t old_pmac_id = sc->pmac_id; int status = 0; - status = bcmp((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr, sc->macaddr.size_of_struct); if (!status) @@ -2291,7 +2237,6 @@ oce_mac_addr_set(POCE_SOFTC sc) } - static int oce_handle_passthrough(struct ifnet *ifp, caddr_t data) { @@ -2501,22 +2446,21 @@ static void oce_detect_hw_error(POCE_SOFTC sc) } - static void oce_local_timer(void *arg) { POCE_SOFTC sc = arg; int i = 0; - + oce_detect_hw_error(sc); oce_refresh_nic_stats(sc); oce_refresh_queue_stats(sc); oce_mac_addr_set(sc); - + /* TX Watch Dog*/ for (i = 0; i < sc->nwqs; i++) oce_tx_restart(sc, sc->wq[i]); - + /* calculate and set the eq delay for optimal interrupt rate */ if (IS_BE(sc) || IS_SH(sc)) oce_eqd_set_periodic(sc); @@ -2613,7 +2557,6 @@ oce_if_deactivate(POCE_SOFTC sc) DELAY(10); } - static void oce_if_activate(POCE_SOFTC sc) { @@ -2623,9 +2566,9 @@ oce_if_activate(POCE_SOFTC sc) int i, rc = 0; sc->ifp->if_drv_flags |= IFF_DRV_RUNNING; - + oce_hw_intr_disable(sc); - + oce_start_rx(sc); for_all_rq_queues(sc, rq, i) { @@ -2640,7 +2583,6 @@ oce_if_activate(POCE_SOFTC sc) device_printf(sc->dev, "Unable to start TX\n"); } - for_all_evnt_queues(sc, eq, i) oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE); @@ -2662,7 +2604,6 @@ process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe) } } - static void oce_async_grp5_osbmc_process(POCE_SOFTC sc, struct oce_async_evt_grp5_os2bmc *evt) { @@ -2683,7 +2624,6 @@ static void oce_async_grp5_osbmc_process(POCE_SOFTC sc, sc->bmc_filt_mask |= (evt->u.s.mcast_filt << 8); } - static void oce_process_grp5_events(POCE_SOFTC sc, struct oce_mq_cqe *cqe) { struct oce_async_event_grp5_pvid_state *gcqe; @@ -2719,7 +2659,6 @@ oce_mq_handler(void *arg) struct oce_async_cqe_link_state *acqe; struct oce_async_event_qnq *dbgcqe; - bus_dmamap_sync(cq->ring->dma.tag, cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe); @@ -2757,7 +2696,6 @@ oce_mq_handler(void *arg) return 0; } - static void setup_max_queues_want(POCE_SOFTC sc) { @@ -2778,7 +2716,6 @@ setup_max_queues_want(POCE_SOFTC sc) sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1; } - static void update_queues_got(POCE_SOFTC sc) { diff --git a/sys/dev/oce/oce_if.h b/sys/dev/oce/oce_if.h index 033d48f7ad90..8938dd86ecce 100644 --- a/sys/dev/oce/oce_if.h +++ b/sys/dev/oce/oce_if.h @@ -120,7 +120,6 @@ #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) - /* proportion Service Level Interface queues */ #define OCE_MAX_UNITS 2 #define OCE_MAX_PPORT OCE_MAX_UNITS @@ -164,7 +163,6 @@ extern int mp_ncpus; /* system's total active cpu cores */ #define OCE_HWLRO_MAX_RQ_POSTS 64 #define OCE_DEFAULT_PROMISCUOUS 0 - #define RSS_ENABLE_IPV4 0x1 #define RSS_ENABLE_TCP_IPV4 0x2 #define RSS_ENABLE_IPV6 0x4 @@ -178,7 +176,6 @@ extern int mp_ncpus; /* system's total active cpu cores */ #define OCE_FC_RX 0x00000002 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) - /* Interface capabilities to give device when creating interface */ #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ MBX_RX_IFACE_FLAGS_UNTAGGED | \ @@ -200,7 +197,6 @@ extern int mp_ncpus; /* system's total active cpu cores */ #define OCE_IF_HWASSIST_NONE 0 #define OCE_IF_CAPABILITIES_NONE 0 - #define MAX_VLANFILTER_SIZE 64 #define MAX_VLANS 4096 @@ -224,7 +220,6 @@ extern int mp_ncpus; /* system's total active cpu cores */ #define for_all_cq_queues(sc, cq, i) \ for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) - /* Flash specific */ #define IOCTL_COOKIE "SERVERENGINES CORP" #define MAX_FLASH_COMP 32 @@ -278,7 +273,6 @@ typedef struct oce_intr_info { int vector; /* interrupt vector number */ } OCE_INTR_INFO, *POCE_INTR_INFO; - /* Ring related */ #define GET_Q_NEXT(_START, _STEP, _END) \ (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ @@ -643,14 +637,12 @@ struct oce_cq { uint32_t ref_count; }; - struct mq_config { uint32_t eqd; uint8_t q_len; uint8_t pad[3]; }; - struct oce_mq { void *parent; oce_ring_buffer_t *ring; @@ -742,7 +734,6 @@ struct oce_rx_queue_stats { uint32_t rx_drops_no_frags; /* HW has no fetched frags */ }; - struct oce_rq { struct rq_config cfg; uint32_t rq_id; @@ -776,8 +767,6 @@ struct link_status { uint16_t qos_link_speed; }; - - #define OCE_FLAGS_PCIX 0x00000001 #define OCE_FLAGS_PCIE 0x00000002 #define OCE_FLAGS_MSI_CAPABLE 0x00000004 @@ -904,7 +893,6 @@ typedef struct oce_softc { #define OCE_RDMA_FLAG_SUPPORTED 0x00000001 - /************************************************** * BUS memory read/write macros * BE3: accesses three BAR spaces (CFG, CSR, DB) @@ -1011,7 +999,6 @@ void oce_free_posted_rxbuf(struct oce_rq *rq); void oce_free_lro(POCE_SOFTC sc); #endif - /************************************************************ * Mailbox functions ************************************************************/ @@ -1086,7 +1073,6 @@ void mbx_common_req_hdr_init(struct mbx_hdr *hdr, uint32_t timeout, uint32_t pyld_len, uint8_t version); - uint16_t oce_mq_handler(void *arg); /************************************************************ @@ -1102,7 +1088,6 @@ void oce_tx_task(void *arg, int npending); int oce_alloc_rx_bufs(struct oce_rq *rq, int count); uint16_t oce_rq_handler(void *arg); - /* Sysctl functions */ void oce_add_sysctls(POCE_SOFTC sc); void oce_refresh_queue_stats(POCE_SOFTC sc); @@ -1193,8 +1178,6 @@ extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; struct oce_rdma_info; extern struct oce_rdma_if *oce_rdma_if; - - /* OS2BMC related */ #define DHCP_CLIENT_PORT 68 @@ -1266,4 +1249,3 @@ extern struct oce_rdma_if *oce_rdma_if; #define LRO_FLAGS_CLSC_IPV6 0x00000020 #define NIC_RQ_FLAGS_RSS 0x0001 #define NIC_RQ_FLAGS_LRO 0x0020 - diff --git a/sys/dev/oce/oce_mbox.c b/sys/dev/oce/oce_mbox.c index 05dac5847cb8..7470d7a13b07 100644 --- a/sys/dev/oce/oce_mbox.c +++ b/sys/dev/oce/oce_mbox.c @@ -117,7 +117,6 @@ oce_reset_fun(POCE_SOFTC sc) return rc; } - /** * @brief This funtions tells firmware we are * done with commands. @@ -145,11 +144,10 @@ oce_fw_clean(POCE_SOFTC sc) *ptr = 0xff; ret = oce_mbox_dispatch(sc, 2); - + return ret; } - /** * @brief Mailbox wait * @param sc software handle to the device @@ -180,7 +178,6 @@ oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec) return ETIMEDOUT; } - /** * @brief Mailbox dispatch * @param sc software handle to the device @@ -223,8 +220,6 @@ oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec) return rc; } - - /** * @brief Mailbox common request header initialization * @param hdr mailbox header @@ -252,8 +247,6 @@ mbx_common_req_hdr_init(struct mbx_hdr *hdr, hdr->u0.req.version = version; } - - /** * @brief Function to initialize the hw with host endian information * @param sc software handle to the device @@ -282,11 +275,10 @@ oce_mbox_init(POCE_SOFTC sc) ret = oce_mbox_dispatch(sc, 0); } - + return ret; } - /** * @brief Function to get the firmware version * @param sc software handle to the device @@ -329,7 +321,6 @@ error: return ret; } - /** * @brief Firmware will send gracious notifications during * attach only after sending first mcc commnad. We @@ -347,7 +338,7 @@ oce_first_mcc_cmd(POCE_SOFTC sc) mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx); bzero(mbx, sizeof(struct oce_mbx)); - + fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload; mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, MBX_SUBSYSTEM_COMMON, @@ -405,7 +396,7 @@ oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx) */ mb_cqe = &mb->cqe; DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe)); - + /* copy mbox mbx back */ bcopy(mb_mbx, mbx, sizeof(struct oce_mbx)); @@ -547,7 +538,7 @@ oce_get_fw_config(POCE_SOFTC sc) sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot); sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot); } - + error: return ret; @@ -794,7 +785,6 @@ oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) uint8_t *tbl = fwcmd->params.req.cputable; struct oce_rq *rq = NULL; - for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { for_all_rss_queues(sc, rq, i) { if ((j + i) >= INDIRECTION_TABLE_ENTRIES) @@ -807,7 +797,7 @@ oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) rc = ENXIO; } - + /* fill log2 value indicating the size of the CPU table */ if (rc == 0) fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES)); @@ -860,7 +850,7 @@ oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss) fwcmd->params.req.if_id = LE_32(if_id); read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash)); - + rc = oce_rss_itbl_init(sc, fwcmd); if (rc == 0) { mbx.u0.s.embedded = 1; @@ -918,11 +908,10 @@ oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable) rc = oce_set_common_iface_rx_filter(sc, &sgl); oce_dma_free(sc, &sgl); - + return rc; } - /** * @brief Function modify and select rx filter options * @param sc software handle to the device @@ -1015,7 +1004,6 @@ error: return rc; } - /** * @brief Function to get NIC statistics * @param sc software handle to the device @@ -1069,7 +1057,6 @@ OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0); OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1); OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2); - /** * @brief Function to get pport (physical port) statistics * @param sc software handle to the device @@ -1098,7 +1085,7 @@ oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, fwcmd->params.req.reset_stats = reset_stats; fwcmd->params.req.port_number = sc->port_id; - + mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ mbx.u0.s.sge_count = 1; /* using scatter gather instead */ @@ -1123,7 +1110,6 @@ oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, return rc; } - /** * @brief Function to get vport (virtual port) statistics * @param sc software handle to the device @@ -1153,7 +1139,7 @@ oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, fwcmd->params.req.reset_stats = reset_stats; fwcmd->params.req.vport_number = sc->if_id; - + mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ mbx.u0.s.sge_count = 1; /* using scatter gather instead */ @@ -1178,7 +1164,6 @@ oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, return rc; } - /** * @brief Function to update the muticast filter with * values in dma_mem @@ -1225,7 +1210,6 @@ oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem) return rc; } - /** * @brief Function to send passthrough Ioctls * @param sc software handle to the device @@ -1256,7 +1240,6 @@ oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size) return rc; } - int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, uint32_t if_id, uint32_t *pmac_id) @@ -1296,7 +1279,6 @@ error: return rc; } - int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) { @@ -1332,8 +1314,6 @@ oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) return rc; } - - int oce_mbox_check_native_mode(POCE_SOFTC sc) { @@ -1377,8 +1357,6 @@ error: return 0; } - - int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, uint8_t loopback_type, uint8_t enable) @@ -1387,7 +1365,6 @@ oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, struct mbx_lowlevel_set_loopback_mode *fwcmd; int rc = 0; - bzero(&mbx, sizeof(struct oce_mbx)); fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload; @@ -1425,12 +1402,11 @@ oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, uint64_t pattern) { - + struct oce_mbx mbx; struct mbx_lowlevel_test_loopback_mode *fwcmd; int rc = 0; - bzero(&mbx, sizeof(struct oce_mbx)); fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload; @@ -1460,7 +1436,7 @@ oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, "%s failed - cmd status: %d addi status: %d\n", __FUNCTION__, rc, fwcmd->hdr.u0.rsp.additional_status); - + return rc; } @@ -1507,7 +1483,7 @@ oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, "%s failed - cmd status: %d addi status: %d\n", __FUNCTION__, rc, fwcmd->hdr.u0.rsp.additional_status); - + return rc; } @@ -1607,7 +1583,6 @@ error: } - int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, uint32_t data_offset, POCE_DMA_MEM pdma_mem, @@ -1664,8 +1639,6 @@ error: } - - int oce_mbox_create_rq(struct oce_rq *rq) { @@ -1689,7 +1662,7 @@ oce_mbox_create_rq(struct oce_rq *rq) /* oce_page_list will also prepare pages */ num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); - + if (IS_XE201(sc)) { fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; fwcmd->params.req.page_size = 1; @@ -1701,10 +1674,10 @@ oce_mbox_create_rq(struct oce_rq *rq) fwcmd->params.req.if_id = sc->if_id; fwcmd->params.req.max_frame_size = rq->cfg.mtu; fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue; - + mbx.u0.s.embedded = 1; mbx.payload_length = sizeof(struct mbx_create_nic_rq); - + rc = oce_mbox_post(sc, &mbx, NULL); if (!rc) rc = fwcmd->hdr.u0.rsp.status; @@ -1722,8 +1695,6 @@ error: } - - int oce_mbox_create_wq(struct oce_wq *wq) { @@ -1783,8 +1754,6 @@ error: } - - int oce_mbox_create_eq(struct oce_eq *eq) { @@ -1812,7 +1781,6 @@ oce_mbox_create_eq(struct oce_eq *eq) fwcmd->params.req.ctx.armed = 0; fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd; - mbx.u0.s.embedded = 1; mbx.payload_length = sizeof(struct mbx_create_common_eq); @@ -1831,8 +1799,6 @@ error: return rc; } - - int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) { @@ -1844,7 +1810,6 @@ oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) uint32_t num_pages, page_size; int rc = 0; - bzero(&mbx, sizeof(struct oce_mbx)); fwcmd = (struct mbx_create_common_cq *)&mbx.payload; @@ -2011,7 +1976,6 @@ oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, fwcmd->params.req.delay[i].dm = htole32(set_eqd[i].delay_multiplier); } - /* command post */ rc = oce_mbox_post(sc, &mbx, NULL); @@ -2116,7 +2080,6 @@ oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss) else sc->nrssqs = max_rss; sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ - } error: oce_dma_free(sc, &dma); @@ -2138,7 +2101,7 @@ oce_get_func_config(POCE_SOFTC sc) int i; boolean_t nic_desc_valid = FALSE; uint32_t max_rss = 0; - + if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) max_rss = OCE_LEGACY_MODE_RSS; else @@ -2367,4 +2330,3 @@ oce_mbox_create_rq_v2(struct oce_rq *rq) error: return rc; } - diff --git a/sys/dev/oce/oce_queue.c b/sys/dev/oce/oce_queue.c index 11619e267f56..04c92a5f397b 100644 --- a/sys/dev/oce/oce_queue.c +++ b/sys/dev/oce/oce_queue.c @@ -78,8 +78,6 @@ struct oce_cq *oce_cq_create(POCE_SOFTC sc, uint32_t nodelay, uint32_t ncoalesce); static void oce_cq_del(POCE_SOFTC sc, struct oce_cq *cq); - - /** * @brief Create and initialize all the queues on the board * @param sc software handle to the device @@ -122,7 +120,7 @@ oce_queue_init_all(POCE_SOFTC sc) aic->min_eqd = OCE_MIN_EQD; aic->et_eqd = OCE_MIN_EQD; aic->enable = TRUE; - + sc->eq[vector] = oce_eq_create(sc, sc->enable_hwlro ? EQ_LEN_2048 : EQ_LEN_1024, EQE_SIZE_4,0, vector); @@ -158,8 +156,6 @@ error: return 1; } - - /** * @brief Releases all mailbox queues created * @param sc software handle to the device @@ -199,8 +195,6 @@ oce_queue_release_all(POCE_SOFTC sc) } } - - /** * @brief Function to create a WQ for NIC Tx * @param sc software handle to the device @@ -248,7 +242,6 @@ oce_wq *oce_wq_init(POCE_SOFTC sc, uint32_t q_len, uint32_t wq_type) if (rc) goto free_wq; - for (i = 0; i < OCE_WQ_PACKET_ARRAY_SIZE; i++) { rc = bus_dmamap_create(wq->tag, 0, &wq->pckts[i].map); if (rc) @@ -259,10 +252,9 @@ oce_wq *oce_wq_init(POCE_SOFTC sc, uint32_t q_len, uint32_t wq_type) if (!wq->ring) goto free_wq; - LOCK_CREATE(&wq->tx_lock, "TX_lock"); LOCK_CREATE(&wq->tx_compl_lock, "WQ_HANDLER_LOCK"); - + /* Allocate buf ring for multiqueue*/ wq->br = buf_ring_alloc(4096, M_DEVBUF, M_WAITOK, &wq->tx_lock.mutex); @@ -270,15 +262,12 @@ oce_wq *oce_wq_init(POCE_SOFTC sc, uint32_t q_len, uint32_t wq_type) goto free_wq; return wq; - free_wq: device_printf(sc->dev, "Create WQ failed\n"); oce_wq_free(wq); return NULL; } - - /** * @brief Frees the work queue * @param wq pointer to work queue to free @@ -314,8 +303,6 @@ oce_wq_free(struct oce_wq *wq) free(wq, M_DEVBUF); } - - /** * @brief Create a work queue * @param wq pointer to work queue @@ -336,7 +323,6 @@ oce_wq_create(struct oce_wq *wq, struct oce_eq *eq) if (!cq) return ENXIO; - wq->cq = cq; rc = oce_mbox_create_wq(wq); @@ -361,9 +347,6 @@ error: return rc; } - - - /** * @brief Delete a work queue * @param wq pointer to work queue @@ -391,8 +374,6 @@ oce_wq_del(struct oce_wq *wq) } } - - /** * @brief function to allocate receive queue resources * @param sc software handle to the device @@ -413,7 +394,7 @@ oce_rq *oce_rq_init(POCE_SOFTC sc, if (OCE_LOG2(frag_size) <= 0) return NULL; - + if ((q_len == 0) || (q_len > 1024)) return NULL; @@ -422,7 +403,6 @@ oce_rq *oce_rq_init(POCE_SOFTC sc, if (!rq) return NULL; - rq->cfg.q_len = q_len; rq->cfg.frag_size = frag_size; rq->cfg.mtu = mtu; @@ -465,9 +445,6 @@ free_rq: return NULL; } - - - /** * @brief Free a receive queue * @param rq pointer to receive queue @@ -501,9 +478,6 @@ oce_rq_free(struct oce_rq *rq) free(rq, M_DEVBUF); } - - - /** * @brief Create a receive queue * @param rq receive queue @@ -539,9 +513,6 @@ oce_rq_create(struct oce_rq *rq, uint32_t if_id, struct oce_eq *eq) } - - - /** * @brief Delete a receive queue * @param rq receive queue @@ -575,8 +546,6 @@ oce_rq_del(struct oce_rq *rq) } } - - /** * @brief function to create an event queue * @param sc software handle to the device @@ -605,7 +574,7 @@ oce_eq *oce_eq_create(POCE_SOFTC sc, uint32_t q_len, eq->ring = oce_create_ring_buffer(sc, q_len, item_size); if (!eq->ring) goto free_eq; - + eq->eq_cfg.q_len = q_len; eq->eq_cfg.item_size = item_size; eq->eq_cfg.cur_eqd = (uint8_t) eq_delay; @@ -623,9 +592,6 @@ free_eq: return NULL; } - - - /** * @brief Function to delete an event queue * @param eq pointer to an event queue @@ -654,9 +620,6 @@ oce_eq_del(struct oce_eq *eq) } - - - /** * @brief Function to create an MQ * @param sc software handle to the device @@ -766,10 +729,6 @@ error: return mq; } - - - - /** * @brief Function to free a mailbox queue * @param mq pointer to a mailbox queue @@ -807,8 +766,6 @@ oce_mq_free(struct oce_mq *mq) mq = NULL; } - - /** * @brief Function to delete a EQ, CQ, MQ, WQ or RQ * @param sc sofware handle to the device @@ -869,8 +826,6 @@ oce_destroy_q(POCE_SOFTC sc, struct oce_mbx *mbx, size_t req_size, return rc; } - - /** * @brief Function to create a completion queue * @param sc software handle to the device @@ -901,7 +856,7 @@ oce_cq_create(POCE_SOFTC sc, struct oce_eq *eq, cq->ring = oce_create_ring_buffer(sc, q_len, item_size); if (!cq->ring) goto error; - + cq->parent = sc; cq->eq = eq; cq->cq_cfg.q_len = q_len; @@ -922,8 +877,6 @@ error: return NULL; } - - /** * @brief Deletes the completion queue * @param sc software handle to the device @@ -936,7 +889,6 @@ oce_cq_del(POCE_SOFTC sc, struct oce_cq *cq) struct mbx_destroy_common_cq *fwcmd; if (cq->ring != NULL) { - bzero(&mbx, sizeof(struct oce_mbx)); /* now fill the command */ fwcmd = (struct mbx_destroy_common_cq *)&mbx.payload; @@ -952,8 +904,6 @@ oce_cq_del(POCE_SOFTC sc, struct oce_cq *cq) cq = NULL; } - - /** * @brief Start a receive queue * @param rq pointer to a receive queue @@ -975,8 +925,6 @@ oce_start_rq(struct oce_rq *rq) return rc; } - - /** * @brief Start a work queue * @param wq pointer to a work queue @@ -988,8 +936,6 @@ oce_start_wq(struct oce_wq *wq) return 0; } - - /** * @brief Start a mailbox queue * @param mq pointer to a mailbox queue @@ -1001,8 +947,6 @@ oce_start_mq(struct oce_mq *mq) return 0; } - - /** * @brief Function to arm an EQ so that it can generate events * @param sc software handle to the device @@ -1027,9 +971,6 @@ oce_arm_eq(POCE_SOFTC sc, } - - - /** * @brief Function to arm a CQ with CQEs * @param sc software handle to the device @@ -1049,9 +990,6 @@ void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm) } - - - /* * @brief function to cleanup the eqs used during stop * @param eq pointer to event queue structure @@ -1078,11 +1016,9 @@ oce_drain_eq(struct oce_eq *eq) } while (TRUE); oce_arm_eq(sc, eq->eq_id, num_eqe, FALSE, TRUE); - + } - - void oce_drain_wq_cq(struct oce_wq *wq) { @@ -1110,7 +1046,6 @@ oce_drain_wq_cq(struct oce_wq *wq) } - /* * @brief function to drain a MCQ and process its CQEs * @param dev software handle to the device @@ -1124,8 +1059,6 @@ oce_drain_mq_cq(void *arg) return; } - - /** * @brief function to process a Recieve queue * @param arg pointer to the RQ to charge @@ -1155,14 +1088,12 @@ oce_drain_rq_cq(struct oce_rq *rq) return; } - void oce_free_posted_rxbuf(struct oce_rq *rq) { struct oce_packet_desc *pd; - - while (rq->pending) { + while (rq->pending) { pd = &rq->pckts[rq->ring->cidx]; bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(rq->tag, pd->map); @@ -1254,7 +1185,6 @@ exit_rx_cq_clean_hwlro: return; } - void oce_rx_cq_clean(struct oce_rq *rq) { @@ -1265,7 +1195,7 @@ oce_rx_cq_clean(struct oce_rq *rq) int flush_compl = 0; sc = rq->parent; cq = rq->cq; - + for (;;) { bus_dmamap_sync(cq->ring->dma.tag, cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); @@ -1308,7 +1238,7 @@ oce_stop_rx(POCE_SOFTC sc) struct mbx_delete_nic_rq_v1 *fwcmd1; struct oce_rq *rq; int i = 0; - + /* before deleting disable hwlro */ if(sc->enable_hwlro) oce_mbox_nic_set_iface_lro_config(sc, 0); @@ -1346,14 +1276,12 @@ oce_stop_rx(POCE_SOFTC sc) } } - - int oce_start_rx(POCE_SOFTC sc) { struct oce_rq *rq; int rc = 0, i; - + for_all_rq_queues(sc, rq, i) { if (rq->qstate == QCREATED) continue; @@ -1374,7 +1302,7 @@ oce_start_rx(POCE_SOFTC sc) rq->ring->cidx = 0; rq->ring->pidx = 0; } - + if(sc->enable_hwlro) { rc = oce_mbox_nic_set_iface_lro_config(sc, 1); if (rc) @@ -1382,13 +1310,12 @@ oce_start_rx(POCE_SOFTC sc) } DELAY(1); - + /* RSS config */ if (is_rss_enabled(sc)) { rc = oce_config_nic_rss(sc, (uint8_t) sc->if_id, RSS_ENABLE); if (rc) goto error; - } DELAY(1); @@ -1398,6 +1325,3 @@ error: return rc; } - - - diff --git a/sys/dev/oce/oce_sysctl.c b/sys/dev/oce/oce_sysctl.c index 95f22fa1aa58..bfe4d042af1c 100644 --- a/sys/dev/oce/oce_sysctl.c +++ b/sys/dev/oce/oce_sysctl.c @@ -64,7 +64,6 @@ static void oce_add_stats_sysctls_xe201(POCE_SOFTC sc, struct sysctl_ctx_list *ctx, struct sysctl_oid *stats_node); - extern char component_revision[32]; uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; @@ -160,10 +159,8 @@ oce_add_sysctls(POCE_SOFTC sc) else oce_add_stats_sysctls_xe201(sc, ctx, stats_node); - } - static uint32_t oce_loopback_test(struct oce_softc *sc, uint8_t loopback_type) { @@ -249,7 +246,6 @@ oce_sysctl_loopback(SYSCTL_HANDLER_ARGS) return 0; } - static int oce_sys_fwupgrade(SYSCTL_HANDLER_ARGS) { @@ -435,7 +431,6 @@ oce_sh_be3_flashdata(POCE_SOFTC sc, const struct firmware *fw, int32_t num_imgs) num_imgs = MAX_FLASH_COMP; for (i = 0; i < num_imgs; i++) { - bzero(&imgatt, sizeof(struct flash_img_attri)); oce_fill_flash_img_data(sc, fsec, &imgatt, i, fw, bin_offset); @@ -452,7 +447,6 @@ oce_sh_be3_flashdata(POCE_SOFTC sc, const struct firmware *fw, int32_t num_imgs) } while (imgatt.img_size) { - if (imgatt.img_size > 32*1024) num_bytes = 32*1024; else @@ -477,9 +471,7 @@ oce_sh_be3_flashdata(POCE_SOFTC sc, const struct firmware *fw, int32_t num_imgs) } /* Leave the CPU for others for some time */ pause("yield", 10); - } - } ret: @@ -517,7 +509,6 @@ be_get_ufi_exit: return -1; } - static int oce_skyhawk_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) { @@ -559,7 +550,6 @@ oce_skyhawk_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) default: rc = -1; break; - } } @@ -596,7 +586,6 @@ oce_be3_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) return rc; } - static boolean_t oce_phy_flashing_required(POCE_SOFTC sc) { @@ -615,7 +604,6 @@ oce_phy_flashing_required(POCE_SOFTC sc) return FALSE; } - static boolean_t oce_img_flashing_required(POCE_SOFTC sc, const char *p, int img_optype, uint32_t img_offset, @@ -641,7 +629,6 @@ oce_img_flashing_required(POCE_SOFTC sc, const char *p, return FALSE; } - static int oce_lancer_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) { @@ -686,7 +673,6 @@ oce_lancer_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) data += data_written; offset += data_written; pause("yield", 10); - } if (!rc) @@ -703,7 +689,6 @@ oce_lancer_fwupgrade(POCE_SOFTC sc, const struct firmware *fw) } - static void oce_add_stats_sysctls_be3(POCE_SOFTC sc, struct sysctl_ctx_list *ctx, @@ -724,7 +709,6 @@ oce_add_stats_sysctls_be3(POCE_SOFTC sc, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Ethernet Statistics"); rx_stat_list = SYSCTL_CHILDREN(rx_stats_node); - SYSCTL_ADD_QUAD(ctx, rx_stat_list, OID_AUTO, "total_pkts", CTLFLAG_RD, &stats->rx.t_rx_pkts, "Total Received Packets"); @@ -752,7 +736,7 @@ oce_add_stats_sysctls_be3(POCE_SOFTC sc, SYSCTL_ADD_UINT(ctx, rx_stat_list, OID_AUTO, "control_frames", CTLFLAG_RD, &stats->u0.be.rx_control_frames, 0, "Control Frames"); - + for (i = 0; i < sc->nrqs; i++) { sprintf(prefix, "queue%d",i); queue_stats_node = SYSCTL_ADD_NODE(ctx, @@ -786,12 +770,12 @@ oce_add_stats_sysctls_be3(POCE_SOFTC sc, "num of packet drops due to no fragments"); } } - + rx_stats_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(rx_stats_node), OID_AUTO, "err", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Receive Error Stats"); rx_stat_list = SYSCTL_CHILDREN(rx_stats_node); - + SYSCTL_ADD_UINT(ctx, rx_stat_list, OID_AUTO, "crc_errs", CTLFLAG_RD, &stats->u0.be.rx_crc_errors, 0, "CRC Errors"); @@ -916,12 +900,10 @@ oce_add_stats_sysctls_be3(POCE_SOFTC sc, "ipv6_ext_hdr_tx_drop",CTLFLAG_RD, &sc->wq[i]->tx_stats.ipv6_ext_hdr_tx_drop, 0, "Transmit IPV6 Ext Header Drop"); - } return; } - static void oce_add_stats_sysctls_xe201(POCE_SOFTC sc, struct sysctl_ctx_list *ctx, @@ -943,7 +925,6 @@ oce_add_stats_sysctls_xe201(POCE_SOFTC sc, "RX Ethernet Statistics"); rx_stat_list = SYSCTL_CHILDREN(rx_stats_node); - SYSCTL_ADD_QUAD(ctx, rx_stat_list, OID_AUTO, "total_pkts", CTLFLAG_RD, &stats->rx.t_rx_pkts, "Total Received Packets"); @@ -968,7 +949,7 @@ oce_add_stats_sysctls_xe201(POCE_SOFTC sc, SYSCTL_ADD_UQUAD(ctx, rx_stat_list, OID_AUTO, "control_frames", CTLFLAG_RD, &stats->u0.xe201.rx_control_frames, "Control Frames"); - + for (i = 0; i < sc->nrqs; i++) { sprintf(prefix, "queue%d",i); queue_stats_node = SYSCTL_ADD_NODE(ctx, @@ -1003,7 +984,7 @@ oce_add_stats_sysctls_xe201(POCE_SOFTC sc, SYSCTL_CHILDREN(rx_stats_node), OID_AUTO, "err", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Receive Error Stats"); rx_stat_list = SYSCTL_CHILDREN(rx_stats_node); - + SYSCTL_ADD_UQUAD(ctx, rx_stat_list, OID_AUTO, "crc_errs", CTLFLAG_RD, &stats->u0.xe201.rx_crc_errors, "CRC Errors"); @@ -1115,12 +1096,10 @@ oce_add_stats_sysctls_xe201(POCE_SOFTC sc, "ipv6_ext_hdr_tx_drop", CTLFLAG_RD, &sc->wq[i]->tx_stats.ipv6_ext_hdr_tx_drop, 0, "Transmit IPV6 Ext Header Drop"); - } return; } - void oce_refresh_queue_stats(POCE_SOFTC sc) { @@ -1128,9 +1107,9 @@ oce_refresh_queue_stats(POCE_SOFTC sc) int i; adapter_stats = &sc->oce_stats_info; - + /* Caluculate total TX and TXstats from all queues */ - + bzero(&adapter_stats->rx, sizeof(struct oce_rx_stats)); for (i = 0; i < sc->nrqs; i++) { @@ -1158,8 +1137,6 @@ oce_refresh_queue_stats(POCE_SOFTC sc) } - - static void copy_stats_to_sc_xe201(POCE_SOFTC sc) { @@ -1299,8 +1276,6 @@ copy_stats_to_sc_xe201(POCE_SOFTC sc) port_stats->rx_pkts_8192_to_9216_bytes; } - - static void copy_stats_to_sc_be2(POCE_SOFTC sc) { @@ -1315,10 +1290,9 @@ copy_stats_to_sc_be2(POCE_SOFTC sc) pmem = &nic_mbx->params.rsp.stats.pmem; rxf_stats = &nic_mbx->params.rsp.stats.rxf; port_stats = &nic_mbx->params.rsp.stats.rxf.port[port]; - + adapter_stats = &sc->oce_stats_info.u0.be; - /* Update stats */ adapter_stats->rx_pause_frames = port_stats->rx_pause_frames; adapter_stats->rx_crc_errors = port_stats->rx_crc_errors; @@ -1346,7 +1320,7 @@ copy_stats_to_sc_be2(POCE_SOFTC sc) port_stats->rx_alignment_symbol_errors; adapter_stats->tx_pauseframes = port_stats->tx_pauseframes; adapter_stats->tx_controlframes = port_stats->tx_controlframes; - + if (sc->if_id) adapter_stats->jabber_events = rxf_stats->port1_jabber_events; else @@ -1365,7 +1339,6 @@ copy_stats_to_sc_be2(POCE_SOFTC sc) adapter_stats->eth_red_drops = pmem->eth_red_drops; } - static void copy_stats_to_sc_be3(POCE_SOFTC sc) { @@ -1500,14 +1473,11 @@ copy_stats_to_sc_sh(POCE_SOFTC sc) sc->rq[i]->rx_stats.rx_drops_no_frags = erx_stats->rx_drops_no_fragments[sc->rq[i]->rq_id]; } - - int oce_stats_init(POCE_SOFTC sc) { int rc = 0, sz = 0; - if( IS_BE2(sc) ) sz = sizeof(struct mbx_get_nic_stats_v0); else if( IS_BE3(sc) ) @@ -1522,7 +1492,6 @@ oce_stats_init(POCE_SOFTC sc) return rc; } - void oce_stats_free(POCE_SOFTC sc) { @@ -1531,7 +1500,6 @@ oce_stats_free(POCE_SOFTC sc) } - int oce_refresh_nic_stats(POCE_SOFTC sc) { diff --git a/sys/dev/oce/oce_user.h b/sys/dev/oce/oce_user.h index ae1f96d5d317..b38665898270 100644 --- a/sys/dev/oce/oce_user.h +++ b/sys/dev/oce/oce_user.h @@ -78,7 +78,6 @@ struct oce_dev_info { #define OCE_RDMA_INFO_RDMA_SUPPORTED 0x00000001 }; - #define OCE_GEN2_FAMILY 2 #ifdef notdef diff --git a/sys/dev/oce/oce_util.c b/sys/dev/oce/oce_util.c index fefea2e16eb7..464f441d0e04 100644 --- a/sys/dev/oce/oce_util.c +++ b/sys/dev/oce/oce_util.c @@ -60,7 +60,6 @@ oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags) { int rc; - memset(dma, 0, sizeof(OCE_DMA_MEM)); rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), @@ -121,12 +120,10 @@ oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma) bus_dma_tag_destroy(dma->tag); dma->tag = NULL; - + return; } - - /** * @brief Map DMA memory segment addresses * @param arg physical address pointer @@ -145,8 +142,6 @@ oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error) *paddr = segs->ds_addr; } - - /** * @brief Destroy a ring buffer * @param sc software handle to the device @@ -160,8 +155,6 @@ oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring) free(ring, M_DEVBUF); } - - oce_ring_buffer_t * oce_create_ring_buffer(POCE_SOFTC sc, uint32_t q_len, uint32_t item_size) @@ -170,7 +163,6 @@ oce_create_ring_buffer(POCE_SOFTC sc, int rc; oce_ring_buffer_t *ring; - ring = malloc(sizeof(oce_ring_buffer_t), M_DEVBUF, M_NOWAIT | M_ZERO); if (ring == NULL) return NULL; @@ -187,7 +179,6 @@ oce_create_ring_buffer(POCE_SOFTC sc, if (rc) goto fail; - rc = bus_dmamem_alloc(ring->dma.tag, &ring->dma.ptr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, @@ -199,9 +190,9 @@ oce_create_ring_buffer(POCE_SOFTC sc, bus_dmamap_sync(ring->dma.tag, ring->dma.map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ring->dma.paddr = 0; - + return ring; - + fail: oce_dma_free(sc, &ring->dma); free(ring, M_DEVBUF); @@ -209,16 +200,12 @@ fail: return NULL; } - - struct _oce_dmamap_paddr_table { uint32_t max_entries; uint32_t num_entries; struct phys_addr *paddrs; }; - - /** * @brief Map ring buffer * @param arg dma map phyical address table pointer @@ -244,8 +231,6 @@ oce_dma_map_ring(void *arg, bus_dma_segment_t * segs, int nseg, int error) } } - - /** * @brief Load bus dma map for a ring buffer * @param ring ring buffer pointer