Allow operation with UTMI+ phy.
Submitted by: kan Sponsored by: DARPA, AFRL
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a8d6954281
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cec8009ca1
@ -98,10 +98,6 @@
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GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \
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GINTSTS_SESSREQINT)
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#define DWC_OTG_PHY_ULPI 0
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#define DWC_OTG_PHY_HSIC 1
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#define DWC_OTG_PHY_INTERNAL 2
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#ifndef DWC_OTG_PHY_DEFAULT
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#define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
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#endif
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@ -110,10 +106,10 @@ static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
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static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG");
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SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
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&dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL");
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&dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+");
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#ifdef USB_DEBUG
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static int dwc_otg_debug;
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static int dwc_otg_debug = 0;
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SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
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&dwc_otg_debug, 0, "DWC OTG debug level");
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@ -3889,8 +3885,13 @@ dwc_otg_init(struct dwc_otg_softc *sc)
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break;
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}
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/* select HSIC, ULPI or internal PHY mode */
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switch (dwc_otg_phy_type) {
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if (sc->sc_phy_type == 0)
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sc->sc_phy_type = dwc_otg_phy_type + 1;
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if (sc->sc_phy_bits == 0)
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sc->sc_phy_bits = 16;
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/* select HSIC, ULPI, UTMI+ or internal PHY mode */
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switch (sc->sc_phy_type) {
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case DWC_OTG_PHY_HSIC:
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DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
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GUSBCFG_PHYIF |
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@ -3910,6 +3911,16 @@ dwc_otg_init(struct dwc_otg_softc *sc)
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GUSBCFG_TRD_TIM_SET(5) | temp);
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DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
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temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
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DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
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temp & ~GLPMCFG_HSIC_CONN);
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break;
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case DWC_OTG_PHY_UTMI:
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DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
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(sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) |
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GUSBCFG_TRD_TIM_SET(5) | temp);
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DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
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temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
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DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
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temp & ~GLPMCFG_HSIC_CONN);
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@ -191,6 +191,13 @@ struct dwc_otg_softc {
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uint16_t sc_active_rx_ep;
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uint16_t sc_last_frame_num;
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uint8_t sc_phy_type;
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uint8_t sc_phy_bits;
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#define DWC_OTG_PHY_ULPI 1
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#define DWC_OTG_PHY_HSIC 2
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#define DWC_OTG_PHY_INTERNAL 3
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#define DWC_OTG_PHY_UTMI 4
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uint8_t sc_timer_active;
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uint8_t sc_dev_ep_max;
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uint8_t sc_dev_in_ep_max;
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