Change the PIO loops from a hard counter into a loop that calls DELAY()
in each cycle, with a tunable max cycle count defined in fdreg.h. This is said to fix the problem on some Compaq hardware (and perhaps on other machines using the Natsemi PC87317 chip) where the fdc(4) driver failed to operate at all. PR: kern/21397 Submitted by: Jung-uk Kim <jkim@niksun.com> MFC after: 3 days
This commit is contained in:
Joerg Wunsch
parent
d147c3da04
commit
d0900d6bc0
@ -563,13 +563,15 @@ enable_fifo(fdc_p fdc)
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return fdc_err(fdc, "Enable FIFO failed\n");
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/* If command is invalid, return */
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j = 100000;
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j = FDSTS_TIMEOUT;
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while ((i = fdsts_rd(fdc) & (NE7_DIO | NE7_RQM))
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!= NE7_RQM && j-- > 0)
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!= NE7_RQM && j-- > 0) {
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if (i == (NE7_DIO | NE7_RQM)) {
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fdc_reset(fdc);
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return FD_FAILED;
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}
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DELAY(1);
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}
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if (j<0 ||
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fd_cmd(fdc, 3,
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0, (fifo_threshold - 1) & 0xf, 0, 0) < 0) {
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@ -1473,11 +1475,13 @@ fdc_reset(fdc_p fdc)
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static int
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fd_in(struct fdc_data *fdc, int *ptr)
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{
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int i, j = 100000;
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int i, j = FDSTS_TIMEOUT;
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while ((i = fdsts_rd(fdc) & (NE7_DIO|NE7_RQM))
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!= (NE7_DIO|NE7_RQM) && j-- > 0)
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!= (NE7_DIO|NE7_RQM) && j-- > 0) {
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if (i == NE7_RQM)
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return fdc_err(fdc, "ready for output in input\n");
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DELAY(1);
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}
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if (j <= 0)
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return fdc_err(fdc, bootverbose? "input ready timeout\n": 0);
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#ifdef FDC_DEBUG
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@ -1499,13 +1503,15 @@ out_fdc(struct fdc_data *fdc, int x)
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int i;
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/* Check that the direction bit is set */
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i = 100000;
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while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0);
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i = FDSTS_TIMEOUT;
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while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0)
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DELAY(1);
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if (i <= 0) return fdc_err(fdc, "direction bit not set\n");
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/* Check that the floppy controller is ready for a command */
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i = 100000;
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while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0);
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i = FDSTS_TIMEOUT;
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while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0)
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DELAY(1);
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if (i <= 0)
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return fdc_err(fdc, bootverbose? "output ready timeout\n": 0);
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@ -69,3 +69,15 @@
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#define FDI_DCHG 0x80 /* diskette has been changed */
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/* requires drive and motor being selected */
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/* is cleared by any step pulse to drive */
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/*
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* Timeout value for the PIO loops to wait until the FDC main status
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* register matches our expextations (request for master, direction
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* bit). This is the number of cycles to loop while waiting, with a
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* 1-microsecond (in theory) DELAY() in each cycle. In particular on
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* slower hardware, it could take a fair amount more to execute. Of
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* course, as soon as the FDC main status register indicates the correct
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* bits are set, the loop will terminate, so this is merely a safety
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* measure to avoid looping forever in case of broken hardware.
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*/
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#define FDSTS_TIMEOUT 200
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22
sys/isa/fd.c
22
sys/isa/fd.c
@ -563,13 +563,15 @@ enable_fifo(fdc_p fdc)
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return fdc_err(fdc, "Enable FIFO failed\n");
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/* If command is invalid, return */
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j = 100000;
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j = FDSTS_TIMEOUT;
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while ((i = fdsts_rd(fdc) & (NE7_DIO | NE7_RQM))
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!= NE7_RQM && j-- > 0)
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!= NE7_RQM && j-- > 0) {
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if (i == (NE7_DIO | NE7_RQM)) {
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fdc_reset(fdc);
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return FD_FAILED;
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}
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DELAY(1);
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}
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if (j<0 ||
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fd_cmd(fdc, 3,
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0, (fifo_threshold - 1) & 0xf, 0, 0) < 0) {
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@ -1473,11 +1475,13 @@ fdc_reset(fdc_p fdc)
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static int
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fd_in(struct fdc_data *fdc, int *ptr)
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{
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int i, j = 100000;
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int i, j = FDSTS_TIMEOUT;
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while ((i = fdsts_rd(fdc) & (NE7_DIO|NE7_RQM))
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!= (NE7_DIO|NE7_RQM) && j-- > 0)
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!= (NE7_DIO|NE7_RQM) && j-- > 0) {
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if (i == NE7_RQM)
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return fdc_err(fdc, "ready for output in input\n");
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DELAY(1);
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}
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if (j <= 0)
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return fdc_err(fdc, bootverbose? "input ready timeout\n": 0);
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#ifdef FDC_DEBUG
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@ -1499,13 +1503,15 @@ out_fdc(struct fdc_data *fdc, int x)
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int i;
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/* Check that the direction bit is set */
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i = 100000;
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while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0);
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i = FDSTS_TIMEOUT;
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while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0)
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DELAY(1);
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if (i <= 0) return fdc_err(fdc, "direction bit not set\n");
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/* Check that the floppy controller is ready for a command */
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i = 100000;
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while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0);
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i = FDSTS_TIMEOUT;
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while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0)
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DELAY(1);
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if (i <= 0)
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return fdc_err(fdc, bootverbose? "output ready timeout\n": 0);
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@ -69,3 +69,15 @@
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#define FDI_DCHG 0x80 /* diskette has been changed */
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/* requires drive and motor being selected */
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/* is cleared by any step pulse to drive */
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/*
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* Timeout value for the PIO loops to wait until the FDC main status
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* register matches our expextations (request for master, direction
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* bit). This is the number of cycles to loop while waiting, with a
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* 1-microsecond (in theory) DELAY() in each cycle. In particular on
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* slower hardware, it could take a fair amount more to execute. Of
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* course, as soon as the FDC main status register indicates the correct
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* bits are set, the loop will terminate, so this is merely a safety
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* measure to avoid looping forever in case of broken hardware.
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*/
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#define FDSTS_TIMEOUT 200
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