MFp4: Omnibus ed changes
o Attach AX88x90's MII bus to system, and require its presence.
o Reorg the mii code a little, and move more of it into pccard attachment.
o Eliminate ed_pccard_{read,write}_attrmem in favor of a more appropriate
function in the pccard layer.
o Update comments to reflect knowledge gained.
o Update how re recognize a NE-2000 ROM. I found a couple of different
datasheets that define the structure of the PROM data, so the code's
old heuristics have been removed, and comments updated to reflect the
structure.
o Eliminate work around for EC2T. It is no longer needed, and was wrong
headed since the EC2T has a Winbound 82C926C in it, not a AX88x90.
o Add copyright to if_ed_pccard.c, since I believe I've re-written more than
3/4 of it.
# With these changes, all of my 20-odd ed based cards work, except for the
# NetGear FA-410, and I'm pretty sure that's a MII/PHY problem.
This commit is contained in:
Warner Losh
parent
ff1de32e3b
commit
d21d33847c
@ -1635,43 +1635,6 @@ ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
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}
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#ifndef ED_NO_MIIBUS
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/*
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* MII bus support routines.
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*/
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int
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ed_miibus_readreg(device_t dev, int phy, int reg)
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{
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struct ed_softc *sc;
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int failed, val;
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sc = device_get_softc(dev);
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(*sc->mii_writebits)(sc, 0xffffffff, 32);
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(*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
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(*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
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(*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
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(*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
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failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
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val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
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(*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
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return (failed ? 0 : val);
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}
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void
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ed_miibus_writereg(device_t dev, int phy, int reg, int data)
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{
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struct ed_softc *sc;
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sc = device_get_softc(dev);
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(*sc->mii_writebits)(sc, 0xffffffff, 32);
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(*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
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(*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
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(*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
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(*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
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(*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
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(*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
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(*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
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}
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int
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ed_ifmedia_upd(struct ifnet *ifp)
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{
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@ -1,4 +1,5 @@
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/*-
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* Copyright (c) 2005, M. Warner Losh
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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@ -51,6 +52,7 @@
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#include <dev/ed/if_edreg.h>
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#include <dev/ed/if_edvar.h>
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#include <dev/pccard/pccardvar.h>
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#include <dev/pccard/pccardreg.h>
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#include <dev/pccard/pccard_cis.h>
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#ifndef ED_NO_MIIBUS
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#include <dev/mii/mii.h>
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@ -79,7 +81,9 @@ MODULE_DEPEND(ed, ether, 1, 1, 1);
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*
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* This applies only to the older, NE-2000 compatbile cards. The newer
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* cards based on the AX88x90 or DL100XX chipsets have a specific place
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* to look for MAC information.
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* to look for MAC information. And only to those NE-2000 compatible cards
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* that don't the NE-2000 compatible thing of placing the PROM contents
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* starting at location 0 of memory.
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*/
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#define ED_DEFAULT_MAC_OFFSET 0xff0
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@ -186,15 +190,18 @@ static const struct ed_product {
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static int ed_pccard_probe(device_t);
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static int ed_pccard_attach(device_t);
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static int ed_pccard_memread(device_t dev, off_t offset, u_char *byte);
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static int ed_pccard_memwrite(device_t dev, off_t offset, u_char byte);
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static int ed_pccard_dl100xx(device_t dev, const struct ed_product *);
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#ifndef ED_NO_MIIBUS
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static void ed_pccard_dl10xx_mii_reset(struct ed_softc *sc);
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static u_int ed_pccard_dl10xx_mii_readbits(struct ed_softc *sc, int nbits);
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static void ed_pccard_dl10xx_mii_writebits(struct ed_softc *sc, u_int val,
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static void ed_pccard_dl100xx_mii_reset(struct ed_softc *sc);
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static u_int ed_pccard_dl100xx_mii_readbits(struct ed_softc *sc, int nbits);
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static void ed_pccard_dl100xx_mii_writebits(struct ed_softc *sc, u_int val,
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int nbits);
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static void ed_pccard_ax88x90_mii_reset(struct ed_softc *sc);
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static u_int ed_pccard_ax88x90_mii_readbits(struct ed_softc *sc, int nbits);
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static void ed_pccard_ax88x90_mii_writebits(struct ed_softc *sc, u_int val,
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int nbits);
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static int ed_miibus_readreg(device_t dev, int phy, int reg);
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#endif
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static int ed_pccard_ax88x90(device_t dev, const struct ed_product *);
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@ -232,25 +239,50 @@ static int
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ed_pccard_rom_mac(device_t dev, uint8_t *enaddr)
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{
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struct ed_softc *sc = device_get_softc(dev);
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uint8_t romdata[16];
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uint8_t romdata[32];
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int i;
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/*
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* Read in the rom data at location 0. We should see one of
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* two patterns. Either you'll see odd locations 0xff and
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* even locations data, or you'll see odd and even locations
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* mirror each other. In addition, the last two even locations
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* should be 0. If they aren't 0, then we'll assume that
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* there's no valid ROM data on this card and try another method
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* to recover the MAC address. Since there are no NE-1000
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* based PC Card devices, we'll assume we're 16-bit.
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* Read in the rom data at location 0. Since there are no
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* NE-1000 based PC Card devices, we'll assume we're 16-bit.
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*
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* In researching what format this takes, I've found that the
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* following appears to be true for multiple cards based on
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* observation as well as datasheet digging.
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*
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* Data is stored in some ROM and is copied out 8 bits at a time
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* into 16-bit wide locations. This means that the odd locations
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* of the ROM are not used (and can be either 0 or ff).
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*
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* The contents appears to be as follows:
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* PROM RAM
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* Offset Offset What
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* 0 0 ENETADDR 0
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* 1 2 ENETADDR 1
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* 2 4 ENETADDR 2
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* 3 6 ENETADDR 3
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* 4 8 ENETADDR 4
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* 5 10 ENETADDR 5
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* 6-13 12-26 Reserved (varies by manufacturer)
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* 14 28 0x57
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* 15 30 0x57
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*
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* Some manufacturers have another image of enetaddr from
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* PROM offset 0x10 to 0x15 with 0x42 in 0x1e and 0x1f, but
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* this doesn't appear to be universally documented in the
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* datasheets. Some manufactuers have a card type, card config
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* checksums, etc encoded into PROM offset 6-13, but deciphering it
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* requires more knowledge about the exact underlying chipset than
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* we possess (and maybe can possess).
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*/
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ed_pio_readmem(sc, 0, romdata, 16);
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if (romdata[12] != 0 || romdata[14] != 0)
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return 0;
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ed_pio_readmem(sc, 0, romdata, 32);
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if (bootverbose)
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printf("ROM DATA: %32D\n", romdata, " ");
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if (romdata[28] != 0x57 || romdata[30] != 0x57)
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return (0);
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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enaddr[i] = romdata[i * 2];
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return 1;
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return (1);
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}
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static int
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@ -311,7 +343,7 @@ ed_pccard_attach(device_t dev)
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error = ENXIO;
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if (error != 0)
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error = ed_pccard_dl100xx(dev, pp);
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if (error != 0 && pp->flags & NE2000DVF_AX88X90)
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if (error != 0)
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error = ed_pccard_ax88x90(dev, pp);
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if (error != 0)
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error = ed_probe_Novell_generic(dev, device_get_flags(dev));
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@ -349,17 +381,17 @@ ed_pccard_attach(device_t dev)
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}
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if (sum == 0 && pp->flags & NE2000DVF_ENADDR) {
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for (i = 0; i < ETHER_ADDR_LEN; i++) {
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ed_pccard_memread(dev, pp->enoff + i * 2,
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pccard_attr_read_1(dev, pp->enoff + i * 2,
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enaddr + i);
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sum |= enaddr[i];
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}
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if (bootverbose)
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device_printf(dev, "Hint MAC %6D\n", enaddr,
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":");
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device_printf(dev, "Hint %x MAC %6D\n",
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pp->enoff, enaddr, ":");
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}
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if (sum == 0) {
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for (i = 0; i < ETHER_ADDR_LEN; i++) {
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ed_pccard_memread(dev, ED_DEFAULT_MAC_OFFSET +
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pccard_attr_read_1(dev, ED_DEFAULT_MAC_OFFSET +
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i * 2, enaddr + i);
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sum |= enaddr[i];
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}
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@ -382,11 +414,17 @@ ed_pccard_attach(device_t dev)
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if (sc->chip_type == ED_CHIP_TYPE_DL10019 ||
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sc->chip_type == ED_CHIP_TYPE_DL10022) {
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/* Probe for an MII bus, but ignore errors. */
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ed_pccard_dl10xx_mii_reset(sc);
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sc->mii_readbits = ed_pccard_dl10xx_mii_readbits;
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sc->mii_writebits = ed_pccard_dl10xx_mii_writebits;
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ed_pccard_dl100xx_mii_reset(sc);
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mii_phy_probe(dev, &sc->miibus, ed_ifmedia_upd,
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ed_ifmedia_sts);
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} else if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
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ed_pccard_ax88x90_mii_reset(sc);
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if ((error = mii_phy_probe(dev, &sc->miibus, ed_ifmedia_upd,
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ed_ifmedia_sts)) != 0) {
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device_printf(dev, "Missing mii!\n");
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goto bad;
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}
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}
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#endif
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if (sc->modem_rid != -1)
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@ -397,52 +435,6 @@ ed_pccard_attach(device_t dev)
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return (error);
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}
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static int
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ed_pccard_memwrite(device_t dev, off_t offset, u_char byte)
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{
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int cis_rid;
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struct resource *cis;
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cis_rid = 0;
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cis = bus_alloc_resource(dev, SYS_RES_MEMORY, &cis_rid, 0, ~0,
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4 << 10, RF_ACTIVE | RF_SHAREABLE);
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if (cis == NULL)
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return (ENXIO);
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CARD_SET_RES_FLAGS(device_get_parent(dev), dev, SYS_RES_MEMORY,
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cis_rid, PCCARD_A_MEM_ATTR);
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bus_space_write_1(rman_get_bustag(cis), rman_get_bushandle(cis),
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offset, byte);
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bus_deactivate_resource(dev, SYS_RES_MEMORY, cis_rid, cis);
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bus_release_resource(dev, SYS_RES_MEMORY, cis_rid, cis);
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return (0);
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}
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static int
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ed_pccard_memread(device_t dev, off_t offset, u_char *byte)
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{
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int cis_rid;
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struct resource *cis;
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cis_rid = 0;
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cis = bus_alloc_resource(dev, SYS_RES_MEMORY, &cis_rid, 0, ~0,
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4 << 10, RF_ACTIVE | RF_SHAREABLE);
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if (cis == NULL)
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return (ENXIO);
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CARD_SET_RES_FLAGS(device_get_parent(dev), dev, SYS_RES_MEMORY,
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cis_rid, PCCARD_A_MEM_ATTR);
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*byte = bus_space_read_1(rman_get_bustag(cis), rman_get_bushandle(cis),
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offset);
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bus_deactivate_resource(dev, SYS_RES_MEMORY, cis_rid, cis);
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bus_release_resource(dev, SYS_RES_MEMORY, cis_rid, cis);
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return (0);
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}
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/*
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* Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100
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* and compatible cards (DL10019C Ethernet controller).
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@ -459,9 +451,13 @@ ed_pccard_dl100xx(device_t dev, const struct ed_product *pp)
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uint8_t id;
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int i, error;
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if (!pp->flags & NE2000DVF_DL100XX)
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if (!(pp->flags & NE2000DVF_DL100XX))
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return (ENXIO);
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if (bootverbose)
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device_printf(dev, "Trying DL100xx probing\n");
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error = ed_probe_Novell_generic(dev, device_get_flags(dev));
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if (bootverbose && error)
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device_printf(dev, "Novell generic probe failed: %d\n", error);
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if (error != 0)
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return (error);
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@ -474,8 +470,13 @@ ed_pccard_dl100xx(device_t dev, const struct ed_product *pp)
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*/
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for (sum = 0, i = 0x04; i < 0x0c; i++)
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sum += ed_asic_inb(sc, i);
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if (sum != 0xff)
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if (sum != 0xff) {
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if (bootverbose)
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device_printf(dev, "Bad checksum %#x\n", sum);
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return (ENXIO); /* invalid DL10019C */
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}
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if (bootverbose)
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device_printf(dev, "CIR is %d\n", ed_asic_inb(sc, 0xa));
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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sc->enaddr[i] = ed_asic_inb(sc, 0x04 + i);
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ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
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@ -486,83 +487,85 @@ ed_pccard_dl100xx(device_t dev, const struct ed_product *pp)
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sc->chip_type = (id & 0x90) == 0x90 ?
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ED_CHIP_TYPE_DL10022 : ED_CHIP_TYPE_DL10019;
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sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019";
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sc->mii_readbits = ed_pccard_dl100xx_mii_readbits;
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sc->mii_writebits = ed_pccard_dl100xx_mii_writebits;
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return (0);
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}
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#ifndef ED_NO_MIIBUS
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/* MII bit-twiddling routines for cards using Dlink chipset */
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#define DL10XX_MIISET(sc, x) ed_asic_outb(sc, ED_DL10XX_MIIBUS, \
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ed_asic_inb(sc, ED_DL10XX_MIIBUS) | (x))
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#define DL10XX_MIICLR(sc, x) ed_asic_outb(sc, ED_DL10XX_MIIBUS, \
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ed_asic_inb(sc, ED_DL10XX_MIIBUS) & ~(x))
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#define DL100XX_MIISET(sc, x) ed_asic_outb(sc, ED_DL100XX_MIIBUS, \
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ed_asic_inb(sc, ED_DL100XX_MIIBUS) | (x))
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#define DL100XX_MIICLR(sc, x) ed_asic_outb(sc, ED_DL100XX_MIIBUS, \
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ed_asic_inb(sc, ED_DL100XX_MIIBUS) & ~(x))
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static void
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ed_pccard_dl10xx_mii_reset(struct ed_softc *sc)
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ed_pccard_dl100xx_mii_reset(struct ed_softc *sc)
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{
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if (sc->chip_type != ED_CHIP_TYPE_DL10022)
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return;
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ed_asic_outb(sc, ED_DL10XX_MIIBUS, ED_DL10XX_MII_RESET2);
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ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL100XX_MII_RESET2);
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DELAY(10);
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ed_asic_outb(sc, ED_DL10XX_MIIBUS,
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ED_DL10XX_MII_RESET2 | ED_DL10XX_MII_RESET1);
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ed_asic_outb(sc, ED_DL100XX_MIIBUS,
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ED_DL100XX_MII_RESET2 | ED_DL100XX_MII_RESET1);
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DELAY(10);
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ed_asic_outb(sc, ED_DL10XX_MIIBUS, ED_DL10XX_MII_RESET2);
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ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL100XX_MII_RESET2);
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DELAY(10);
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ed_asic_outb(sc, ED_DL10XX_MIIBUS,
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ED_DL10XX_MII_RESET2 | ED_DL10XX_MII_RESET1);
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ed_asic_outb(sc, ED_DL100XX_MIIBUS,
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ED_DL100XX_MII_RESET2 | ED_DL100XX_MII_RESET1);
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DELAY(10);
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ed_asic_outb(sc, ED_DL10XX_MIIBUS, 0);
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ed_asic_outb(sc, ED_DL100XX_MIIBUS, 0);
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}
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static void
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ed_pccard_dl10xx_mii_writebits(struct ed_softc *sc, u_int val, int nbits)
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ed_pccard_dl100xx_mii_writebits(struct ed_softc *sc, u_int val, int nbits)
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{
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int i;
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if (sc->chip_type == ED_CHIP_TYPE_DL10022)
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DL10XX_MIISET(sc, ED_DL10XX_MII_DIROUT_22);
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DL100XX_MIISET(sc, ED_DL100XX_MII_DIROUT_22);
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else
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DL10XX_MIISET(sc, ED_DL10XX_MII_DIROUT_19);
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DL100XX_MIISET(sc, ED_DL100XX_MII_DIROUT_19);
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for (i = nbits - 1; i >= 0; i--) {
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if ((val >> i) & 1)
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DL10XX_MIISET(sc, ED_DL10XX_MII_DATAOUT);
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DL100XX_MIISET(sc, ED_DL100XX_MII_DATAOUT);
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else
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DL10XX_MIICLR(sc, ED_DL10XX_MII_DATAOUT);
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DL100XX_MIICLR(sc, ED_DL100XX_MII_DATAOUT);
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DELAY(10);
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DL10XX_MIISET(sc, ED_DL10XX_MII_CLK);
|
||||
DL100XX_MIISET(sc, ED_DL100XX_MII_CLK);
|
||||
DELAY(10);
|
||||
DL10XX_MIICLR(sc, ED_DL10XX_MII_CLK);
|
||||
DL100XX_MIICLR(sc, ED_DL100XX_MII_CLK);
|
||||
DELAY(10);
|
||||
}
|
||||
}
|
||||
|
||||
static u_int
|
||||
ed_pccard_dl10xx_mii_readbits(struct ed_softc *sc, int nbits)
|
||||
ed_pccard_dl100xx_mii_readbits(struct ed_softc *sc, int nbits)
|
||||
{
|
||||
int i;
|
||||
u_int val = 0;
|
||||
|
||||
if (sc->chip_type == ED_CHIP_TYPE_DL10022)
|
||||
DL10XX_MIICLR(sc, ED_DL10XX_MII_DIROUT_22);
|
||||
DL100XX_MIICLR(sc, ED_DL100XX_MII_DIROUT_22);
|
||||
else
|
||||
DL10XX_MIICLR(sc, ED_DL10XX_MII_DIROUT_19);
|
||||
DL100XX_MIICLR(sc, ED_DL100XX_MII_DIROUT_19);
|
||||
|
||||
for (i = nbits - 1; i >= 0; i--) {
|
||||
DL10XX_MIISET(sc, ED_DL10XX_MII_CLK);
|
||||
DL100XX_MIISET(sc, ED_DL100XX_MII_CLK);
|
||||
DELAY(10);
|
||||
val <<= 1;
|
||||
if (ed_asic_inb(sc, ED_DL10XX_MIIBUS) & ED_DL10XX_MII_DATATIN)
|
||||
if (ed_asic_inb(sc, ED_DL100XX_MIIBUS) & ED_DL100XX_MII_DATATIN)
|
||||
val++;
|
||||
DL10XX_MIICLR(sc, ED_DL10XX_MII_CLK);
|
||||
DL100XX_MIICLR(sc, ED_DL100XX_MII_CLK);
|
||||
DELAY(10);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
static int
|
||||
ed_pccard_ax88x90_geteprom(struct ed_softc *sc)
|
||||
{
|
||||
int prom[16],i;
|
||||
@ -598,33 +601,13 @@ ed_pccard_ax88x90_geteprom(struct ed_softc *sc)
|
||||
ed_nic_outb(sc, pg_seq[i].offset, pg_seq[i].value);
|
||||
|
||||
/* Get Data */
|
||||
for (i = 0; i < 16; i++)
|
||||
for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
|
||||
prom[i] = ed_asic_inw(sc, 0);
|
||||
|
||||
/*
|
||||
* Work around a bug I've seen on Linksys EC2T cards. On
|
||||
* these cards, the node address is contained in the low order
|
||||
* bytes of the prom, with the upper byte being 0. On other
|
||||
* cards, the bytes are packed two per word. I'm unsure why
|
||||
* this is the case, and why no other open source OS has a
|
||||
* similar workaround. The Linksys EC2T card is still extremely
|
||||
* popular on E-Bay, fetching way more than any other 10Mbps
|
||||
* only card. I might be able to test to see if prom[7] and
|
||||
* prom[15] == 0x5757, since that appears to be a reliable
|
||||
* test. On the EC2T cards, I get 0x0057 in prom[14,15] instead.
|
||||
*/
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
||||
if (prom[i] & 0xff00)
|
||||
break;
|
||||
if (i == ETHER_ADDR_LEN) {
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
||||
sc->enaddr[i] = prom[i] & 0xff;
|
||||
} else {
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
|
||||
sc->enaddr[i] = prom[i / 2] & 0xff;
|
||||
sc->enaddr[i + 1] = (prom[i / 2] >> 8) & 0xff;
|
||||
}
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
|
||||
sc->enaddr[i] = prom[i / 2] & 0xff;
|
||||
sc->enaddr[i + 1] = (prom[i / 2] >> 8) & 0xff;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -633,30 +616,68 @@ ed_pccard_ax88x90_geteprom(struct ed_softc *sc)
|
||||
static int
|
||||
ed_pccard_ax88x90(device_t dev, const struct ed_product *pp)
|
||||
{
|
||||
int error;
|
||||
int iobase;
|
||||
int error, iobase, i, id;
|
||||
char *ts;
|
||||
struct ed_softc *sc = device_get_softc(dev);
|
||||
|
||||
if (!pp->flags & NE2000DVF_AX88X90)
|
||||
if (!(pp->flags & NE2000DVF_AX88X90))
|
||||
return (ENXIO);
|
||||
|
||||
/* XXX
|
||||
* Set Attribute Memory IOBASE Register. Is this a deficiency in
|
||||
* the PC Card layer, or an ax88190 specific issue? The card
|
||||
* definitely doesn't work without it.
|
||||
if (bootverbose)
|
||||
device_printf(dev, "Checking AX88x90\n");
|
||||
|
||||
/*
|
||||
* Set the IOBASE Register. The AX88x90 cards are potentially
|
||||
* multifunction cards, and thus requires a slight workaround.
|
||||
* We write the address the card is at.
|
||||
*/
|
||||
iobase = rman_get_start(sc->port_res);
|
||||
ed_pccard_memwrite(dev, ED_AX88190_IOBASE0, iobase & 0xff);
|
||||
ed_pccard_memwrite(dev, ED_AX88190_IOBASE1, (iobase >> 8) & 0xff);
|
||||
pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE0, iobase & 0xff);
|
||||
pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE1, (iobase >> 8) & 0xff);
|
||||
|
||||
#ifdef ED_NO_MIIBUS
|
||||
return (ENXIO);
|
||||
#else
|
||||
/*
|
||||
* Check to see if we have a MII PHY ID at any of the first 17
|
||||
* locations. All AX88x90 devices have MII and a PHY, so we use
|
||||
* this to weed out chips that would otherwise make it through
|
||||
* the tests we have after this point.
|
||||
*/
|
||||
sc->mii_readbits = ed_pccard_ax88x90_mii_readbits;
|
||||
sc->mii_writebits = ed_pccard_ax88x90_mii_writebits;
|
||||
for (i = 0; i < 17; i++) {
|
||||
id = ed_miibus_readreg(dev, i, MII_PHYIDR1);
|
||||
if (id != 0 && id != 0xffff)
|
||||
break;
|
||||
}
|
||||
if (i == 17) {
|
||||
sc->mii_readbits = 0;
|
||||
sc->mii_writebits = 0;
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
|
||||
ts = "AX88190";
|
||||
if (ed_asic_inb(sc, ED_ASIX_TEST) != 0) {
|
||||
ed_pccard_memwrite(dev, ED_AX88790_CSR, ED_AX88790_CSR_PWRDWN);
|
||||
/*
|
||||
* AX88790 (and I think AX88190A) chips need to be
|
||||
* powered down. There's an erratum that says we should
|
||||
* power down the PHY for 2.5s, but this seems to power
|
||||
* down the whole card. I'm unsure why this was done, but
|
||||
* appears to be required for proper operation.
|
||||
*/
|
||||
pccard_ccr_write_1(dev, PCCARD_CCR_STATUS,
|
||||
PCCARD_CCR_STATUS_PWRDWN);
|
||||
ts = "AX88790";
|
||||
}
|
||||
sc->chip_type = ED_CHIP_TYPE_AX88190;
|
||||
ed_pccard_ax88x90_geteprom(sc);
|
||||
error = ed_pccard_ax88x90_geteprom(sc);
|
||||
if (error)
|
||||
return (error);
|
||||
error = ed_probe_Novell_generic(dev, device_get_flags(dev));
|
||||
if (bootverbose)
|
||||
device_printf(dev, "probe novel returns %d\n", error);
|
||||
if (error == 0) {
|
||||
sc->vendor = ED_VENDOR_NOVELL;
|
||||
sc->type = ED_TYPE_NE2000;
|
||||
@ -664,8 +685,116 @@ ed_pccard_ax88x90(device_t dev, const struct ed_product *pp)
|
||||
sc->type_str = ts;
|
||||
}
|
||||
return (error);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef ED_NO_MIIBUS
|
||||
/* MII bit-twiddling routines for cards using Dlink chipset */
|
||||
#define AX88X90_MIISET(sc, x) ed_asic_outb(sc, ED_AX88X90_MIIBUS, \
|
||||
ed_asic_inb(sc, ED_AX88X90_MIIBUS) | (x))
|
||||
#define AX88X90_MIICLR(sc, x) ed_asic_outb(sc, ED_AX88X90_MIIBUS, \
|
||||
ed_asic_inb(sc, ED_AX88X90_MIIBUS) & ~(x))
|
||||
|
||||
static void
|
||||
ed_pccard_ax88x90_mii_reset(struct ed_softc *sc)
|
||||
{
|
||||
/* Do nothing! */
|
||||
}
|
||||
|
||||
static void
|
||||
ed_pccard_ax88x90_mii_writebits(struct ed_softc *sc, u_int val, int nbits)
|
||||
{
|
||||
int i;
|
||||
|
||||
AX88X90_MIICLR(sc, ED_AX88X90_MII_DIROUT);
|
||||
for (i = nbits - 1; i >= 0; i--) {
|
||||
if ((val >> i) & 1)
|
||||
AX88X90_MIISET(sc, ED_AX88X90_MII_DATAOUT);
|
||||
else
|
||||
AX88X90_MIICLR(sc, ED_AX88X90_MII_DATAOUT);
|
||||
DELAY(10);
|
||||
AX88X90_MIISET(sc, ED_AX88X90_MII_CLK);
|
||||
DELAY(10);
|
||||
AX88X90_MIICLR(sc, ED_AX88X90_MII_CLK);
|
||||
DELAY(10);
|
||||
}
|
||||
}
|
||||
|
||||
static u_int
|
||||
ed_pccard_ax88x90_mii_readbits(struct ed_softc *sc, int nbits)
|
||||
{
|
||||
int i;
|
||||
u_int val = 0;
|
||||
|
||||
AX88X90_MIISET(sc, ED_AX88X90_MII_DIROUT);
|
||||
for (i = nbits - 1; i >= 0; i--) {
|
||||
AX88X90_MIISET(sc, ED_AX88X90_MII_CLK);
|
||||
DELAY(10);
|
||||
val <<= 1;
|
||||
if (ed_asic_inb(sc, ED_AX88X90_MIIBUS) & ED_AX88X90_MII_DATATIN)
|
||||
val++;
|
||||
AX88X90_MIICLR(sc, ED_AX88X90_MII_CLK);
|
||||
DELAY(10);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef ED_NO_MIIBUS
|
||||
/*
|
||||
* MII bus support routines.
|
||||
*/
|
||||
static int
|
||||
ed_miibus_readreg(device_t dev, int phy, int reg)
|
||||
{
|
||||
struct ed_softc *sc;
|
||||
int failed, val;
|
||||
|
||||
/*
|
||||
* The AX88790 seem to have phy 0..f external, and 0x10 internal.
|
||||
* but they also seem to have a bogus one that shows up at phy
|
||||
* 0x11 through 0x1f.
|
||||
*/
|
||||
if (phy >= 0x11)
|
||||
return (0);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
(*sc->mii_writebits)(sc, 0xffffffff, 32);
|
||||
(*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
|
||||
(*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
|
||||
(*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
|
||||
(*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
|
||||
failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
|
||||
val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
|
||||
(*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
|
||||
return (failed ? 0 : val);
|
||||
}
|
||||
|
||||
static void
|
||||
ed_miibus_writereg(device_t dev, int phy, int reg, int data)
|
||||
{
|
||||
struct ed_softc *sc;
|
||||
|
||||
/*
|
||||
* The AX88790 seem to have phy 0..f external, and 0x10 internal.
|
||||
* but they also seem to have a bogus one that shows up at phy
|
||||
* 0x11 through 0x1f.
|
||||
*/
|
||||
if (phy >= 0x11)
|
||||
return;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
(*sc->mii_writebits)(sc, 0xffffffff, 32);
|
||||
(*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
|
||||
(*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
|
||||
(*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
|
||||
(*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
|
||||
(*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
|
||||
(*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
|
||||
(*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
|
||||
}
|
||||
#endif
|
||||
|
||||
static device_method_t ed_pccard_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, ed_pccard_probe),
|
||||
|
||||
@ -1072,25 +1072,14 @@ struct ed_ring {
|
||||
#define ED_CHIP_TYPE_DL10019 0x03
|
||||
#define ED_CHIP_TYPE_DL10022 0x04
|
||||
|
||||
/*
|
||||
* AX88190 configuration status register.
|
||||
*/
|
||||
#define ED_AX88790_CSR 0x3c2
|
||||
#define ED_AX88790_CSR_PWRDWN 0x04
|
||||
/*
|
||||
* AX88190 IOBASE registers, I'm pretty sure these don't need to be written
|
||||
* to to make the card work by ed.
|
||||
*/
|
||||
#define ED_AX88190_IOBASE0 0x3ca
|
||||
#define ED_AX88190_IOBASE1 0x3cc
|
||||
|
||||
/*
|
||||
* Test for AX88790 vs 88190 cards.
|
||||
*/
|
||||
#define ED_ASIX_TEST 0x05
|
||||
|
||||
/*
|
||||
* MII bus definitions.
|
||||
* MII bus definitions. These are common to both DL100xx and AX88x90
|
||||
* MII definitions, most likely because they are standards based.
|
||||
*/
|
||||
#define ED_MII_STARTDELIM 0x01
|
||||
#define ED_MII_WRITEOP 0x01
|
||||
@ -1108,13 +1097,21 @@ struct ed_ring {
|
||||
#define ED_MII_IDLE_BITS 1
|
||||
|
||||
/* Dlink chipset used on some Netgear and Dlink PCMCIA cards */
|
||||
#define ED_DL10XX_MIIBUS 0x0c /* MII bus register on ASIC */
|
||||
#define ED_DL100XX_MIIBUS 0x0c /* MII bus register on ASIC */
|
||||
|
||||
#define ED_DL10XX_MII_RESET1 0x04
|
||||
#define ED_DL10XX_MII_RESET2 0x08
|
||||
#define ED_DL100XX_MII_RESET1 0x04
|
||||
#define ED_DL100XX_MII_RESET2 0x08
|
||||
|
||||
#define ED_DL10XX_MII_DATATIN 0x10
|
||||
#define ED_DL10XX_MII_DIROUT_22 0x20
|
||||
#define ED_DL10XX_MII_DIROUT_19 0x10
|
||||
#define ED_DL10XX_MII_DATAOUT 0x40
|
||||
#define ED_DL10XX_MII_CLK 0x80
|
||||
#define ED_DL100XX_MII_DATATIN 0x10
|
||||
#define ED_DL100XX_MII_DIROUT_22 0x20
|
||||
#define ED_DL100XX_MII_DIROUT_19 0x10
|
||||
#define ED_DL100XX_MII_DATAOUT 0x40
|
||||
#define ED_DL100XX_MII_CLK 0x80
|
||||
|
||||
/* AX88x90 based miibus defines */
|
||||
#define ED_AX88X90_MIIBUS 0x04 /* MII bus register on ASIC */
|
||||
|
||||
#define ED_AX88X90_MII_DATAOUT 0x08
|
||||
#define ED_AX88X90_MII_DATATIN 0x04
|
||||
#define ED_AX88X90_MII_DIROUT 0x02
|
||||
#define ED_AX88X90_MII_CLK 0x01
|
||||
|
||||
@ -213,8 +213,6 @@ void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
|
||||
void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
|
||||
void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
|
||||
#ifndef ED_NO_MIIBUS
|
||||
int ed_miibus_readreg(device_t, int, int);
|
||||
void ed_miibus_writereg(device_t, int, int, int);
|
||||
int ed_ifmedia_upd(struct ifnet *);
|
||||
void ed_ifmedia_sts(struct ifnet *, struct ifmediareq *);
|
||||
void ed_child_detached(device_t, device_t);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user