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Definitions for registers and trap types found on new POWER CPUs.

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MFC after:	3 weeks
This commit is contained in:
Nathan Whitehorn 2017-11-25 22:08:40 +00:00
parent 66d6978c27
commit d225a2a9c9
2 changed files with 6 additions and 0 deletions
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5
sys/powerpc/include/spr.h
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@ -210,6 +210,11 @@
#define EPCR_DMIUH 0x00400000
#define EPCR_PMGS 0x00200000
#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */
#define SPR_LPCR 0x13e /* Logical Partitioning Control */
#define LPCR_LPES 0x008 /* Bit 60 */
#define SPR_LPID 0x13f /* Logical Partitioning Control */
#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */

1
sys/powerpc/include/trap.h
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@ -77,6 +77,7 @@
#define EXC_DSMISS 0x1200 /* Data store translation miss */
/* Power ISA 2.06+: */
#define EXC_HEA 0x0e40 /* Hypervisor Emulation Assistance */
#define EXC_VSX 0x0f40 /* VSX Unavailable */
/* The following are available on 4xx and 85xx */