Add driver for Microchip LAN78xx USB3-GigE controller
This driver supports two Microchip USB-Ethernet controllers: LAN7800 USB 3.1 to 10/100/1000 Mbps Ethernet LAN7515 USB 2 to 10/100/1000 Mbps Ethernet with built-in USB hub The LAN7515 is the Ethernet controller on the Raspberry Pi 3B+. At present there is no datasheet for the LAN7515, but it is effectively a USB 2 hub combined with a LAN7800 controller. A comprehensive LAN7800 datasheet is at http://www.microchip.com/wwwproducts/en/LAN7800. This driver is based on the structure of the smsc(4) driver which supports Microchip/SMSC's LAN95xx family. (Microchip acquired SMSC in May 2012.) The Linux lan78xx driver served as a reference for some functionality and registers. The 'muge' driver name comes from "Microchip USB Gigabit Ethernet". I made some style adjustments and minor edits to Arshan's submission. It will be connected to the build after additional review and testing. Thanks to Microchip for providing a number of Evaluation Boards (EVBs) for development and testing. Submitted by: Arshan Khanifar Reviewed by: hselasky (earlier) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D15168
This commit is contained in:
Ed Maste
parent
d96ee3e017
commit
d30c739c90
2199
sys/dev/usb/net/if_muge.c
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2199
sys/dev/usb/net/if_muge.c
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Load Diff
357
sys/dev/usb/net/if_mugereg.h
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sys/dev/usb/net/if_mugereg.h
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (C) 2018 The FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for the Microchip LAN78xx USB-to-Ethernet controllers.
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*
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* This information was mostly taken from the LAN7800 manual, but some
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* undocumented registers are based on the Linux driver.
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*
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*/
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#ifndef _IF_MUGEREG_H_
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#define _IF_MUGEREG_H_
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/* USB Vendor Requests */
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#define UVR_WRITE_REG 0xA0
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#define UVR_READ_REG 0xA1
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#define UVR_GET_STATS 0xA2
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/* Device ID and revision register */
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#define ID_REV 0x000
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#define ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL
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#define ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL
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/* Device interrupt status register. */
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#define INT_STS 0x00C
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#define INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL
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/* Hardware Configuration Register. */
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#define HW_CFG 0x010
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#define HW_CFG_LED3_EN_ (0x1UL << 23)
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#define HW_CFG_LED2_EN_ (0x1UL << 22)
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#define HW_CFG_LED1_EN_ (0x1UL << 21)
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#define HW_CFG_LEDO_EN_ (0x1UL << 20)
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#define HW_CFG_MEF_ (0x1UL << 4)
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#define HW_CFG_ETC_ (0x1UL << 3)
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#define HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */
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#define HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */
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/* Power Management Control Register. */
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#define PMT_CTL 0x014
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#define PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */
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#define PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan enable */
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#define PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY interrupt as a wake up event*/
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/* GPIO Configuration 0 Register. */
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#define GPIO_CFG0 0x018
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/* GPIO Configuration 1 Register. */
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#define GPIO_CFG1 0x01C
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/* GPIO wake enable and polarity register. */
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#define GPIO_WAKE 0x020
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/* RX Command A */
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#define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Detected */
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#define RX_CMD_A_ICSM_ (0x1UL << 14)
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#define RX_CMD_A_LEN_MASK_ 0x00003FFFUL
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/* TX Command A */
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#define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL
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#define TX_CMD_A_FCS_ (0x1UL << 22)
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/* Data Port Select Register */
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#define DP_SEL 0x024
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#define DP_SEL_DPRDY_ (0x1UL << 31)
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#define DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN and DA Hash Table */
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#define DP_SEL_RSEL_MASK_ 0x0000000F
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#define DP_SEL_VHF_HASH_LEN 16
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#define DP_SEL_VHF_VLAN_LEN 128
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/* Data Port Command Register */
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#define DP_CMD 0x028
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#define DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */
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#define DP_CMD_READ_ (0x0UL << 0) /* 0 for read */
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/* Data Port Address Register */
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#define DP_ADDR 0x02C
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/* Data Port Data Register */
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#define DP_DATA 0x030
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/* EEPROM Command Register */
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#define E2P_CMD 0x040
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#define E2P_CMD_MASK_ 0x70000000UL
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#define E2P_CMD_ADDR_MASK_ 0x000001FFUL
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#define E2P_CMD_BUSY_ (0x1UL << 31)
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#define E2P_CMD_READ_ (0x0UL << 28)
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#define E2P_CMD_WRITE_ (0x3UL << 28)
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#define E2P_CMD_ERASE_ (0x5UL << 28)
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#define E2P_CMD_RELOAD_ (0x7UL << 28)
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#define E2P_CMD_TIMEOUT_ (0x1UL << 10)
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#define E2P_MAC_OFFSET 0x01
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#define E2P_INDICATOR_OFFSET 0x00
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/* EEPROM Data Register */
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#define E2P_DATA 0x044
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#define E2P_INDICATOR 0xA5 /* Indicates an EEPROM is present */
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/* Packet sizes. */
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#define MUGE_SS_USB_PKT_SIZE 1024
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#define MUGE_HS_USB_PKT_SIZE 512
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#define MUGE_FS_USB_PKT_SIZE 64
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/* Receive Filtering Engine Control Register */
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#define RFE_CTL 0x0B0
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#define RFE_CTL_IGMP_COE_ (0x1U << 14)
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#define RFE_CTL_ICMP_COE_ (0x1U << 13)
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#define RFE_CTL_TCPUDP_COE_ (0x1U << 12)
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#define RFE_CTL_IP_COE_ (0x1U << 11)
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#define RFE_CTL_BCAST_EN_ (0x1U << 10)
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#define RFE_CTL_MCAST_EN_ (0x1U << 9)
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#define RFE_CTL_UCAST_EN_ (0x1U << 8)
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#define RFE_CTL_VLAN_FILTER_ (0x1U << 5)
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#define RFE_CTL_MCAST_HASH_ (0x1U << 3)
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#define RFE_CTL_DA_PERFECT_ (0x1U << 1)
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/* End address of the RX FIFO */
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#define FCT_RX_FIFO_END 0x0C8
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#define FCT_RX_FIFO_END_MASK_ 0x0000007FUL
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#define MUGE_MAX_RX_FIFO_SIZE (12 * 1024)
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/* End address of the TX FIFO */
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#define FCT_TX_FIFO_END 0x0CC
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#define FCT_TX_FIFO_END_MASK_ 0x0000003FUL
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#define MUGE_MAX_TX_FIFO_SIZE (12 * 1024)
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/* USB Configuration Register 0 */
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#define USB_CFG0 0x080
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#define USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty response */
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#define USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */
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/* USB Configuration Register 1 */
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#define USB_CFG1 0x084
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/* USB Configuration Register 2 */
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#define USB_CFG2 0x088
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/* USB bConfigIndex: it only has one configuration. */
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#define MUGE_CONFIG_INDEX 0
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/* Burst Cap Register */
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#define BURST_CAP 0x090
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#define MUGE_DEFAULT_BURST_CAP_SIZE MUGE_MAX_TX_FIFO_SIZE
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/* Bulk-In Delay Register */
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#define BULK_IN_DLY 0x094
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#define MUGE_DEFAULT_BULK_IN_DELAY 0x0800
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/* Interrupt Endpoint Control Register */
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#define INT_EP_CTL 0x098
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#define INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */
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/* Registers on the phy, accessed via MII/MDIO */
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#define MUGE_PHY_INTR_STAT 25
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#define MUGE_PHY_INTR_MASK 26
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#define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13)
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#define MUGE_PHY_INTR_ANEG_COMP (0x1U << 10)
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#define MUGE_EXT_PAGE_ACCESS 0x1F
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#define MUGE_EXT_PAGE_SPACE_0 0x0000
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#define MUGE_EXT_PAGE_SPACE_1 0x0001
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#define MUGE_EXT_PAGE_SPACE_2 0x0002
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/* Extended Register Page 1 Space */
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#define MUGE_EXT_MODE_CTRL 0x0013
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#define MUGE_EXT_MODE_CTRL_MDIX_MASK_ 0x000C
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#define MUGE_EXT_MODE_CTRL_AUTO_MDIX_ 0x0000
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/* FCT Flow Control Threshold Register */
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#define FCT_FLOW 0x0D0
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/* FCT RX FIFO Control Register */
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#define FCT_RX_CTL 0x0C0
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/* FCT TX FIFO Control Register */
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#define FCT_TX_CTL 0x0C4
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#define FCT_TX_CTL_EN_ (0x1U << 31)
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/* MAC Control Register */
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#define MAC_CR 0x100
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#define MAC_CR_AUTO_DUPLEX_ (0x1U << 12)
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#define MAC_CR_AUTO_SPEED_ (0x1U << 11)
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/* MAC Receive Register */
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#define MAC_RX 0x104
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#define MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000
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#define MAC_RX_MAX_FR_SIZE_SHIFT_ 16
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#define MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */
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/* MAC Transmit Register */
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#define MAC_TX 0x108
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#define MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */
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/* Flow Control Register */
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#define FLOW 0x10C
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#define FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */
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#define FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */
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/* MAC Receive Address Registers */
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#define RX_ADDRH 0x118 /* High */
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#define RX_ADDRL 0x11C /* Low */
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/* MII Access Register */
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#define MII_ACCESS 0x120
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#define MII_BUSY_ (0x1UL << 0)
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#define MII_READ_ (0x0UL << 1)
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#define MII_WRITE_ (0x1UL << 1)
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/* MII Data Register */
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#define MII_DATA 0x124
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/* MAC address perfect filter registers (ADDR_FILTx) */
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#define PFILTER_BASE 0x400
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#define PFILTER_HIX 0x00
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#define PFILTER_LOX 0x04
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#define MUGE_NUM_PFILTER_ADDRS_ 33
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#define PFILTER_ADDR_VALID_ (0x1UL << 31)
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#define PFILTER_ADDR_TYPE_SRC_ (0x1UL << 30)
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#define PFILTER_ADDR_TYPE_DST_ (0x0UL << 30)
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#define PFILTER_HI(index) (PFILTER_BASE + (8 * (index)) + (PFILTER_HIX))
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#define PFILTER_LO(index) (PFILTER_BASE + (8 * (index)) + (PFILTER_LOX))
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/*
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* These registers are not documented in the datasheet, and are based on
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* the Linux driver.
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*/
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#define OTP_BASE_ADDR 0x01000
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#define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00)
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#define OTP_PWR_DN_PWRDN_N 0x01
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#define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01)
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#define OTP_ADDR1_15_11 0x1F
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#define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02)
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#define OTP_ADDR2_10_3 0xFF
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#define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03)
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#define OTP_ADDR3_2_0 0x03
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#define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06)
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#define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08)
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#define OTP_FUNC_CMD_RESET 0x04
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#define OTP_FUNC_CMD_PROGRAM_ 0x02
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#define OTP_FUNC_CMD_READ_ 0x01
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#define OTP_MAC_OFFSET 0x01
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#define OTP_INDICATOR_OFFSET 0x00
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#define OTP_INDICATOR_1 0xF3
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#define OTP_INDICATOR_2 0xF7
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#define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A)
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#define OTP_CMD_GO_GO_ 0x01
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#define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0A)
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#define OTP_STATUS_OTP_LOCK_ 0x10
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#define OTP_STATUS_BUSY_ 0x01
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/* Some unused registers, from the data sheet. */
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#if 0
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#define BOS_ATTR 0x050
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#define SS_ATTR 0x054
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#define HS_ATTR 0x058
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#define FS_ATTR 0x05C
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#define STRNG_ATTR0 0x060
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#define STRNG_ATTR1 0x064
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#define FLAG_ATTR 0x068
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#define SW_GP_1 0x06C
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#define SW_GP_2 0x070
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#define SW_GP_3 0x074
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#define VLAN_TYPE 0x0B4
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#define RX_DP_STOR 0x0D4
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#define TX_DP_STOR 0x0D8
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#define LTM_BELT_IDLE0 0x0E0
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#define LTM_BELT_IDLE1 0x0E4
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#define LTM_BELT_ACT0 0x0E8
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#define LTM_BELT_ACT1 0x0EC
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#define LTM_INACTIVE0 0x0F0
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#define LTM_INACTIVE1 0x0F4
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#define RAND_SEED 0x110
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#define ERR_STS 0x114
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#define EEE_TX_LPI_REQUEST_DELAY_CNT 0x130
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#define EEE_TW_TX_SYS 0x134
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#define EEE_TX_LPI_AUTO_REMOVAL_DELAY 0x138
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#define WUCSR1 0x140
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#define WK_SRC 0x144
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#define WUF_CFG_BASE 0x150
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#define WUF_MASK_BASE 0x200
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#define WUCSR2 0x600
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#define NSx_IPV6_ADDR_DEST_0 0x610
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#define NSx_IPV6_ADDR_DEST_1 0x614
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#define NSx_IPV6_ADDR_DEST_2 0x618
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#define NSx_IPV6_ADDR_DEST_3 0x61C
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#define NSx_IPV6_ADDR_SRC_0 0x620
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#define NSx_IPV6_ADDR_SRC_1 0x624
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#define NSx_IPV6_ADDR_SRC_2 0x628
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#define NSx_IPV6_ADDR_SRC_3 0x62C
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#define NSx_ICMPV6_ADDR0_0 0x630
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#define NSx_ICMPV6_ADDR0_1 0x634
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#define NSx_ICMPV6_ADDR0_2 0x638
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#define NSx_ICMPV6_ADDR0_3 0x63C
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#define NSx_ICMPV6_ADDR1_0 0x640
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#define NSx_ICMPV6_ADDR1_1 0x644
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#define NSx_ICMPV6_ADDR1_2 0x648
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#define NSx_ICMPV6_ADDR1_3 0x64C
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#define NSx_IPV6_ADDR_DEST 0x650
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#define NSx_IPV6_ADDR_SRC 0x660
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#define NSx_ICMPV6_ADDR0 0x670
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#define NSx_ICMPV6_ADDR1 0x680
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#define SYN_IPV4_ADDR_SRC 0x690
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#define SYN_IPV4_ADDR_DEST 0x694
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#define SYN_IPV4_TCP_PORTS 0x698
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#define SYN_IPV6_ADDR_SRC_0 0x69C
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#define SYN_IPV6_ADDR_SRC_1 0x6A0
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#define SYN_IPV6_ADDR_SRC_2 0x6A4
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#define SYN_IPV6_ADDR_SRC_3 0x6A8
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#define SYN_IPV6_ADDR_DEST_0 0x6AC
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#define SYN_IPV6_ADDR_DEST_1 0x6B0
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#define SYN_IPV6_ADDR_DEST_2 0x6B4
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#define SYN_IPV6_ADDR_DEST_3 0x6B8
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#define SYN_IPV6_TCP_PORTS 0x6BC
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#define ARP_SPA 0x6C0
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#define ARP_TPA 0x6C4
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#define PHY_DEV_ID 0x700
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#endif
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#endif /* _IF_MUGEREG_H_ */
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13
sys/modules/usb/muge/Makefile
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13
sys/modules/usb/muge/Makefile
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@ -0,0 +1,13 @@
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# $FreeBSD$
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S= ${SRCTOP}/sys
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.PATH: $S/dev/usb/net
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KMOD= if_muge
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SRCS= opt_bus.h opt_usb.h device_if.h bus_if.h usb_if.h usbdevs.h \
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miibus_if.h miidevs.h opt_inet.h opt_platform.h ofw_bus_if.h \
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if_muge.c
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SRCS+=
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.include <bsd.kmod.mk>
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