i386 and amd64 mp_machdep: improve topology detection for Intel CPUs
This patch is significantly based on previous work by jkim. List of changes: - added comments that describe topology uniformity assumption - added reference to Intel Processor Topology Enumeration article - documented a few global variables that describe topology - retired weirdly set and used logical_cpus variable - changed fallback code for mp_ncpus > 0 case, so that CPUs are treated as being different packages rather than cores in a single package - moved AMD-specific code to topo_probe_amd [jkim] - in topo_probe_0x4() follow Intel-prescribed procedure of deriving SMT and core masks and match APIC IDs against those masks [started by jkim] - in topo_probe_0x4() drop code for double-checking topology parameters by looking at L1 cache properties [jkim] - in topo_probe_0xb() add fallback path to topo_probe_0x4() as prescribed by Intel [jkim] Still to do: - prepare for upcoming AMD CPUs by using new mechanism of uniform topology description [pointed by jkim] - probe cache topology in addition to CPU topology and probably use that for scheduler affinity topology; e.g. Core2 Duo and Athlon II X2 have the same CPU topology, but Athlon cores do not share L2 cache while Core2's do (no L3 cache in both cases) - think of supporting non-uniform topologies if they are ever implemented for platforms in question - think how to better described old HTT vs new HTT distinction, HTT vs SMT can be confusing as SMT is a generic term - more robust code for marking CPUs as "logical" and/or "hyperthreaded", use HTT mask instead of modulo operation - correct support for halting logical and/or hyperthreaded CPUs, let scheduler know that it shouldn't schedule any threads on those CPUs PR: kern/145385 (related) In collaboration with: jkim Tested by: Sergey Kandaurov <pluknet@gmail.com>, Jeremy Chadwick <freebsd@jdc.parodius.com>, Chip Camden <sterling@camdensoftware.com>, Steve Wills <steve@mouf.net>, Olivier Smedts <olivier@gid0.org>, Florian Smeets <flo@smeets.im> MFC after: 1 month
This commit is contained in:
Andriy Gapon
parent
08a9c20500
commit
d443a96ffb
@ -126,7 +126,6 @@ extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
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* Local data and functions.
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*/
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static u_int logical_cpus;
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static volatile cpumask_t ipi_nmi_pending;
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/* used to hold the AP's until we are ready to release them */
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@ -152,8 +151,8 @@ int apic_cpuids[MAX_APIC_ID + 1];
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static volatile u_int cpu_ipi_pending[MAXCPU];
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static u_int boot_address;
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static int cpu_logical;
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static int cpu_cores;
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static int cpu_logical; /* logical cpus per core */
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static int cpu_cores; /* cores per package */
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static void assign_cpu_ids(void);
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static void set_interrupt_apic_ids(void);
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@ -162,7 +161,7 @@ static int start_ap(int apic_id);
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static void release_aps(void *dummy);
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static int hlt_logical_cpus;
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static u_int hyperthreading_cpus;
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static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
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static cpumask_t hyperthreading_cpus_mask;
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static int hyperthreading_allowed = 1;
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static struct sysctl_ctx_list logical_cpu_clist;
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@ -175,25 +174,106 @@ mem_range_AP_init(void)
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mem_range_softc.mr_op->initAP(&mem_range_softc);
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}
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static void
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topo_probe_amd(void)
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{
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/* AMD processors do not support HTT. */
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cpu_cores = (amd_feature2 & AMDID2_CMP) != 0 ?
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(cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
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cpu_logical = 1;
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}
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/*
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* Round up to the next power of two, if necessary, and then
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* take log2.
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* Returns -1 if argument is zero.
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*/
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static __inline int
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mask_width(u_int x)
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{
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return (fls(x << (1 - powerof2(x))) - 1);
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}
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static void
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topo_probe_0x4(void)
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{
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u_int p[4];
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int pkg_id_bits;
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int core_id_bits;
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int max_cores;
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int max_logical;
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int id;
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/* Both zero and one here mean one logical processor per package. */
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max_logical = (cpu_feature & CPUID_HTT) != 0 ?
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(cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
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if (max_logical <= 1)
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return;
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/*
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* Because of uniformity assumption we examine only
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* those logical processors that belong to the same
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* package as BSP. Further, we count number of
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* logical processors that belong to the same core
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* as BSP thus deducing number of threads per core.
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*/
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cpuid_count(0x04, 0, p);
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max_cores = ((p[0] >> 26) & 0x3f) + 1;
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core_id_bits = mask_width(max_logical/max_cores);
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if (core_id_bits < 0)
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return;
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pkg_id_bits = core_id_bits + mask_width(max_cores);
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for (id = 0; id <= MAX_APIC_ID; id++) {
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/* Check logical CPU availability. */
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if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
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continue;
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/* Check if logical CPU has the same package ID. */
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if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
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continue;
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cpu_cores++;
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/* Check if logical CPU has the same package and core IDs. */
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if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
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cpu_logical++;
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}
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cpu_cores /= cpu_logical;
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hyperthreading_cpus = cpu_logical;
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}
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static void
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topo_probe_0xb(void)
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{
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int logical;
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int p[4];
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u_int p[4];
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int bits;
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int type;
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int cnt;
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int i;
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int logical;
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int type;
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int x;
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/* We only support two levels for now. */
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/* We only support three levels for now. */
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for (i = 0; i < 3; i++) {
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cpuid_count(0x0B, i, p);
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cpuid_count(0x0b, i, p);
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/* Fall back if CPU leaf 11 doesn't really exist. */
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if (i == 0 && p[1] == 0) {
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topo_probe_0x4();
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return;
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}
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bits = p[0] & 0x1f;
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logical = p[1] &= 0xffff;
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type = (p[2] >> 8) & 0xff;
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if (type == 0 || logical == 0)
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break;
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/*
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* Because of uniformity assumption we examine only
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* those logical processors that belong to the same
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* package as BSP.
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*/
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for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
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if (!cpu_info[x].cpu_present ||
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cpu_info[x].cpu_disabled)
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@ -211,76 +291,16 @@ topo_probe_0xb(void)
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cpu_cores /= cpu_logical;
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}
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static void
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topo_probe_0x4(void)
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{
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u_int threads_per_cache, p[4];
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u_int htt, cmp;
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int i;
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htt = cmp = 1;
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/*
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* If this CPU supports HTT or CMP then mention the
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* number of physical/logical cores it contains.
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*/
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if (cpu_feature & CPUID_HTT)
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htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
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if (cpu_vendor_id == CPU_VENDOR_AMD && (amd_feature2 & AMDID2_CMP))
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cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
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else if (cpu_vendor_id == CPU_VENDOR_INTEL && (cpu_high >= 4)) {
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cpuid_count(4, 0, p);
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if ((p[0] & 0x1f) != 0)
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cmp = ((p[0] >> 26) & 0x3f) + 1;
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}
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cpu_cores = cmp;
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cpu_logical = htt / cmp;
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/* Setup the initial logical CPUs info. */
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if (cpu_feature & CPUID_HTT)
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logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
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/*
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* Work out if hyperthreading is *really* enabled. This
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* is made really ugly by the fact that processors lie: Dual
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* core processors claim to be hyperthreaded even when they're
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* not, presumably because they want to be treated the same
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* way as HTT with respect to per-cpu software licensing.
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* At the time of writing (May 12, 2005) the only hyperthreaded
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* cpus are from Intel, and Intel's dual-core processors can be
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* identified via the "deterministic cache parameters" cpuid
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* calls.
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*/
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/*
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* First determine if this is an Intel processor which claims
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* to have hyperthreading support.
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*/
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if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
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/*
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* If the "deterministic cache parameters" cpuid calls
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* are available, use them.
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*/
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if (cpu_high >= 4) {
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/* Ask the processor about the L1 cache. */
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for (i = 0; i < 1; i++) {
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cpuid_count(4, i, p);
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threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
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if (hyperthreading_cpus < threads_per_cache)
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hyperthreading_cpus = threads_per_cache;
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if ((p[0] & 0x1f) == 0)
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break;
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}
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}
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/*
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* If the deterministic cache parameters are not
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* available, or if no caches were reported to exist,
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* just accept what the HTT flag indicated.
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*/
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if (hyperthreading_cpus == 0)
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hyperthreading_cpus = logical_cpus;
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}
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}
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/*
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* Both topology discovery code and code that consumes topology
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* information assume top-down uniformity of the topology.
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* That is, all physical packages must be identical and each
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* core in a package must have the same number of threads.
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* Topology information is queried only on BSP, on which this
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* code runs and for which it can query CPUID information.
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* Then topology is extrapolated on all packages using the
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* uniformity assumption.
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*/
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static void
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topo_probe(void)
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{
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@ -289,13 +309,31 @@ topo_probe(void)
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if (cpu_topo_probed)
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return;
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logical_cpus = logical_cpus_mask = 0;
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if (cpu_high >= 0xb)
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topo_probe_0xb();
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else if (cpu_high)
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topo_probe_0x4();
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logical_cpus_mask = 0;
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if (cpu_vendor_id == CPU_VENDOR_AMD)
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topo_probe_amd();
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else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
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/*
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* See Intel(R) 64 Architecture Processor
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* Topology Enumeration article for details.
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*
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* Note that 0x1 <= cpu_high < 4 case should be
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* compatible with topo_probe_0x4() logic when
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* CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
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* or it should trigger the fallback otherwise.
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*/
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if (cpu_high >= 0xb)
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topo_probe_0xb();
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else if (cpu_high >= 0x1)
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topo_probe_0x4();
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}
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/*
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* Fallback: assume each logical CPU is in separate
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* physical package. That is, no multi-core, no SMT.
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*/
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if (cpu_cores == 0)
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cpu_cores = mp_ncpus > 0 ? mp_ncpus : 1;
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cpu_cores = 1;
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if (cpu_logical == 0)
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cpu_logical = 1;
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cpu_topo_probed = 1;
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@ -675,7 +713,8 @@ init_secondary(void)
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printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
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/* Determine if we are a logical CPU. */
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if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
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/* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
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if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
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logical_cpus_mask |= PCPU_GET(cpumask);
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/* Determine if we are a hyperthread. */
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@ -173,7 +173,6 @@ static u_long *ipi_hardclock_counts[MAXCPU];
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* Local data and functions.
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*/
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static u_int logical_cpus;
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static volatile cpumask_t ipi_nmi_pending;
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/* used to hold the AP's until we are ready to release them */
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@ -199,8 +198,8 @@ int apic_cpuids[MAX_APIC_ID + 1];
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static volatile u_int cpu_ipi_pending[MAXCPU];
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static u_int boot_address;
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static int cpu_logical;
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static int cpu_cores;
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static int cpu_logical; /* logical cpus per core */
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static int cpu_cores; /* cores per package */
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static void assign_cpu_ids(void);
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static void install_ap_tramp(void);
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@ -210,7 +209,7 @@ static int start_ap(int apic_id);
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static void release_aps(void *dummy);
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static int hlt_logical_cpus;
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static u_int hyperthreading_cpus;
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static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
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static cpumask_t hyperthreading_cpus_mask;
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static int hyperthreading_allowed = 1;
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static struct sysctl_ctx_list logical_cpu_clist;
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@ -222,25 +221,106 @@ mem_range_AP_init(void)
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mem_range_softc.mr_op->initAP(&mem_range_softc);
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}
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static void
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topo_probe_amd(void)
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{
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/* AMD processors do not support HTT. */
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cpu_cores = (amd_feature2 & AMDID2_CMP) != 0 ?
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(cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
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cpu_logical = 1;
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}
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/*
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* Round up to the next power of two, if necessary, and then
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* take log2.
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* Returns -1 if argument is zero.
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*/
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static __inline int
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mask_width(u_int x)
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{
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return (fls(x << (1 - powerof2(x))) - 1);
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}
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static void
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topo_probe_0x4(void)
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{
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u_int p[4];
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int pkg_id_bits;
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int core_id_bits;
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int max_cores;
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int max_logical;
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int id;
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/* Both zero and one here mean one logical processor per package. */
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max_logical = (cpu_feature & CPUID_HTT) != 0 ?
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(cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
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if (max_logical <= 1)
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return;
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/*
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* Because of uniformity assumption we examine only
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* those logical processors that belong to the same
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* package as BSP. Further, we count number of
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* logical processors that belong to the same core
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* as BSP thus deducing number of threads per core.
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*/
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cpuid_count(0x04, 0, p);
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max_cores = ((p[0] >> 26) & 0x3f) + 1;
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core_id_bits = mask_width(max_logical/max_cores);
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if (core_id_bits < 0)
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return;
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pkg_id_bits = core_id_bits + mask_width(max_cores);
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for (id = 0; id <= MAX_APIC_ID; id++) {
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/* Check logical CPU availability. */
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if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
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continue;
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/* Check if logical CPU has the same package ID. */
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if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
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continue;
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cpu_cores++;
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/* Check if logical CPU has the same package and core IDs. */
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if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
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cpu_logical++;
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}
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cpu_cores /= cpu_logical;
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hyperthreading_cpus = cpu_logical;
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}
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static void
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topo_probe_0xb(void)
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{
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int logical;
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int p[4];
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u_int p[4];
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int bits;
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int type;
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int cnt;
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int i;
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int logical;
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int type;
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int x;
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/* We only support two levels for now. */
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/* We only support three levels for now. */
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for (i = 0; i < 3; i++) {
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cpuid_count(0x0B, i, p);
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cpuid_count(0x0b, i, p);
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/* Fall back if CPU leaf 11 doesn't really exist. */
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if (i == 0 && p[1] == 0) {
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topo_probe_0x4();
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return;
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}
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bits = p[0] & 0x1f;
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logical = p[1] &= 0xffff;
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type = (p[2] >> 8) & 0xff;
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if (type == 0 || logical == 0)
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break;
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/*
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* Because of uniformity assumption we examine only
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* those logical processors that belong to the same
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* package as BSP.
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*/
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for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
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if (!cpu_info[x].cpu_present ||
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cpu_info[x].cpu_disabled)
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@ -258,76 +338,16 @@ topo_probe_0xb(void)
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cpu_cores /= cpu_logical;
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}
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static void
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topo_probe_0x4(void)
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{
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u_int threads_per_cache, p[4];
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u_int htt, cmp;
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int i;
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htt = cmp = 1;
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/*
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* If this CPU supports HTT or CMP then mention the
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* number of physical/logical cores it contains.
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*/
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if (cpu_feature & CPUID_HTT)
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htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
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if (cpu_vendor_id == CPU_VENDOR_AMD && (amd_feature2 & AMDID2_CMP))
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cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
|
||||
else if (cpu_vendor_id == CPU_VENDOR_INTEL && (cpu_high >= 4)) {
|
||||
cpuid_count(4, 0, p);
|
||||
if ((p[0] & 0x1f) != 0)
|
||||
cmp = ((p[0] >> 26) & 0x3f) + 1;
|
||||
}
|
||||
cpu_cores = cmp;
|
||||
cpu_logical = htt / cmp;
|
||||
|
||||
/* Setup the initial logical CPUs info. */
|
||||
if (cpu_feature & CPUID_HTT)
|
||||
logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
|
||||
|
||||
/*
|
||||
* Work out if hyperthreading is *really* enabled. This
|
||||
* is made really ugly by the fact that processors lie: Dual
|
||||
* core processors claim to be hyperthreaded even when they're
|
||||
* not, presumably because they want to be treated the same
|
||||
* way as HTT with respect to per-cpu software licensing.
|
||||
* At the time of writing (May 12, 2005) the only hyperthreaded
|
||||
* cpus are from Intel, and Intel's dual-core processors can be
|
||||
* identified via the "deterministic cache parameters" cpuid
|
||||
* calls.
|
||||
*/
|
||||
/*
|
||||
* First determine if this is an Intel processor which claims
|
||||
* to have hyperthreading support.
|
||||
*/
|
||||
if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
|
||||
/*
|
||||
* If the "deterministic cache parameters" cpuid calls
|
||||
* are available, use them.
|
||||
*/
|
||||
if (cpu_high >= 4) {
|
||||
/* Ask the processor about the L1 cache. */
|
||||
for (i = 0; i < 1; i++) {
|
||||
cpuid_count(4, i, p);
|
||||
threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
|
||||
if (hyperthreading_cpus < threads_per_cache)
|
||||
hyperthreading_cpus = threads_per_cache;
|
||||
if ((p[0] & 0x1f) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If the deterministic cache parameters are not
|
||||
* available, or if no caches were reported to exist,
|
||||
* just accept what the HTT flag indicated.
|
||||
*/
|
||||
if (hyperthreading_cpus == 0)
|
||||
hyperthreading_cpus = logical_cpus;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Both topology discovery code and code that consumes topology
|
||||
* information assume top-down uniformity of the topology.
|
||||
* That is, all physical packages must be identical and each
|
||||
* core in a package must have the same number of threads.
|
||||
* Topology information is queried only on BSP, on which this
|
||||
* code runs and for which it can query CPUID information.
|
||||
* Then topology is extrapolated on all packages using the
|
||||
* uniformity assumption.
|
||||
*/
|
||||
static void
|
||||
topo_probe(void)
|
||||
{
|
||||
@ -336,13 +356,31 @@ topo_probe(void)
|
||||
if (cpu_topo_probed)
|
||||
return;
|
||||
|
||||
logical_cpus = logical_cpus_mask = 0;
|
||||
if (cpu_high >= 0xb)
|
||||
topo_probe_0xb();
|
||||
else if (cpu_high)
|
||||
topo_probe_0x4();
|
||||
logical_cpus_mask = 0;
|
||||
if (cpu_vendor_id == CPU_VENDOR_AMD)
|
||||
topo_probe_amd();
|
||||
else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
|
||||
/*
|
||||
* See Intel(R) 64 Architecture Processor
|
||||
* Topology Enumeration article for details.
|
||||
*
|
||||
* Note that 0x1 <= cpu_high < 4 case should be
|
||||
* compatible with topo_probe_0x4() logic when
|
||||
* CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
|
||||
* or it should trigger the fallback otherwise.
|
||||
*/
|
||||
if (cpu_high >= 0xb)
|
||||
topo_probe_0xb();
|
||||
else if (cpu_high >= 0x1)
|
||||
topo_probe_0x4();
|
||||
}
|
||||
|
||||
/*
|
||||
* Fallback: assume each logical CPU is in separate
|
||||
* physical package. That is, no multi-core, no SMT.
|
||||
*/
|
||||
if (cpu_cores == 0)
|
||||
cpu_cores = mp_ncpus > 0 ? mp_ncpus : 1;
|
||||
cpu_cores = 1;
|
||||
if (cpu_logical == 0)
|
||||
cpu_logical = 1;
|
||||
cpu_topo_probed = 1;
|
||||
@ -706,7 +744,8 @@ init_secondary(void)
|
||||
printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
|
||||
|
||||
/* Determine if we are a logical CPU. */
|
||||
if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
|
||||
/* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
|
||||
if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
|
||||
logical_cpus_mask |= PCPU_GET(cpumask);
|
||||
|
||||
/* Determine if we are a hyperthread. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user