Fixes for the D-Link DFE-580 card.
This is pretty much fixes any issue I can find:
- Watchdog timeouts were due to starting the TX DMA engine
before we had a packet ready for it. So the first packet
sent never got out only if we sent more then one packet
at a time did the others make it out and not blow up.
Of course reseting the chip then caused us not to transmit
the first packet again ie. catch-22. This required logic changes.
- Combine interrupts on TX packets being queued up.
- Don't keep running around the RX ring since we might get
out of sync so only go around once per receive
- Let the RX engine recover via the poll interface which is
similar to the TX interface. This way the chip wakes
up with no effort when we read enough packets.
- Do better hand-shaking on RX & TX packets so they don't
start of to soon.
- Force a duplex setting when the link comes up after
an ste_init or it will default to half-duplex and be
really slow. This only happens on subsequent ste_init.
The first one worked.
- Don't call stat_update for every overflow. We only monitor
the collisions so the tick interval is good enough for that.
Just read in the collision stats to minimize bus reads.
- Don't read the miibus every tick since it uses delays and
delays are not good for performance.
- Tie link events directly to the miibus code so the port
gets set correctly if someone changes the port settings.
- Reduce the extreme number of {R,T}FD's. They would consume
130K of kernel memory for each NIC.
- Set the TX_THRESH to wait for the DMA engine to complete
before running the TX FIFO. This hurts peak TX performance
but under bi-directional load the DMA engine can't keep up
with the FIFO. Testing shows that we end up in the case
anyways (a la dc(4) issues but worse since the RX engine hogs
everything).
- When stopping the card do a reset since the reset verifies the
card has stopped. Otherwise on heavy RX load the RX DMA engine
is still stuffing packets into memory. If that happens after
we free the DMA area memory bits get scribled in memory and
bad things happen.
This card still has seemingly unfixable issues under heavy RX load in
which the card takes over the PCI bus.
Sponsored by: Vernier Networks
MFC after: 1 week
This commit is contained in:
Doug Ambrisko
parent
130be1f120
commit
d44ef39e51
172
sys/pci/if_ste.c
172
sys/pci/if_ste.c
@ -45,6 +45,7 @@
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_vlan_var.h>
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#include <net/bpf.h>
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@ -643,6 +644,10 @@ static void ste_intr(xsc)
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ste_stats_update(sc);
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}
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if (status & STE_ISR_LINKEVENT)
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mii_pollstat(device_get_softc(sc->ste_miibus));
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if (status & STE_ISR_HOSTERR) {
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ste_reset(sc);
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ste_init(sc);
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@ -671,14 +676,17 @@ static void ste_rxeof(sc)
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struct mbuf *m;
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struct ifnet *ifp;
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struct ste_chain_onefrag *cur_rx;
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int total_len = 0;
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int total_len = 0, count=0;
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u_int32_t rxstat;
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ifp = &sc->arpcom.ac_if;
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again:
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while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
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& STE_RXSTAT_DMADONE) {
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if ((STE_RX_LIST_CNT - count) < 3) {
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break;
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}
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while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) {
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cur_rx = sc->ste_cdata.ste_rx_head;
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sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
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@ -732,29 +740,9 @@ static void ste_rxeof(sc)
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/* Remove header from mbuf and pass it on. */
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m_adj(m, sizeof(struct ether_header));
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ether_input(ifp, eh, m);
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}
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/*
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* Handle the 'end of channel' condition. When the upload
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* engine hits the end of the RX ring, it will stall. This
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* is our cue to flush the RX ring, reload the uplist pointer
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* register and unstall the engine.
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* XXX This is actually a little goofy. With the ThunderLAN
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* chip, you get an interrupt when the receiver hits the end
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* of the receive ring, which tells you exactly when you
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* you need to reload the ring pointer. Here we have to
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* fake it. I'm mad at myself for not being clever enough
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* to avoid the use of a goto here.
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*/
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if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 ||
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CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) {
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
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ste_wait(sc);
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CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
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vtophys(&sc->ste_ldata->ste_rx_list[0]));
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sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0];
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
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goto again;
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cur_rx->ste_ptr->ste_status = 0;
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count++;
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}
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return;
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@ -838,11 +826,8 @@ static void ste_stats_update(xsc)
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void *xsc;
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{
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struct ste_softc *sc;
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struct ste_stats stats;
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struct ifnet *ifp;
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struct mii_data *mii;
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int i;
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u_int8_t *p;
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sc = xsc;
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STE_LOCK(sc);
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@ -850,22 +835,23 @@ static void ste_stats_update(xsc)
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ifp = &sc->arpcom.ac_if;
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mii = device_get_softc(sc->ste_miibus);
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p = (u_int8_t *)&stats;
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ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
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+ CSR_READ_1(sc, STE_MULTI_COLLS)
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+ CSR_READ_1(sc, STE_SINGLE_COLLS);
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for (i = 0; i < sizeof(stats); i++) {
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*p = CSR_READ_1(sc, STE_STATS + i);
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p++;
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}
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ifp->if_collisions += stats.ste_single_colls +
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stats.ste_multi_colls + stats.ste_late_colls;
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mii_tick(mii);
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if (!sc->ste_link && mii->mii_media_status & IFM_ACTIVE &&
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
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sc->ste_link++;
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if (ifp->if_snd.ifq_head != NULL)
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ste_start(ifp);
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if (!sc->ste_link) {
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mii_pollstat(mii);
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if (mii->mii_media_status & IFM_ACTIVE &&
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
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sc->ste_link++;
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/*
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* we don't get a call-back on re-init so do it
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* otherwise we get stuck in the wrong link state
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*/
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ste_miibus_statchg(sc->ste_dev);
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if (ifp->if_snd.ifq_head != NULL)
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ste_start(ifp);
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}
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}
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sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
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@ -913,6 +899,7 @@ static int ste_attach(dev)
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sc = device_get_softc(dev);
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unit = device_get_unit(dev);
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bzero(sc, sizeof(struct ste_softc));
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sc->ste_dev = dev;
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mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
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MTX_DEF | MTX_RECURSE);
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@ -1065,10 +1052,18 @@ static int ste_attach(dev)
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ifp->if_baudrate = 10000000;
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ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
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sc->ste_tx_thresh = STE_TXSTART_THRESH;
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/*
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* Call MI attach routine.
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*/
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ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
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/*
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* Tell the upper layer(s) we support long frames.
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*/
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ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
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STE_UNLOCK(sc);
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return(0);
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@ -1134,7 +1129,7 @@ static int ste_newbuf(sc, c, m)
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c->ste_mbuf = m_new;
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c->ste_ptr->ste_status = 0;
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c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
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c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST;
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c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
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return(0);
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}
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@ -1164,7 +1159,7 @@ static int ste_init_rx_list(sc)
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ld->ste_rx_list[i].ste_next =
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vtophys(&ld->ste_rx_list[i + 1]);
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}
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ld->ste_rx_list[i].ste_status = 0;
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}
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cd->ste_rx_head = &cd->ste_rx_chain[0];
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@ -1183,6 +1178,8 @@ static void ste_init_tx_list(sc)
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ld = sc->ste_ldata;
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for (i = 0; i < STE_TX_LIST_CNT; i++) {
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cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
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cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
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cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
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cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
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if (i == (STE_TX_LIST_CNT - 1))
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cd->ste_tx_chain[i].ste_next =
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@ -1198,10 +1195,6 @@ static void ste_init_tx_list(sc)
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&cd->ste_tx_chain[i - 1];
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}
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bzero((char *)ld->ste_tx_list,
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sizeof(struct ste_desc) * STE_TX_LIST_CNT);
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cd->ste_tx_prod = 0;
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cd->ste_tx_cons = 0;
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cd->ste_tx_cnt = 0;
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@ -1238,6 +1231,9 @@ static void ste_init(xsc)
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return;
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}
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/* Set RX polling interval */
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CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
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/* Init TX descriptors */
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ste_init_tx_list(sc);
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@ -1277,20 +1273,21 @@ static void ste_init(xsc)
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
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/* Set TX polling interval */
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CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
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/* Set TX polling interval (defer until we TX first packet */
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CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
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/* Load address of the TX list */
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
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ste_wait(sc);
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CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
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vtophys(&sc->ste_ldata->ste_tx_list[0]));
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CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
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ste_wait(sc);
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sc->ste_tx_prev_idx=-1;
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/* Enable receiver and transmitter */
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CSR_WRITE_2(sc, STE_MACCTL0, 0);
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CSR_WRITE_2(sc, STE_MACCTL1, 0);
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STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
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STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
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@ -1301,6 +1298,9 @@ static void ste_init(xsc)
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CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
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CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
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/* Accept VLAN length packets */
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CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
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ste_ifmedia_upd(ifp);
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ifp->if_flags |= IFF_RUNNING;
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@ -1330,6 +1330,11 @@ static void ste_stop(sc)
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STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
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STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
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ste_wait(sc);
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/*
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* Try really hard to stop the RX engine or under heavy RX
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* data chip will write into de-allocated memory.
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*/
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ste_reset(sc);
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sc->ste_link = 0;
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@ -1347,6 +1352,8 @@ static void ste_stop(sc)
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}
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}
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bzero(sc->ste_ldata, sizeof(struct ste_list_data));
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ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
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STE_UNLOCK(sc);
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@ -1410,8 +1417,10 @@ static int ste_ioctl(ifp, command, data)
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sc->ste_if_flags & IFF_PROMISC) {
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STE_CLRBIT1(sc, STE_RX_MODE,
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STE_RXMODE_PROMISC);
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} else if (!(ifp->if_flags & IFF_RUNNING)) {
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sc->ste_tx_thresh = STE_MIN_FRAMELEN;
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}
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if (!(ifp->if_flags & IFF_RUNNING)) {
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sc->ste_tx_thresh = STE_MIN_FRAMELEN * 2;
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sc->ste_tx_thresh = STE_TXSTART_THRESH;
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ste_init(sc);
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}
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} else {
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@ -1454,14 +1463,13 @@ static int ste_encap(sc, c, m_head)
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d = c->ste_ptr;
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d->ste_ctl = 0;
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d->ste_next = 0;
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for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
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if (m->m_len != 0) {
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if (frag == STE_MAXFRAGS)
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break;
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total_len += m->m_len;
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f = &c->ste_ptr->ste_frags[frag];
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f = &d->ste_frags[frag];
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f->ste_addr = vtophys(mtod(m, vm_offset_t));
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f->ste_len = m->m_len;
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frag++;
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@ -1469,8 +1477,8 @@ static int ste_encap(sc, c, m_head)
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}
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c->ste_mbuf = m_head;
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c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
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c->ste_ptr->ste_ctl = total_len;
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d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
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d->ste_ctl = 1;
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return(0);
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}
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@ -1480,7 +1488,7 @@ static void ste_start(ifp)
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{
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struct ste_softc *sc;
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struct mbuf *m_head = NULL;
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struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx;
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struct ste_chain *cur_tx = NULL;
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int idx;
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sc = ifp->if_softc;
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@ -1497,7 +1505,6 @@ static void ste_start(ifp)
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}
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idx = sc->ste_cdata.ste_tx_prod;
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start_tx = &sc->ste_cdata.ste_tx_chain[idx];
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while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
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@ -1514,9 +1521,32 @@ static void ste_start(ifp)
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ste_encap(sc, cur_tx, m_head);
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if (prev != NULL)
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prev->ste_ptr->ste_next = cur_tx->ste_phys;
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prev = cur_tx;
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cur_tx->ste_ptr->ste_next = 0;
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if(sc->ste_tx_prev_idx < 0){
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cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
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/* Load address of the TX list */
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
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ste_wait(sc);
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CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
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vtophys(&sc->ste_ldata->ste_tx_list[0]));
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/* Set TX polling interval to start TX engine */
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CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
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STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
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ste_wait(sc);
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}else{
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cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
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sc->ste_cdata.ste_tx_chain[
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sc->ste_tx_prev_idx].ste_ptr->ste_next
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= cur_tx->ste_phys;
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}
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sc->ste_tx_prev_idx=idx;
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/*
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* If there's a BPF listener, bounce a copy of this frame
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@ -1527,20 +1557,10 @@ static void ste_start(ifp)
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STE_INC(idx, STE_TX_LIST_CNT);
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sc->ste_cdata.ste_tx_cnt++;
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ifp->if_timer = 5;
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sc->ste_cdata.ste_tx_prod = idx;
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}
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if (cur_tx == NULL) {
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STE_UNLOCK(sc);
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return;
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}
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cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR;
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/* Start transmission */
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sc->ste_cdata.ste_tx_prod = idx;
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start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys;
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ifp->if_timer = 5;
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STE_UNLOCK(sc);
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return;
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@ -93,6 +93,10 @@
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#define STE_MAR3 0x66
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#define STE_STATS 0x68
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#define STE_LATE_COLLS 0x75
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#define STE_MULTI_COLLS 0x76
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#define STE_SINGLE_COLLS 0x77
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#define STE_DMACTL_RXDMA_STOPPED 0x00000001
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#define STE_DMACTL_TXDMA_CMPREQ 0x00000002
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#define STE_DMACTL_TXDMA_STOPPED 0x00000004
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@ -224,13 +228,13 @@
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* The number of bytes that must in present in the TX FIFO before
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* transmission begins. Value should be in increments of 4 bytes.
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*/
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#define STE_TXSTART_THRESH 0x1FFF
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#define STE_TXSTART_THRESH 0x1FFC
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/*
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||||
* Number of bytes that must be present in the RX FIFO before
|
||||
* an RX EARLY interrupt is generated.
|
||||
*/
|
||||
#define STE_RXEARLY_THRESH 0x1FFF
|
||||
#define STE_RXEARLY_THRESH 0x1FFC
|
||||
|
||||
#define STE_WAKEEVENT_WAKEPKT_ENB 0x01
|
||||
#define STE_WAKEEVENT_MAGICPKT_ENB 0x02
|
||||
@ -272,8 +276,9 @@
|
||||
#define STE_IMR_RX_DMADONE 0x0400
|
||||
|
||||
#define STE_INTRS \
|
||||
(STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE|STE_IMR_STATS_OFLOW| \
|
||||
STE_IMR_TX_DONE|STE_IMR_HOSTERR|STE_IMR_RX_EARLY)
|
||||
(STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
|
||||
STE_IMR_TX_DONE|STE_IMR_HOSTERR| \
|
||||
STE_IMR_LINKEVENT)
|
||||
|
||||
#define STE_ISR_INTLATCH 0x0001
|
||||
#define STE_ISR_HOSTERR 0x0002
|
||||
@ -406,7 +411,7 @@ struct ste_frag {
|
||||
#define STE_FRAG_LAST 0x80000000
|
||||
#define STE_FRAG_LEN 0x00001FFF
|
||||
|
||||
#define STE_MAXFRAGS 63
|
||||
#define STE_MAXFRAGS 8
|
||||
|
||||
struct ste_desc {
|
||||
u_int32_t ste_next;
|
||||
@ -460,9 +465,10 @@ struct ste_desc_onefrag {
|
||||
#define STE_MIN_FRAMELEN 60
|
||||
#define STE_PACKET_SIZE 1536
|
||||
#define ETHER_ALIGN 2
|
||||
#define STE_RX_LIST_CNT 128
|
||||
#define STE_TX_LIST_CNT 256
|
||||
#define STE_RX_LIST_CNT 64
|
||||
#define STE_TX_LIST_CNT 64
|
||||
#define STE_INC(x, y) (x) = (x + 1) % y
|
||||
#define STE_NEXT(x, y) (x + 1) % y
|
||||
|
||||
struct ste_type {
|
||||
u_int16_t ste_vid;
|
||||
@ -509,10 +515,12 @@ struct ste_softc {
|
||||
void *ste_intrhand;
|
||||
struct ste_type *ste_info;
|
||||
device_t ste_miibus;
|
||||
device_t ste_dev;
|
||||
int ste_unit;
|
||||
int ste_tx_thresh;
|
||||
u_int8_t ste_link;
|
||||
int ste_if_flags;
|
||||
int ste_tx_prev_idx;
|
||||
struct ste_list_data *ste_ldata;
|
||||
struct ste_chain_data ste_cdata;
|
||||
struct callout_handle ste_stat_ch;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user