Add support for RTL8153B, RTL8156 and RTL8156B to if_ure(4).
Submitted by: fbbz@synack.eu PR: 253374 MFC after: 1 week Sponsored by: Mellanox Technologies // NVIDIA Networking
This commit is contained in:
Hans Petter Selasky
parent
73570795e7
commit
d4cf41a99b
File diff suppressed because it is too large
Load Diff
@ -26,6 +26,9 @@
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* $FreeBSD$
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*/
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#ifndef _IF_UREREG_H_
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#define _IF_UREREG_H_
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#define URE_CONFIG_IDX 0 /* config number 1 */
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#define URE_IFACE_IDX 0
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@ -40,7 +43,10 @@
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#define URE_BYTE_EN_BYTE 0x11
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#define URE_BYTE_EN_SIX_BYTES 0x3f
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#define URE_FRAMELEN(mtu) ((mtu) + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN)
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#define URE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
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#define URE_JUMBO_FRAMELEN (9*1024)
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#define URE_JUMBO_MTU (URE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)
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#define URE_PLA_IDR 0xc000
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#define URE_PLA_RCR 0xc010
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@ -58,6 +64,9 @@
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#define URE_PAL_BDC_CR 0xd1a0
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#define URE_PLA_TEREDO_TIMER 0xd2cc
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#define URE_PLA_REALWOW_TIMER 0xd2e8
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#define URE_PLA_SUSPEND_FLAG 0xd38a
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#define URE_PLA_INDICATE_FALG 0xd38c
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#define URE_PLA_EXTRA_STATUS 0xd398
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#define URE_PLA_LEDSEL 0xdd90
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#define URE_PLA_LED_FEATURE 0xdd92
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#define URE_PLA_PHYAR 0xde00
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@ -74,9 +83,10 @@
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#define URE_PLA_TCR1 0xe612
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#define URE_PLA_MTPS 0xe615
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#define URE_PLA_TXFIFO_CTRL 0xe618
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#define URE_PLA_RSTTELLY 0xe800
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#define URE_PLA_RSTTALLY 0xe800
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#define URE_PLA_CR 0xe813
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#define URE_PLA_CRWECR 0xe81c
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#define URE_PLA_CONFIG34 0xe820
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#define URE_PLA_CONFIG5 0xe822
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#define URE_PLA_PHY_PWR 0xe84c
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#define URE_PLA_OOB_CTRL 0xe84f
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@ -86,7 +96,18 @@
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#define URE_PLA_OCP_GPHY_BASE 0xe86c
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#define URE_PLA_TELLYCNT 0xe890
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#define URE_PLA_SFF_STS_7 0xe8de
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#define URE_PLA_PHYSTATUS 0xe908
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#define URE_GMEDIASTAT 0xe908
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#define URE_PLA_BP_BA 0xfc26
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#define URE_PLA_BP_0 0xfc28
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#define URE_PLA_BP_1 0xfc2a
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#define URE_PLA_BP_2 0xfc2c
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#define URE_PLA_BP_3 0xfc2e
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#define URE_PLA_BP_4 0xfc30
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#define URE_PLA_BP_5 0xfc32
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#define URE_PLA_BP_6 0xfc34
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#define URE_PLA_BP_7 0xfc36
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#define URE_PLA_BP_EN 0xfc38
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#define URE_USB_USB2PHY 0xb41e
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#define URE_USB_SSPHYLINK2 0xb428
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@ -95,22 +116,52 @@
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#define URE_USB_CSR_DUMMY2 0xb466
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#define URE_USB_DEV_STAT 0xb808
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#define URE_USB_CONNECT_TIMER 0xcbf8
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#define URE_USB_MSC_TIMER 0xcbfc
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#define URE_USB_BURST_SIZE 0xcfc0
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#define URE_USB_LPM_CONFIG 0xcfd8
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#define URE_USB_FW_CTRL 0xd334 /* RTL8153B */
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#define URE_USB_USB_CTRL 0xd406
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#define URE_USB_PHY_CTRL 0xd408
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#define URE_USB_TX_AGG 0xd40a
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#define URE_USB_RX_BUF_TH 0xd40c
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#define URE_USB_FW_TASK 0xd4e8 /* RTL8153B */
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#define URE_USB_USB_TIMER 0xd428
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#define URE_USB_RX_EARLY_AGG 0xd42c
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#define URE_USB_PM_CTRL_STATUS 0xd432
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#define URE_USB_RX_EARLY_SIZE 0xd42e
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#define URE_USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
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#define URE_USB_RX_EXTRA_AGG_TMR 0xd432 /* RTL8153B */
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#define URE_USB_TX_DMA 0xd434
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#define URE_USB_UPT_RXDMA_OWN 0xd437
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#define URE_USB_FC_TIMER 0xd340
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#define URE_USB_TOLERANCE 0xd490
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#define URE_USB_LPM_CTRL 0xd41a
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#define URE_USB_BMU_RESET 0xd4b0
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#define URE_USB_U1U2_TIMER 0xd4da
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#define URE_USB_UPS_CTRL 0xd800
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#define URE_USB_MISC_0 0xd81a
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#define URE_USB_POWER_CUT 0xd80a
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#define URE_USB_MISC_0 0xd81a
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#define URE_USB_AFE_CTRL2 0xd824
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#define URE_USB_WDT11_CTRL 0xe43c
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#define URE_USB_BP_BA URE_PLA_BP_BA
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#define URE_USB_BP_0 URE_PLA_BP_0
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#define URE_USB_BP_1 URE_PLA_BP_1
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#define URE_USB_BP_2 URE_PLA_BP_2
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#define URE_USB_BP_3 URE_PLA_BP_3
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#define URE_USB_BP_4 URE_PLA_BP_4
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#define URE_USB_BP_5 URE_PLA_BP_5
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#define URE_USB_BP_6 URE_PLA_BP_6
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#define URE_USB_BP_7 URE_PLA_BP_7
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#define URE_USB_BP_EN URE_PLA_BP_EN /* RTL8153A */
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#define URE_USB_BP_8 0xfc38 /* RTL8153B */
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#define URE_USB_BP_9 0xfc3a
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#define URE_USB_BP_10 0xfc3c
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#define URE_USB_BP_11 0xfc3e
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#define URE_USB_BP_12 0xfc40
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#define URE_USB_BP_13 0xfc42
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#define URE_USB_BP_14 0xfc44
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#define URE_USB_BP_15 0xfc46
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#define URE_USB_BP2_EN 0xfc48
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/* OCP Registers. */
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#define URE_OCP_ALDPS_CONFIG 0x2010
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@ -130,13 +181,19 @@
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#define URE_OCP_EEE_ADV 0xa5d0
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#define URE_OCP_EEE_LPABLE 0xa5d2
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#define URE_OCP_PHY_STATE 0xa708
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#define URE_OCP_PHY_PATCH_STAT 0xb800
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#define URE_OCP_PHY_PATCH_CMD 0xb820
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#define URE_OCP_PHY_LOCK 0xb82e
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#define URE_OCP_ADC_CFG 0xbc06
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/* SRAM Register. */
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#define URE_SRAM_GREEN_CFG 0x8011
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#define URE_SRAM_LPF_CFG 0x8012
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#define URE_SRAM_GPHY_FW_VER 0x801e
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#define URE_SRAM_10M_AMP1 0x8080
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#define URE_SRAM_10M_AMP2 0x8082
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#define URE_SRAM_IMPEDANCE 0x8084
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#define URE_SRAM_PHY_LOCK 0xb82e
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/* PLA_RCR */
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#define URE_RCR_AAP 0x00000001
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@ -189,6 +246,13 @@
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/* PLA_TCR1 */
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#define URE_VERSION_MASK 0x7cf0
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/* PLA_MTPS */
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#define URE_MTPS_DEFAULT 96
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#define URE_MTPS_JUMBO 192
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/* PLA_RSTTALLY */
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#define URE_TALLY_RESET 0x0001
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/* PLA_CR */
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#define URE_CR_RST 0x10
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#define URE_CR_RE 0x08
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@ -225,6 +289,10 @@
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/* PAL_BDC_CR */
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#define URE_ALDPS_PROXY_MODE 0x0001
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/* URE_PLA_CONFIG34 */
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#define URE_LINK_OFF_WAKE_EN 0x0008
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#define URE_LINK_ON_WAKE_EN 0x0010
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/* PLA_CONFIG5 */
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#define URE_LAN_WAKE_EN 0x0002
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@ -242,9 +310,11 @@
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#define URE_ALDPS_SPDWN_RATIO 0x0f87
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/* PLA_MAC_PWR_CTRL2 */
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#define URE_MAC_CLK_SPDWN_EN 0x8000
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#define URE_EEE_SPDWN_RATIO 0x8007
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/* PLA_MAC_PWR_CTRL3 */
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#define URE_PLA_MCU_SPDWN_EN 0x4000
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#define URE_PKT_AVAIL_SPDWN_EN 0x0100
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#define URE_SUSPEND_SPDWN_EN 0x0004
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#define URE_U1U2_SPDWN_EN 0x0002
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@ -276,6 +346,27 @@
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/* PLA_BOOT_CTRL */
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#define URE_AUTOLOAD_DONE 0x0002
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/* PLA_SUSPEND_FLAG */
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#define URE_LINK_CHG_EVENT 0x01
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/* PLA_INDICATE_FALG */
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#define URE_UPCOMING_RUNTIME_D3 0x01
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/* PLA_EXTRA_STATUS */
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#define URE_POLL_LINK_CHG 0x0001
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#define URE_LINK_CHANGE_FLAG 0x0100
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#define URE_CUR_LINK_OK 0x8000
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/* URE_PLA_PHYSTATUS */
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#define URE_PHYSTATUS_FDX 0x0001
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#define URE_PHYSTATUS_LINK 0x0002
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#define URE_PHYSTATUS_10MBPS 0x0004
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#define URE_PHYSTATUS_100MBPS 0x0008
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#define URE_PHYSTATUS_1000MBPS 0x0010
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#define URE_PHYSTATUS_500MBPS 0x0100
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#define URE_PHYSTATUS_1250MBPS 0x0200
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#define URE_PHYSTATUS_2500MBPS 0x0400
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/* USB_USB2PHY */
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#define URE_USB2PHY_SUSPEND 0x0001
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#define URE_USB2PHY_L1 0x0002
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@ -295,6 +386,9 @@
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#define URE_STAT_SPEED_HIGH 0x0000
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#define URE_STAT_SPEED_FULL 0x0001
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/* URE_USB_LPM_CONFIG */
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#define URE_LPM_U1U2_EN 0x0001
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/* USB_TX_AGG */
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#define URE_TX_AGG_MAX_THRESHOLD 0x03
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@ -302,17 +396,35 @@
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#define URE_RX_THR_SUPER 0x0c350180
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#define URE_RX_THR_HIGH 0x7a120180
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#define URE_RX_THR_SLOW 0xffff0180
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#define URE_RX_THR_B 0x00010001
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/* USB_TX_DMA */
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#define URE_TEST_MODE_DISABLE 0x00000001
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#define URE_TX_SIZE_ADJUST1 0x00000100
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/* USB_BMU_RESET */
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#define URE_BMU_RESET_EP_IN 0x01
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#define URE_BMU_RESET_EP_OUT 0x02
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/* USB_UPT_RXDMA_OWN */
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#define URE_OWN_UPDATE 0x01
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#define URE_OWN_CLEAR 0x02
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/* USB_FW_TASK */
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#define URE_FC_PATCH_TASK 0x0001
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/* USB_UPS_CTRL */
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#define URE_POWER_CUT 0x0100
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/* USB_PM_CTRL_STATUS */
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#define URE_RESUME_INDICATE 0x0001
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/* USB_FW_CTRL */
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#define URE_FLOW_CTRL_PATCH_OPT 0x01
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/* USB_FC_TIMER */
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#define URE_CTRL_TIMER_EN 0x8000
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/* USB_USB_CTRL */
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#define URE_RX_AGG_DISABLE 0x0010
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#define URE_RX_ZERO_EN 0x0080
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@ -321,8 +433,10 @@
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#define URE_U2P3_ENABLE 0x0001
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/* USB_POWER_CUT */
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#define URE_PWR_EN 0x0001
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#define URE_PWR_EN 0x0001
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#define URE_PHASE2_EN 0x0008
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#define URE_UPS_EN 0x0010
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#define URE_USP_PREWAKE 0x0020
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/* USB_MISC_0 */
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#define URE_PCUT_STATUS 0x0001
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@ -355,6 +469,7 @@
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/* OCP_PHY_STATUS */
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#define URE_PHY_STAT_MASK 0x0007
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#define URE_PHY_STAT_EXT_INIT 2
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#define URE_PHY_STAT_LAN_ON 3
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#define URE_PHY_STAT_PWRDN 5
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@ -369,16 +484,37 @@
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/* OCP_DOWN_SPEED */
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#define URE_EN_10M_BGOFF 0x0080
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#define URE_EN_10M_CLKDIV 0x0800
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#define URE_EN_EEE_100 0x1000
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#define URE_EN_EEE_1000 0x2000
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#define URE_EN_EEE_CMODE 0x4000
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/* OCP_PHY_STATE */
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#define URE_TXDIS_STATE 0x01
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#define URE_ABD_STATE 0x02
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/* OCP_PHY_PATCH_STAT */
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#define URE_PATCH_READY 0x40
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/* OCP_PHY_PATCH_CMD */
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#define URE_PATCH_REQUEST 0x10
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/* OCP_PHY_LOCK */
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#define URE_PATCH_LOCK 0x01
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/* OCP_ADC_CFG */
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#define URE_CKADSEL_L 0x0100
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#define URE_ADC_EN 0x0080
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#define URE_EN_EMI_L 0x0040
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/* SRAM_GREEN_CFG */
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#define URE_GREEN_ETH_EN 0x8000
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/* SRAM_PHY_LOCK */
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#define URE_PHY_PATCH_LOCK 0x0001
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#define URE_ADV_2500TFDX 0x0080
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#define URE_MCU_TYPE_PLA 0x0100
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#define URE_MCU_TYPE_USB 0x0000
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@ -423,44 +559,64 @@ struct ure_txpkt {
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#define URE_TKPKT_TX_LS (1 << 30)
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#define URE_TXPKT_LEN_MASK 0xffff
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uint32_t ure_csum;
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#define URE_L4_OFFSET_MAX 0x7ff
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#define URE_L4_OFFSET_SHIFT 17
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#define URE_L4_OFFSET_MAX 0x7ff
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#define URE_L4_OFFSET_SHIFT 17
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#define URE_TXPKT_VLAN_MASK 0xffff
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#define URE_TXPKT_VLAN (1 << 16)
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#define URE_TXPKT_IPV6_CS (1 << 28)
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#define URE_TXPKT_IPV4_CS (1 << 29)
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#define URE_TXPKT_TCP_CS (1 << 30)
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#define URE_TXPKT_UDP_CS (1 << 31)
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#define URE_TXPKT_VLAN (1 << 16)
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#define URE_TXPKT_IPV6_CS (1 << 28)
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#define URE_TXPKT_IPV4_CS (1 << 29)
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#define URE_TXPKT_TCP_CS (1 << 30)
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#define URE_TXPKT_UDP_CS (1 << 31)
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/* Lower 12 bits are the VLAN tag */
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} __packed;
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#define URE_N_TRANSFER 4
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#define URE_TRANSFER_SIZE 16384
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#define URE_MAX_TX 4
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#define URE_MAX_RX 4
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#define URE_TX_BUFSZ 16384
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#define URE_8152_RX_BUFSZ (16 * 1024)
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#define URE_8153_RX_BUFSZ (32 * 1024)
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#define URE_8156_RX_BUFSZ (48 * 1024)
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struct ure_softc {
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struct usb_ether sc_ue;
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struct ifmedia sc_ifmedia;
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struct mtx sc_mtx;
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struct usb_xfer *sc_rx_xfer[URE_N_TRANSFER];
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struct usb_xfer *sc_tx_xfer[URE_N_TRANSFER];
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struct usb_xfer *sc_rx_xfer[URE_MAX_RX];
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struct usb_xfer *sc_tx_xfer[URE_MAX_TX];
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int sc_rxbufsz;
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int sc_rxstarted;
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int sc_phyno;
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u_int sc_flags;
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#define URE_FLAG_LINK 0x0001
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#define URE_FLAG_8152 0x1000 /* RTL8152 */
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#define URE_FLAG_8152 0x0100 /* RTL8152 */
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#define URE_FLAG_8153 0x0200 /* RTL8153 */
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#define URE_FLAG_8153B 0x0400 /* RTL8153B */
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#define URE_FLAG_8156 0x0800 /* RTL8156 */
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#define URE_FLAG_8156B 0x1000 /* RTL8156B */
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u_int sc_chip;
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u_int sc_ver;
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#define URE_CHIP_VER_4C00 0x01
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#define URE_CHIP_VER_4C10 0x02
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#define URE_CHIP_VER_5C00 0x04
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#define URE_CHIP_VER_5C10 0x08
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#define URE_CHIP_VER_5C20 0x10
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#define URE_CHIP_VER_5C30 0x20
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#define URE_CHIP_VER_4C00 0x0001
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#define URE_CHIP_VER_4C10 0x0002
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#define URE_CHIP_VER_5C00 0x0004
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#define URE_CHIP_VER_5C10 0x0008
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#define URE_CHIP_VER_5C20 0x0010
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#define URE_CHIP_VER_5C30 0x0020
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#define URE_CHIP_VER_6000 0x0040
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#define URE_CHIP_VER_6010 0x0080
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#define URE_CHIP_VER_7020 0x0100
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#define URE_CHIP_VER_7030 0x0200
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#define URE_CHIP_VER_7400 0x0400
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#define URE_CHIP_VER_7410 0x0800
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};
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#define URE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define URE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define URE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
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#endif /* _IF_UREREG_H_ */
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