diff --git a/lib/libc/mips/Makefile.inc b/lib/libc/mips/Makefile.inc
index ebee3aa1d8bf..f340477ad22a 100644
--- a/lib/libc/mips/Makefile.inc
+++ b/lib/libc/mips/Makefile.inc
@@ -1,9 +1,5 @@
 #	$NetBSD: Makefile.inc,v 1.7 2005/09/17 11:49:39 tsutsui Exp $
 # $FreeBSD$
 
-.if ${MACHINE_ARCH:Mmips*hf} == ""
-CFLAGS+=-DSOFTFLOAT
-.endif
-
 SRCS+= machdep_ldisd.c
 SYM_MAPS+= ${LIBC_SRCTOP}/mips/Symbol.map
diff --git a/lib/libc/mips/gen/_setjmp.S b/lib/libc/mips/gen/_setjmp.S
index 0f7a75a82a6d..6944d06fbb2c 100644
--- a/lib/libc/mips/gen/_setjmp.S
+++ b/lib/libc/mips/gen/_setjmp.S
@@ -90,7 +90,7 @@ LEAF(_setjmp)
 	 * In N64, FP registers F24 .. F31 are callee-saved.
 	 * In O32, FP registers F20 .. F23 are callee-saved.
 	 */
-#ifndef SOFTFLOAT
+#ifndef __mips_soft_float
 	cfc1	v0, $31				# too bad can't check if FP used
 #if defined(__mips_n64) || defined(__mips_n32)
 	FP_S	$f30, (_JB_FPREG_F30 * SZREG)(a0)
@@ -113,7 +113,7 @@ LEAF(_setjmp)
 	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
 #endif
 	INT_S	v0, (_JB_FPREG_FCSR * SZREG)(a0)
-#endif /* ! SOFTFLOAT */
+#endif /* ! __mips_soft_float */
 	REG_EPILOGUE
 
 	j	ra
@@ -151,7 +151,7 @@ LEAF(_longjmp)
 #if defined(__mips_n32) || defined(__mips_n64)
 	REG_L		gp, (_JB_REG_GP * SZREG)(a0)
 #endif
-#ifndef SOFTFLOAT
+#ifndef __mips_soft_float
 	# get fpu status
 	INT_L		v0, (_JB_FPREG_FCSR * SZREG)(a0)
 	ctc1		v0, $31
@@ -181,7 +181,7 @@ LEAF(_longjmp)
 	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
 	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
 #endif
-#endif	/* ! SOFTFLOAT */
+#endif	/* ! __mips_soft_float */
 
 	REG_EPILOGUE
 	move	v0, a1			# get return value in 1st arg
diff --git a/lib/libc/mips/gen/flt_rounds.c b/lib/libc/mips/gen/flt_rounds.c
index 73428d907d11..27d8bf35315f 100644
--- a/lib/libc/mips/gen/flt_rounds.c
+++ b/lib/libc/mips/gen/flt_rounds.c
@@ -14,7 +14,7 @@ __RCSID("$NetBSD: flt_rounds.c,v 1.5 2005/12/24 23:10:08 perry Exp $");
 #include <fenv.h>
 #include <float.h>
 
-#ifdef	SOFTFLOAT
+#ifdef	__mips_soft_float
 #include "softfloat-for-gcc.h"
 #include "milieu.h"
 #include "softfloat.h"
@@ -32,7 +32,7 @@ __flt_rounds()
 {
 	int mode;
 
-#ifdef SOFTFLOAT
+#ifdef __mips_soft_float
 	mode = __softfloat_float_rounding_mode;
 #else
 	__asm __volatile("cfc1 %0,$31" : "=r" (mode));
diff --git a/lib/libc/mips/gen/setjmp.S b/lib/libc/mips/gen/setjmp.S
index 9c9e8b8d9ee0..4eb12f53b703 100644
--- a/lib/libc/mips/gen/setjmp.S
+++ b/lib/libc/mips/gen/setjmp.S
@@ -106,7 +106,7 @@ NESTED(setjmp, SETJMP_FRAME_SIZE, ra)
 #if defined(__mips_n32) || defined(__mips_n64)
 	REG_S	gp, (_JB_REG_GP * SZREG)(a0)
 #endif
-#ifndef SOFTFLOAT
+#ifndef __mips_soft_float
 	/*
 	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
 	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
@@ -135,7 +135,7 @@ NESTED(setjmp, SETJMP_FRAME_SIZE, ra)
 	FP_S	$f29, (_JB_FPREG_F29 * SZREG)(a0)
 	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
 #endif
-#endif	/* ! SOFTFLOAT */
+#endif	/* ! __mips_soft_float */
 
 	move	v0, zero
 	jr	ra
@@ -190,7 +190,7 @@ NESTED(longjmp, LONGJMP_FRAME_SIZE, ra)
 #if defined(__mips_n32) || defined(__mips_n64)
 	REG_L	gp, (_JB_REG_GP * SZREG)(a0)
 #endif
-#ifndef SOFTFLOAT
+#ifndef __mips_soft_float
 	/*
 	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
 	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
@@ -219,7 +219,7 @@ NESTED(longjmp, LONGJMP_FRAME_SIZE, ra)
 	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
 	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
 #endif
-#endif	/* ! SOFTFLOAT */
+#endif	/* ! __mips_soft_float */
 
 	move	v0, a1
 	j	ra
diff --git a/lib/msun/mips/Makefile.inc b/lib/msun/mips/Makefile.inc
index b05f4fa3812b..8c1a4864f4cf 100644
--- a/lib/msun/mips/Makefile.inc
+++ b/lib/msun/mips/Makefile.inc
@@ -1,8 +1,4 @@
 # $FreeBSD$
 
-.if ${MACHINE_ARCH:Mmips*hf} == ""
-CFLAGS+=-DSOFTFLOAT
-.endif
-
 LDBL_PREC = 53
 SYM_MAPS += ${.CURDIR}/mips/Symbol.map
diff --git a/lib/msun/mips/fenv.c b/lib/msun/mips/fenv.c
index 64beb704c74e..55890e740476 100644
--- a/lib/msun/mips/fenv.c
+++ b/lib/msun/mips/fenv.c
@@ -39,7 +39,7 @@
  */
 const fenv_t __fe_dfl_env = 0;
 
-#ifdef	SOFTFLOAT
+#ifdef	__mips_soft_float
 #define __set_env(env, flags, mask, rnd) env = ((flags)                 \
                                                 | (mask)<<_FPUSW_SHIFT  \
                                                 | (rnd) << 24)
diff --git a/lib/msun/mips/fenv.h b/lib/msun/mips/fenv.h
index 498af3471b5d..3f8f145d6d61 100644
--- a/lib/msun/mips/fenv.h
+++ b/lib/msun/mips/fenv.h
@@ -39,7 +39,7 @@ typedef	__uint32_t	fenv_t;
 typedef	__uint32_t	fexcept_t;
 
 /* Exception flags */
-#ifdef SOFTFLOAT
+#ifdef __mips_soft_float
 #define	_FPUSW_SHIFT	16
 #define	FE_INVALID	0x0001
 #define	FE_DIVBYZERO	0x0002
@@ -74,12 +74,16 @@ extern const fenv_t	__fe_dfl_env;
 #define	_ENABLE_SHIFT	5
 #define	_ENABLE_MASK	(FE_ALL_EXCEPT << _ENABLE_SHIFT)
 
-#ifndef	SOFTFLOAT
+#if !defined(__mips_soft_float) && !defined(__mips_hard_float)
+#error compiler didnt set soft/hard float macros
+#endif
+
+#ifndef	__mips_soft_float
 #define	__cfc1(__fcsr)	__asm __volatile("cfc1 %0, $31" : "=r" (__fcsr))
 #define	__ctc1(__fcsr)	__asm __volatile("ctc1 %0, $31" :: "r" (__fcsr))
 #endif
 
-#ifdef SOFTFLOAT
+#ifdef __mips_soft_float
 int feclearexcept(int __excepts);
 int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
@@ -223,13 +227,13 @@ feupdateenv(const fenv_t *__envp)
 
 	return (0);
 }
-#endif /* !SOFTFLOAT */
+#endif /* !__mips_soft_float */
 
 #if __BSD_VISIBLE
 
 /* We currently provide no external definitions of the functions below. */
 
-#ifdef SOFTFLOAT
+#ifdef __mips_soft_float
 int feenableexcept(int __mask);
 int fedisableexcept(int __mask);
 int fegetexcept(void);
@@ -268,7 +272,7 @@ fegetexcept(void)
 	return ((fcsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
 }
 
-#endif /* !SOFTFLOAT */
+#endif /* !__mips_soft_float */
 
 #endif /* __BSD_VISIBLE */