Add AR5413 radar parameters and strong signal diversity capability.
This is a re-implementation based on the reference carrier code for the AR5413. Tested: * Pulse detection for AR5212 and AR5413, to ensure the correct behaviour for both chips PR: kern/170904 Obtained from: Qualcomm Atheros
This commit is contained in:
Adrian Chadd
parent
0146ef1ae2
commit
d6af4e0f06
@ -843,6 +843,10 @@ ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
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return HAL_OK;
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case 1: /* current setting */
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return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
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case HAL_CAP_STRONG_DIV:
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*result = OS_REG_READ(ah, AR_PHY_RESTART);
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*result = MS(*result, AR_PHY_RESTART_DIV_GC);
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return HAL_OK;
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}
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return HAL_EINVAL;
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case HAL_CAP_DIAG:
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@ -950,16 +954,34 @@ ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
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OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
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return AH_TRUE;
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case HAL_CAP_DIVERSITY:
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if (ahp->ah_phyPowerOn) {
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v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
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if (setting)
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v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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else
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v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
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switch (capability) {
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case 0:
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return AH_FALSE;
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case 1: /* setting */
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if (ahp->ah_phyPowerOn) {
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if (capability == HAL_CAP_STRONG_DIV) {
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}
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v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
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if (setting)
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v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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else
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v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
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}
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ahp->ah_diversity = (setting != 0);
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return AH_TRUE;
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case HAL_CAP_STRONG_DIV:
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if (! ahp->ah_phyPowerOn)
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return AH_FALSE;
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v = OS_REG_READ(ah, AR_PHY_RESTART);
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v &= ~AR_PHY_RESTART_DIV_GC;
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v |= SM(setting, AR_PHY_RESTART_DIV_GC);
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OS_REG_WRITE(ah, AR_PHY_RESTART, v);
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return AH_TRUE;
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default:
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return AH_FALSE;
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}
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ahp->ah_diversity = (setting != 0);
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return AH_TRUE;
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case HAL_CAP_DIAG: /* hardware diagnostic support */
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/*
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* NB: could split this up into virtual capabilities,
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@ -1165,14 +1187,61 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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else
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val &= ~ AR_PHY_RADAR_0_ENA;
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if (IS_5413(ah)) {
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if (pe->pe_blockradar == 1)
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OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_BLOCKOFDMWEAK);
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else
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OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_BLOCKOFDMWEAK);
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if (pe->pe_en_relstep_check == 1)
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OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENRELSTEPCHK);
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else
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OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENRELSTEPCHK);
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if (pe->pe_usefir128 == 1)
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OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_USEFIR128);
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else
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OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_USEFIR128);
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if (pe->pe_enmaxrssi == 1)
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OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENMAXRSSI);
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else
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OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENMAXRSSI);
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if (pe->pe_enrelpwr == 1)
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OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENRELPWRCHK);
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else
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OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_ENRELPWRCHK);
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if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL)
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OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_RELPWR, pe->pe_relpwr);
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if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL)
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OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_RELSTEP, pe->pe_relstep);
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if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL)
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OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
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AR_PHY_RADAR_2_MAXLEN, pe->pe_maxlen);
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}
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OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
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}
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/*
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* Parameters for the AR5212 PHY.
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*
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* TODO: figure out what values were added for the AR5413 and later
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* PHY; update these here.
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*/
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#define AR5212_DFS_FIRPWR -41
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#define AR5212_DFS_RRSSI 12
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@ -1180,19 +1249,52 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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#define AR5212_DFS_PRSSI 22
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#define AR5212_DFS_INBAND 6
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/*
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* Default parameters for the AR5413 PHY.
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*/
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#define AR5413_DFS_FIRPWR -34
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#define AR5413_DFS_RRSSI 20
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#define AR5413_DFS_HEIGHT 10
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#define AR5413_DFS_PRSSI 15
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#define AR5413_DFS_INBAND 6
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#define AR5413_DFS_RELPWR 8
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#define AR5413_DFS_RELSTEP 31
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#define AR5413_DFS_MAXLEN 255
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HAL_BOOL
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ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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{
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pe->pe_firpwr = AR5212_DFS_FIRPWR;
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pe->pe_rrssi = AR5212_DFS_RRSSI;
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pe->pe_height = AR5212_DFS_HEIGHT;
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pe->pe_prssi = AR5212_DFS_PRSSI;
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pe->pe_inband = AR5212_DFS_INBAND;
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/* XXX look up what is needed for the AR5413 */
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pe->pe_relpwr = 0;
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pe->pe_relstep = 0;
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pe->pe_maxlen = 0;
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if (IS_5413(ah)) {
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pe->pe_firpwr = AR5413_DFS_FIRPWR;
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pe->pe_rrssi = AR5413_DFS_RRSSI;
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pe->pe_height = AR5413_DFS_HEIGHT;
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pe->pe_prssi = AR5413_DFS_PRSSI;
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pe->pe_inband = AR5413_DFS_INBAND;
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pe->pe_relpwr = AR5413_DFS_RELPWR;
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pe->pe_relstep = AR5413_DFS_RELSTEP;
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pe->pe_maxlen = AR5413_DFS_MAXLEN;
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pe->pe_usefir128 = 0;
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pe->pe_blockradar = 1;
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pe->pe_enmaxrssi = 1;
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pe->pe_enrelpwr = 1;
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pe->pe_en_relstep_check = 0;
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} else {
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pe->pe_firpwr = AR5212_DFS_FIRPWR;
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pe->pe_rrssi = AR5212_DFS_RRSSI;
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pe->pe_height = AR5212_DFS_HEIGHT;
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pe->pe_prssi = AR5212_DFS_PRSSI;
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pe->pe_inband = AR5212_DFS_INBAND;
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pe->pe_relpwr = 0;
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pe->pe_relstep = 0;
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pe->pe_maxlen = 0;
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pe->pe_usefir128 = 0;
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pe->pe_blockradar = 0;
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pe->pe_enmaxrssi = 0;
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pe->pe_enrelpwr = 0;
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pe->pe_en_relstep_check = 0;
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}
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return (AH_TRUE);
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}
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@ -1216,7 +1318,26 @@ ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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pe->pe_relpwr = 0;
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pe->pe_relstep = 0;
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pe->pe_maxlen = 0;
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pe->pe_usefir128 = 0;
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pe->pe_blockradar = 0;
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pe->pe_enmaxrssi = 0;
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pe->pe_enrelpwr = 0;
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pe->pe_en_relstep_check = 0;
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pe->pe_extchannel = AH_FALSE;
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if (IS_5413(ah)) {
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val = OS_REG_READ(ah, AR_PHY_RADAR_2);
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pe->pe_relpwr = !! MS(val, AR_PHY_RADAR_2_RELPWR);
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pe->pe_relstep = !! MS(val, AR_PHY_RADAR_2_RELSTEP);
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pe->pe_maxlen = !! MS(val, AR_PHY_RADAR_2_MAXLEN);
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pe->pe_usefir128 = !! (val & AR_PHY_RADAR_2_USEFIR128);
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pe->pe_blockradar = !! (val & AR_PHY_RADAR_2_BLOCKOFDMWEAK);
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pe->pe_enmaxrssi = !! (val & AR_PHY_RADAR_2_ENMAXRSSI);
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pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_2_ENRELPWRCHK);
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pe->pe_en_relstep_check =
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!! (val & AR_PHY_RADAR_2_ENRELSTEPCHK);
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}
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}
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/*
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@ -221,6 +221,19 @@
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#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
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#define AR_PHY_RADAR_0_FIRPWR_S 24
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/* ar5413 specific */
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#define AR_PHY_RADAR_2 0x9958 /* radar detection settings */
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#define AR_PHY_RADAR_2_ENRELSTEPCHK 0x00002000 /* Enable using max rssi */
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#define AR_PHY_RADAR_2_ENMAXRSSI 0x00004000 /* Enable using max rssi */
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#define AR_PHY_RADAR_2_BLOCKOFDMWEAK 0x00008000 /* En block OFDM weak sig as radar */
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#define AR_PHY_RADAR_2_USEFIR128 0x00400000 /* En measuring pwr over 128 cycles */
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#define AR_PHY_RADAR_2_ENRELPWRCHK 0x00800000 /* Enable using max rssi */
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#define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */
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#define AR_PHY_RADAR_2_MAXLEN_S 0
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#define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */
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#define AR_PHY_RADAR_2_RELSTEP_S 8
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#define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */
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#define AR_PHY_RADAR_2_RELPWR_S 16
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#define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */
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#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
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