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@ -1,460 +0,0 @@
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.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd October 4, 2008
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.Dt PMC 3
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.Os
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.Sh NAME
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.Nm pmc
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.Nd library for accessing hardware performance monitoring counters
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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Intel Pentium PMCs are present in Intel
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.Tn Pentium
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and
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.Tn "Pentium MMX"
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processors.
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These PMCs are documented in the
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.Rs
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.%B "Intel 64 and IA-32 Intel(R) Architectures Software Developer's Manual"
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.%T "Volume 3B: System Programming Guide, Part 2"
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.%N "Order Number 253669-024US"
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.%D "August 2007"
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.%Q "Intel Corporation"
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.Re
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.Ss PMC Features
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These CPUs contain two PMCs, each 40 bits wide.
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These PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta \&No
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.It PMC_CAP_INTERRUPT Ta \&No
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.It PMC_CAP_INVERT Ta \&No
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta \&No
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for Intel Pentium PMCs can have the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li duration
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Count duration (in clocks) of events.
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The default is to count events.
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.It Li os
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Measure events at privilege levels 0, 1 and 2.
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.It Li overflow
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Assert the external processor pin associated with a counter on counter
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overflow.
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.It Li usr
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Measure events at privilege level 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers are specified, the default is to enable both.
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.Pp
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Some events may only be used on specific counters and some events
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are defined only on processors supporting the MMX instruction set.
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Note that these PMCs do not have the ability to interrupt the CPU.
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.Ss Intel Pentium Event Specifiers
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The event specifiers supported by Intel Pentium PMCs are:
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.Bl -tag -width indent
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.It Li p5-any-segment-register-loaded
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.Pq Event 0FH
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The number of writes to any segment register, including the LDTR,
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GDTR, TR and IDTR.
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Far control transfers and task switches that involve privilege
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level changes will count this event twice.
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.It Li p5-bank-conflicts
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.Pq Event 0AH
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The number of actual bank conflicts.
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.It Li p5-branches
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.Pq Event 12H
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The number of taken and not taken branches including branches, jumps, calls,
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software interrupts and interrupt returns.
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.It Li p5-breakpoint-match-on-dr0-register
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.Pq Event 23H
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The number of matches on the DR0 breakpoint register.
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.It Li p5-breakpoint-match-on-dr1-register
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.Pq Event 24H
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The number of matches on the DR1 breakpoint register.
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.It Li p5-breakpoint-match-on-dr2-register
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.Pq Event 25H
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The number of matches on the DR2 breakpoint register.
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.It Li p5-breakpoint-match-on-dr3-register
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.Pq Event 26H
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The number of matches on the DR3 breakpoint register.
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.It Li p5-btb-false-entries
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.Pq Event 3AH , Tn Pentium MMX
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The number of false entries in the BTB.
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This event is only allocated on counter 0.
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.It Li p5-btb-hits
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.Pq Event 13H
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The number of branches executed that hit in the branch table buffer.
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.It Li p5-btb-miss-prediction-on-not-taken-branch
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.Pq Event 3AH , Tn Pentium MMX
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The number of times the BTB predicted a not-taken branch as taken.
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This event is only allocated on counter 1.
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.It Li p5-bus-cycle-duration
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.Pq Event 18H
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The number of cycles while a bus cycle was in progress.
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.It Li p5-bus-ownership-latency
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.Pq Event 2AH , Tn Pentium MMX
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The time from bus ownership being requested to ownership being granted.
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This event is only allocated on counter 0.
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.It Li p5-bus-ownership-transfers
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.Pq Event 2AH , Tn Pentium MMX
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The number of bus ownership transfers.
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This event is only allocated on counter 1.
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.It Li p5-bus-utilization-due-to-processor-activity
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.Pq Event 2EH , Tn Pentium MMX
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The number of clocks the bus is busy due to the processor's own
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activity.
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This event is only allocated on counter 0.
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.It Li p5-cache-line-sharing
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.Pq Event 2CH , Tn Pentium MMX
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The number of shared data lines in L1 cache.
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This event is only allocated on counter 1.
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.It Li p5-cache-m-state-line-sharing
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.Pq Event 2CH , Tn Pentium MMX
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The number of hits to an M- state line due to a memory access by
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another processor.
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This event is only allocated on counter 0.
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.It Li p5-code-cache-miss
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.Pq Event 0EH
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The number of instruction reads that miss the internal code cache.
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Both cacheable and un-cacheable misses are counted.
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.It Li p5-code-read
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.Pq Event 0CH
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The number of instruction reads to both cacheable and un-cacheable regions.
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.It Li p5-code-tlb-miss
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.Pq Event 0DH
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The number of instruction reads that miss the instruction TLB.
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Both cacheable and un-cacheable unreads are counted.
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.It Li p5-d1-starvation-and-fifo-is-empty
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.Pq Event 33H , Tn Pentium MMX
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The number of times the D1 stage cannot issue any instructions because
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the FIFO was empty.
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This event is only allocated on counter 0.
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.It Li p5-d1-starvation-and-only-one-instruction-in-fifo
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.Pq Event 33H , Tn Pentium MMX
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The number of times the D1 stage could issue only one instruction
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because the FIFO had one instruction ready.
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This event is only allocated on counter 1.
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.It Li p5-data-cache-lines-written-back
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.Pq Event 06H
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The number of data cache lines that are written back, including
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those caused by internal and external snoops.
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.It Li p5-data-cache-tlb-miss-stall-duration
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.Pq Event 30H , Tn Pentium MMX
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The number of clocks the pipeline is stalled due to a data cache
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TLB miss.
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This event is only allocated on counter 1.
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.It Li p5-data-read
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.Pq Event 00H
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The number of memory data reads, counting internal data cache hits and
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misses.
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I/O and data memory accesses due to TLB miss processing are
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not included.
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Split cycle reads are counted individually.
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.It Li p5-data-read-miss
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.Pq Event 03H
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The number of memory read accesses that miss the data cache, counting
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both cacheable and un-cacheable accesses.
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Data accesses that are part of TLB miss processing are not included.
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I/O accesses are not included.
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.It Li p5-data-read-miss-or-write-miss
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.Pq Event 29H
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The number of data reads and writes that miss the internal data cache,
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counting un-cacheable accesses.
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Data accesses due to TLB miss processing are not counted.
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.It Li p5-data-read-or-write
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.Pq Event 28H
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The number of data reads and writes including internal data cache hits
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and misses.
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Data reads due to TLB miss processing are not counted.
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.It Li p5-data-tlb-miss
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.Pq Event 02H
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The number of misses to the data cache translation look aside buffer.
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.It Li p5-data-write
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.Pq Event 01H
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The number of memory data writes, counting internal data cache hits
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and misses.
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I/O is not included and split cycle writes are counted individually.
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.It Li p5-data-write-miss
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.Pq Event 04H
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The number of memory write accesses that miss the data cache, counting
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both cacheable and un-cacheable accesses.
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I/O accesses are not counted.
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.It Li p5-emms-instructions-executed
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.Pq Event 2DH , Tn Pentium MMX
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The number of EMMS instructions executed.
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This event is only allocated on counter 0.
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.It Li p5-external-data-cache-snoop-hits
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.Pq Event 08H
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The number of external snoops to the data cache that hit a valid line,
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or the data line fill buffer, or one of the write back buffers.
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.It Li p5-external-snoops
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.Pq Event 07H
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The number of external snoop requests accepted, including snoops that
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hit in the code cache, the data cache and that hit in neither.
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.It Li p5-floating-point-stalls-duration
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.Pq Event 32H , Tn Pentium MMX
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The number of cycles the pipeline is stalled due to a floating point
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freeze.
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This event is only allocated on counter 0.
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.It Li p5-flops
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.Pq Event 22H
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The number of floating point adds, subtracts, multiples, divides and
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square roots.
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Transcendental instructions trigger this event multiple times.
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Instructions generating divide-by-zero, negative square root, special
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operand and stack exceptions are not counted.
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Integer multiply instructions that use the x87 FPU are counted.
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.It Li p5-full-write-buffer-stall-duration-while-executing-mmx-instructions
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.Pq Event 3BH , Tn Pentium MMX
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The number of clocks the pipeline has stalled due to full write
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buffers when executing MMX instructions.
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This event is only allocated on counter 0.
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.It Li p5-hardware-interrupts
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.Pq Event 27H
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The number of taken INTR and NMI interrupts.
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.It Li p5-instructions-executed
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.Pq Event 16H
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The number of instructions executed.
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Repeat prefixed instructions are counted only once.
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The HLT instruction is counted only once, irrespective of the number
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of cycles spent in the halted state.
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All hardware and software exceptions are counted as instructions, and
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fault handler invocations are also counted as instructions.
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.It Li p5-instructions-executed-v-pipe
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.Pq Event 17H
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The number of instructions that executed in the V pipe.
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.It Li p5-io-read-or-write-cycle
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.Pq Event 1DH
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The number of bus cycles directed to I/O space.
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.It Li p5-locked-bus-cycle
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.Pq Event 1CH
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The number of locked bus cycles that occur on account of the lock
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prefixes, LOCK instructions, page table updates and descriptor table
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updates.
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.It Li p5-memory-accesses-in-both-pipes
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.Pq Event 09H
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The number of data memory reads or writes that are paired in both pipes.
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.It Li p5-misaligned-data-memory-or-io-references
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.Pq Event 0BH
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The number of memory or I/O reads or writes that are not aligned on
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natural boundaries.
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2- and 4-byte accesses are counted as misaligned if they cross a 4
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byte boundary.
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.It Li p5-misaligned-data-memory-reference-on-mmx-instructions
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.Pq Event 36H , Tn Pentium MMX
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The number of misaligned data memory references when executing MMX
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instructions.
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This event is only allocated on counter 0.
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.It Li p5-mispredicted-or-unpredicted-returns
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.Pq Event 37H , Tn Pentium MMX
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The number of returns predicted incorrectly or not at all, only
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counting RET instructions.
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This event is only allocated on counter 0.
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.It Li p5-mmx-instruction-data-read-misses
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.Pq Event 31H , Tn Pentium MMX
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The number of MMX instruction data read misses.
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This event is only allocated on counter 1.
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.It Li p5-mmx-instruction-data-reads
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.Pq Event 31H , Tn Pentium MMX
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The number of MMX instruction data reads.
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This event is only allocated on counter 0.
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|
|
|
.It Li p5-mmx-instruction-data-write-misses
|
|
|
|
|
.Pq Event 34H , Tn Pentium MMX
|
|
|
|
|
The number of data write misses caused by MMX instructions.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-mmx-instruction-data-writes
|
|
|
|
|
.Pq Event 34H , Tn Pentium MMX
|
|
|
|
|
The number of data writes caused by MMX instructions.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-mmx-instructions-executed-u-pipe
|
|
|
|
|
.Pq Event 2BH , Tn Pentium MMX
|
|
|
|
|
The number of MMX instructions executed in the U pipe.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-mmx-instructions-executed-v-pipe
|
|
|
|
|
.Pq Event 2BH , Tn Pentium MMX
|
|
|
|
|
The number of MMX instructions executed in the V pipe.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-mmx-multiply-unit-interlock
|
|
|
|
|
.Pq Event 38H , Tn Pentium MMX
|
|
|
|
|
The number of clocks the pipeline is stalled because the destination
|
|
|
|
|
of a prior MMX multiply is not ready.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-movd-movq-store-stall-due-to-previous-mmx-operation
|
|
|
|
|
.Pq Event 38H , Tn Pentium MMX
|
|
|
|
|
The number of clocks a MOVD/MOVQ instruction stalled in the D2 stage
|
|
|
|
|
of the pipeline due to a previous MMX instruction.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-noncacheable-memory-reads
|
|
|
|
|
.Pq Event 1EH
|
|
|
|
|
The number of bus cycles for non-cacheable instruction or data reads,
|
|
|
|
|
including cycles caused by TLB misses.
|
|
|
|
|
.It Li p5-number-of-cycles-not-in-halt-state
|
|
|
|
|
.Pq Event 30H , Tn Pentium MMX
|
|
|
|
|
The number of cycles the processor is not idle due to the HLT
|
|
|
|
|
instruction.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-pipeline-agi-stalls
|
|
|
|
|
.Pq Event 1FH
|
|
|
|
|
The number of address generation interlock stalls.
|
|
|
|
|
An AGI that occurs in both the U and V pipelines in the same clock
|
|
|
|
|
signals the event twice.
|
|
|
|
|
.It Li p5-pipeline-flushes
|
|
|
|
|
.Pq Event 15H
|
|
|
|
|
The number of pipeline flushes that occur.
|
|
|
|
|
Pipeline flushes are caused by branch mispredicts, exceptions,
|
|
|
|
|
interrupts, some segment register loads, and BTB misses.
|
|
|
|
|
Prefetch queue flushes due to serializing instructions are not
|
|
|
|
|
counted.
|
|
|
|
|
.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions
|
|
|
|
|
.Pq Event 35H , Tn Pentium MMX
|
|
|
|
|
The number of pipeline flushes due to wrong branch predictions
|
|
|
|
|
resolved in either the E- or WB- stage of the pipeline.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions-resolved-in-wb-stage
|
|
|
|
|
.Pq Event 35H , Tn Pentium MMX
|
|
|
|
|
The number of pipeline flushes due to wrong branch predictions
|
|
|
|
|
resolved in the stage of the pipeline.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-pipeline-stall-for-mmx-instruction-data-memory-reads
|
|
|
|
|
.Pq Event 36H , Tn Pentium MMX
|
|
|
|
|
The number of clocks during pipeline stalls caused by waiting MMX data
|
|
|
|
|
memory reads.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-predicted-returns
|
|
|
|
|
.Pq Event 37H , Tn Pentium MMX
|
|
|
|
|
The number of predicted returns, whether correct or incorrect.
|
|
|
|
|
This counter only counts RET instructions.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-returns
|
|
|
|
|
.Pq Event 39H , Tn Pentium MMX
|
|
|
|
|
The number of RET instructions executed.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-saturating-mmx-instructions-executed
|
|
|
|
|
.Pq Event 2FH , Tn Pentium MMX
|
|
|
|
|
The number of saturating MMX instructions executed.
|
|
|
|
|
This event is only allocated on counter 0.
|
|
|
|
|
.It Li p5-saturations-performed
|
|
|
|
|
.Pq Event 2FH , Tn Pentium MMX
|
|
|
|
|
The number of saturating MMX instructions executed when at least one
|
|
|
|
|
of its results were actually saturated.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-stall-on-mmx-instruction-write-to-e-o-m-state-line
|
|
|
|
|
.Pq Event 3BH , Tn Pentium MMX
|
|
|
|
|
The number of clocks during stalls on MMX instructions writing to
|
|
|
|
|
E- or M- state cache lines.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-stall-on-write-to-an-e-or-m-state-line
|
|
|
|
|
.Pq Event 1BH
|
|
|
|
|
The number of stalls on a write to an exclusive or modified data cache
|
|
|
|
|
line.
|
|
|
|
|
.It Li p5-taken-branch-or-btb-hit
|
|
|
|
|
.Pq Event 14H
|
|
|
|
|
The number of events that may cause a hit in the BTB, namely either
|
|
|
|
|
taken branches or BTB hits.
|
|
|
|
|
.It Li p5-taken-branches
|
|
|
|
|
.Pq Event 32H , Tn Pentium MMX
|
|
|
|
|
The number of taken branches.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-transitions-between-mmx-and-fp-instructions
|
|
|
|
|
.Pq Event 2DH , Tn Pentium MMX
|
|
|
|
|
The number of transitions between MMX and floating-point instructions
|
|
|
|
|
and vice-versa.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.It Li p5-waiting-for-data-memory-read-stall-duration
|
|
|
|
|
.Pq Event 1AH
|
|
|
|
|
The number of clocks the pipeline was stalled waiting for data
|
|
|
|
|
memory reads.
|
|
|
|
|
Data TLB misses processing is included in this count.
|
|
|
|
|
.It Li p5-write-buffer-full-stall-duration
|
|
|
|
|
.Pq Event 19H
|
|
|
|
|
The number of clocks while the pipeline was stalled due to write
|
|
|
|
|
buffers being full.
|
|
|
|
|
.It Li p5-write-hit-to-m-or-e-state-lines
|
|
|
|
|
.Pq Event 05H
|
|
|
|
|
The number of writes that hit exclusive or modified lines in the data
|
|
|
|
|
cache.
|
|
|
|
|
.It Li p5-writes-to-noncacheable-memory
|
|
|
|
|
.Pq Event 2EH , Tn Pentium MMX
|
|
|
|
|
The number of writes to non-cacheable memory, including write cycles
|
|
|
|
|
caused by TLB misses and I/O writes.
|
|
|
|
|
This event is only allocated on counter 1.
|
|
|
|
|
.El
|
|
|
|
|
.Ss Event Name Aliases
|
|
|
|
|
The following table shows the mapping between the PMC-independent
|
|
|
|
|
aliases supported by
|
|
|
|
|
.Lb libpmc
|
|
|
|
|
and the underlying hardware events used.
|
|
|
|
|
.Bl -column "branch-mispredicts" "Description"
|
|
|
|
|
.It Em Alias Ta Em Event
|
|
|
|
|
.It Li branches Ta Li p5-taken-branches
|
|
|
|
|
.It Li branch-mispredicts Ta Li (unsupported)
|
|
|
|
|
.It Li dc-misses Ta Li p5-data-read-miss-or-write-miss
|
|
|
|
|
.It Li ic-misses Ta Li p5-code-cache-miss
|
|
|
|
|
.It Li instructions Ta Li p5-instructions-executed
|
|
|
|
|
.It Li interrupts Ta Li p5-hardware-interrupts
|
|
|
|
|
.It Li unhalted-cycles Ta Li p5-number-of-cycles-not-in-halt-state
|
|
|
|
|
.El
|
|
|
|
|
.Sh SEE ALSO
|
|
|
|
|
.Xr pmc 3 ,
|
|
|
|
|
.Xr pmc.atom 3 ,
|
|
|
|
|
.Xr pmc.core 3 ,
|
|
|
|
|
.Xr pmc.core2 3 ,
|
|
|
|
|
.Xr pmc.iaf 3 ,
|
|
|
|
|
.Xr pmc.k7 3 ,
|
|
|
|
|
.Xr pmc.k8 3 ,
|
|
|
|
|
.Xr pmc.p4 3 ,
|
|
|
|
|
.Xr pmc.p6 3 ,
|
|
|
|
|
.Xr pmc.soft 3 ,
|
|
|
|
|
.Xr pmc.tsc 3 ,
|
|
|
|
|
.Xr pmclog 3 ,
|
|
|
|
|
.Xr hwpmc 4
|
|
|
|
|
.Sh HISTORY
|
|
|
|
|
The
|
|
|
|
|
.Nm pmc
|
|
|
|
|
library first appeared in
|
|
|
|
|
.Fx 6.0 .
|
|
|
|
|
.Sh AUTHORS
|
|
|
|
|
The
|
|
|
|
|
.Lb libpmc
|
|
|
|
|
library was written by
|
|
|
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
Mitchell Horne