Add support for AHCI compliant ATA devices.
For now just support the Intel ICH6 as that the HW at hand. Sponsored by: pair.com
This commit is contained in:
Søren Schmidt
parent
3ecc7feefc
commit
d81c813f10
@ -163,16 +163,98 @@
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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#define ATA_SACTIVE 16
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/* SATA AHCI v1.0 register defines */
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#define ATA_AHCI_CAP 0x00
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#define ATA_AHCI_NPMASK 0x1f
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#define ATA_AHCI_GHC 0x04
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#define ATA_AHCI_GHC_AE 0x80000000
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#define ATA_AHCI_GHC_IE 0x00000002
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#define ATA_AHCI_GHC_HR 0x80000001
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#define ATA_AHCI_IS 0x08
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#define ATA_AHCI_PI 0x0c
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#define ATA_AHCI_VS 0x10
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#define ATA_AHCI_OFFSET 0x80
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#define ATA_AHCI_P_CLB 0x100
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#define ATA_AHCI_P_CLBU 0x104
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#define ATA_AHCI_P_FB 0x108
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#define ATA_AHCI_P_FBU 0x10c
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#define ATA_AHCI_P_IS 0x110
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#define ATA_AHCI_P_IE 0x114
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#define ATA_AHCI_P_IX_DHR 0x00000001
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#define ATA_AHCI_P_IX_PS 0x00000002
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#define ATA_AHCI_P_IX_DS 0x00000004
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#define ATA_AHCI_P_IX_SDB 0x00000008
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#define ATA_AHCI_P_IX_UF 0x00000010
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#define ATA_AHCI_P_IX_DP 0x00000020
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#define ATA_AHCI_P_IX_PC 0x00000040
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#define ATA_AHCI_P_IX_DI 0x00000080
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#define ATA_AHCI_P_IX_PRC 0x00400000
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#define ATA_AHCI_P_IX_IPM 0x00800000
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#define ATA_AHCI_P_IX_OF 0x01000000
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#define ATA_AHCI_P_IX_INF 0x04000000
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#define ATA_AHCI_P_IX_IF 0x08000000
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#define ATA_AHCI_P_IX_HBD 0x10000000
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#define ATA_AHCI_P_IX_HBF 0x20000000
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#define ATA_AHCI_P_IX_TFE 0x40000000
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#define ATA_AHCI_P_IX_CPD 0x80000000
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#define ATA_AHCI_P_CMD 0x118
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#define ATA_AHCI_P_CMD_ST 0x00000001
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#define ATA_AHCI_P_CMD_SUD 0x00000002
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#define ATA_AHCI_P_CMD_POD 0x00000004
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#define ATA_AHCI_P_CMD_CLO 0x00000008
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#define ATA_AHCI_P_CMD_FRE 0x00000010
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#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
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#define ATA_AHCI_P_CMD_ISS 0x00002000
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#define ATA_AHCI_P_CMD_FR 0x00004000
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#define ATA_AHCI_P_CMD_CR 0x00008000
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#define ATA_AHCI_P_CMD_CPS 0x00010000
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#define ATA_AHCI_P_CMD_PMA 0x00020000
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#define ATA_AHCI_P_CMD_HPCP 0x00040000
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#define ATA_AHCI_P_CMD_ISP 0x00080000
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#define ATA_AHCI_P_CMD_CPD 0x00100000
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#define ATA_AHCI_P_CMD_ATAPI 0x01000000
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#define ATA_AHCI_P_CMD_DLAE 0x02000000
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#define ATA_AHCI_P_CMD_ALPE 0x04000000
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#define ATA_AHCI_P_CMD_ASP 0x08000000
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#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
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#define ATA_AHCI_P_CMD_NOOP 0x00000000
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#define ATA_AHCI_P_CMD_ACTIVE 0x10000000
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#define ATA_AHCI_P_CMD_PARTIAL 0x20000000
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#define ATA_AHCI_P_CMD_SLUMPER 0x60000000
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#define ATA_AHCI_P_TFD 0x120
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#define ATA_AHCI_P_SIG 0x124
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#define ATA_AHCI_P_SSTS 0x128
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#define ATA_AHCI_P_SCTL 0x12c
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#define ATA_AHCI_P_SERR 0x130
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#define ATA_AHCI_P_SACT 0x134
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#define ATA_AHCI_P_CI 0x138
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#define ATA_AHCI_CL_SIZE 32
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#define ATA_AHCI_CL_OFFSET 0
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#define ATA_AHCI_FB_OFFSET 1024
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#define ATA_AHCI_CT_OFFSET 1024+256
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#define ATA_AHCI_CT_SG_OFFSET 128
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#define ATA_AHCI_CT_SIZE 256
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/* DMA register defines */
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#define ATA_DMA_ENTRIES 256
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#define ATA_DMA_EOT 0x80000000
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#define ATA_BMCMD_PORT 16
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#define ATA_BMCMD_PORT 17
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#define ATA_BMCMD_START_STOP 0x01
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#define ATA_BMCMD_WRITE_READ 0x08
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#define ATA_BMDEVSPEC_0 17
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#define ATA_BMSTAT_PORT 18
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#define ATA_BMDEVSPEC_0 18
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#define ATA_BMSTAT_PORT 19
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#define ATA_BMSTAT_ACTIVE 0x01
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#define ATA_BMSTAT_ERROR 0x02
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#define ATA_BMSTAT_INTERRUPT 0x04
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@ -181,12 +263,12 @@
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#define ATA_BMSTAT_DMA_SLAVE 0x40
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#define ATA_BMSTAT_DMA_SIMPLEX 0x80
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#define ATA_BMDEVSPEC_1 19
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#define ATA_BMDTP_PORT 20
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#define ATA_BMDEVSPEC_1 20
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#define ATA_BMDTP_PORT 21
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#define ATA_IDX_ADDR 21
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#define ATA_IDX_DATA 22
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#define ATA_MAX_RES 23
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#define ATA_IDX_ADDR 22
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#define ATA_IDX_DATA 23
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#define ATA_MAX_RES 24
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/* misc defines */
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#define ATA_PRIMARY 0x1f0
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@ -56,6 +56,11 @@ __FBSDID("$FreeBSD$");
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static int ata_generic_chipinit(device_t);
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static void ata_generic_intr(void *);
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static void ata_generic_setmode(device_t, int);
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static int ata_ahci_allocate(device_t dev);
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static int ata_ahci_begin_transaction(struct ata_request *);
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static int ata_ahci_end_transaction(struct ata_request *);
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static void ata_ahci_intr(void *);
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static void ata_ahci_reset(device_t);
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static int ata_acard_chipinit(device_t);
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static void ata_acard_intr(void *);
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static void ata_acard_850_setmode(device_t, int);
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@ -243,17 +248,16 @@ ata_sata_connect(struct ata_channel *ch)
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else
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break;
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}
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if (1 | bootverbose)
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if (bootverbose)
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device_printf(ch->dev, "SATA connect ready time=%dms\n", timeout * 10);
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if (timeout < 1000) {
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if ((ATA_IDX_INB(ch, ATA_CYL_LSB) == ATAPI_MAGIC_LSB) &&
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(ATA_IDX_INB(ch, ATA_CYL_MSB) == ATAPI_MAGIC_MSB))
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ch->devices = ATA_ATAPI_MASTER;
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else /*if ((ATA_IDX_INB(ch, ATA_COUNT) == 0x01) &&
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(ATA_IDX_INB(ch, ATA_CYL_LSB) == 0x01)) */
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else
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ch->devices = ATA_ATA_MASTER;
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}
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if (1 | bootverbose)
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if (bootverbose)
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device_printf(ch->dev, "sata_connect devices=0x%b\n",
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ch->devices, "\20\3ATAPI_MASTER\1ATA_MASTER");
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return 1;
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@ -318,6 +322,337 @@ ata_sata_phy_event(void *context, int dummy)
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}
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/*
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* AHCI v1.0 compliant SATA chipset support functions
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*/
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struct ata_ahci_dma_prd {
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u_int64_t dba;
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u_int32_t reserved;
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u_int32_t dbc; /* 0 based */
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#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
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#define ATA_AHCI_PRD_IPC (1<<31)
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} __packed;
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struct ata_ahci_cmd_tab {
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u_int8_t cfis[64];
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u_int8_t acmd[32];
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u_int8_t reserved[32];
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struct ata_ahci_dma_prd prd_tab[16];
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} __packed;
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struct ata_ahci_cmd_list {
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u_int16_t cmd_flags;
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u_int16_t prd_length; /* PRD entries */
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u_int32_t bytecount;
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u_int64_t cmd_table_phys; /* 128byte aligned */
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} __packed;
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static int
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ata_ahci_allocate(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = (ch->unit << 7);
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/* XXX SOS this is a hack to satisfy various legacy cruft */
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ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2;
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ch->r_io[ATA_CYL_LSB].offset = ATA_AHCI_P_SIG + 1 + offset;
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ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2;
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ch->r_io[ATA_CYL_MSB].offset = ATA_AHCI_P_SIG + 3 + offset;
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ch->r_io[ATA_STATUS].res = ctlr->r_res2;
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ch->r_io[ATA_STATUS].offset = ATA_AHCI_P_TFD + offset;
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ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
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ch->r_io[ATA_ALTSTAT].offset = ATA_AHCI_P_TFD + offset;
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/* set the SATA resources */
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
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ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
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ch->r_io[ATA_SERROR].res = ctlr->r_res2;
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ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
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ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
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ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
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ch->hw.begin_transaction = ata_ahci_begin_transaction;
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ch->hw.end_transaction = ata_ahci_end_transaction;
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ch->hw.command = NULL; /* not used here */
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/* setup the work areas */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset,
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ch->dma->work_bus + ATA_AHCI_CL_OFFSET);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset,
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ch->dma->work_bus + ATA_AHCI_FB_OFFSET);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000);
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/* enable wanted port interrupts */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
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(ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
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ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
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ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
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ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
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ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
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/* start operations on this channel */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
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(ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
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ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
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return 0;
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}
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static int
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ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request)
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{
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struct ata_device *atadev = device_get_softc(request->dev);
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int idx = 0;
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/* XXX SOS add ATAPI commands support later */
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fis[idx++] = 0x27; /* host to device */
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fis[idx++] = 0x80; /* command FIS (note PM goes here) */
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fis[idx++] = ata_modify_if_48bit(request);
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fis[idx++] = request->u.ata.feature;
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fis[idx++] = request->u.ata.lba;
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fis[idx++] = request->u.ata.lba >> 8;
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fis[idx++] = request->u.ata.lba >> 16;
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fis[idx++] = ATA_D_LBA | atadev->unit;
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fis[idx++] = request->u.ata.lba >> 24;
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fis[idx++] = request->u.ata.lba >> 32;
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fis[idx++] = request->u.ata.lba >> 40;
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fis[idx++] = request->u.ata.feature >> 8;
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fis[idx++] = request->u.ata.count;
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fis[idx++] = request->u.ata.count >> 8;
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fis[idx++] = 0x00;
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fis[idx++] = ATA_A_4BIT;
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fis[idx++] = 0x00;
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fis[idx++] = 0x00;
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fis[idx++] = 0x00;
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fis[idx++] = 0x00;
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return idx;
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}
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/* must be called with ATA channel locked and state_mtx held */
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static int
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ata_ahci_begin_transaction(struct ata_request *request)
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{
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struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
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struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
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struct ata_ahci_cmd_tab *ctp;
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struct ata_ahci_cmd_list *clp;
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int fis_size, entries;
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int tag = 0;
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/* get a piece of the workspace for this request */
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ctp = (struct ata_ahci_cmd_tab *)
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(ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
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/* setup the FIS for this request */ /* XXX SOS ATAPI missing still */
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if (!(fis_size = ata_ahci_setup_fis(&ctp->cfis[0], request))) {
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device_printf(request->dev, "setting up SATA FIS failed\n");
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request->result = EIO;
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return ATA_OP_FINISHED;
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}
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/* if request moves data setup and load SG list */
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if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
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if (ch->dma->load(ch->dev, request->data, request->bytecount,
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request->flags & ATA_R_READ,
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ctp->prd_tab, &entries)) {
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device_printf(request->dev, "setting up DMA failed\n");
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request->result = EIO;
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return ATA_OP_FINISHED;
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}
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}
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/* setup the command list entry */
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clp = (struct ata_ahci_cmd_list *)
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(ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
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clp->prd_length = entries;
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clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
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(request->flags & ATA_R_ATAPI ? (1<<5) : 0) |
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(fis_size / sizeof(u_int32_t));
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clp->bytecount = 0;
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clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
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(ATA_AHCI_CT_SIZE * tag));
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/* clear eventual ACTIVE bit */
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ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
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/* issue the command */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + (ch->unit << 7), (1 << tag));
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/* start the timeout */
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callout_reset(&request->callout, request->timeout * hz,
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(timeout_t*)ata_timeout, request);
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return ATA_OP_CONTINUES;
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}
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/* must be called with ATA channel locked and state_mtx held */
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static int
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ata_ahci_end_transaction(struct ata_request *request)
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{
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struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
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struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
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struct ata_ahci_cmd_list *clp;
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u_int32_t tf_data;
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int tag = 0;
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/* kill the timeout */
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callout_stop(&request->callout);
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/* get status */
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tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit << 7));
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request->status = tf_data;
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/* if error status get details */
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if (request->status & ATA_S_ERROR)
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request->error = tf_data >> 8;
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/* record how much data we actually moved */
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clp = (struct ata_ahci_cmd_list *)
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(ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
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request->donecount = clp->bytecount;
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/* release SG list etc */
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ch->dma->unload(ch->dev);
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return ATA_OP_FINISHED;
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}
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static void
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ata_ahci_intr(void *data)
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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u_int32_t port, status, error, issued;
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int unit;
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int tag = 0;
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port = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < ctlr->channels; unit++) {
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if (port & (1 << unit)) {
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if ((ch = ctlr->interrupt[unit].argument)) {
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struct ata_connect_task *tp;
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int offset = (ch->unit << 7);
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error = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SERR + offset);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_SERR + offset, error);
|
||||
status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, status);
|
||||
issued = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
|
||||
|
||||
/* do we have cold connect surprise */
|
||||
if (status & ATA_AHCI_P_IX_CPD) {
|
||||
printf("ata_ahci_intr status=%08x error=%08x issued=%08x\n",
|
||||
status, error, issued);
|
||||
}
|
||||
|
||||
/* check for and handle connect events */
|
||||
if ((status & ATA_AHCI_P_IX_PC) &&
|
||||
(tp = (struct ata_connect_task *)
|
||||
malloc(sizeof(struct ata_connect_task),
|
||||
M_ATA, M_NOWAIT | M_ZERO))) {
|
||||
|
||||
device_printf(ch->dev, "CONNECT requested\n");
|
||||
tp->action = ATA_C_ATTACH;
|
||||
tp->dev = ch->dev;
|
||||
TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
|
||||
taskqueue_enqueue(taskqueue_thread, &tp->task);
|
||||
}
|
||||
|
||||
/* check for and handle disconnect events */
|
||||
if (((status & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC)) ==
|
||||
ATA_AHCI_P_IX_PRC) &&
|
||||
(tp = (struct ata_connect_task *)
|
||||
malloc(sizeof(struct ata_connect_task),
|
||||
M_ATA, M_NOWAIT | M_ZERO))) {
|
||||
|
||||
device_printf(ch->dev, "DISCONNECT requested\n");
|
||||
tp->action = ATA_C_DETACH;
|
||||
tp->dev = ch->dev;
|
||||
TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
|
||||
taskqueue_enqueue(taskqueue_thread, &tp->task);
|
||||
}
|
||||
|
||||
/* any drive action to take care of ? */
|
||||
if (!(issued & (1<<tag)))
|
||||
ctlr->interrupt[unit].function(ch);
|
||||
}
|
||||
}
|
||||
}
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, port);
|
||||
}
|
||||
|
||||
static void
|
||||
ata_ahci_reset(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
|
||||
struct ata_channel *ch = device_get_softc(dev);
|
||||
u_int32_t cmd;
|
||||
int offset = (ch->unit << 7);
|
||||
|
||||
/* kill off all activity on this channel */
|
||||
cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
|
||||
cmd & ~(ATA_AHCI_P_CMD_CR | ATA_AHCI_P_CMD_FR |
|
||||
ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
|
||||
|
||||
DELAY(500000); /* XXX SOS */
|
||||
|
||||
/* spin up device */
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD);
|
||||
|
||||
ata_sata_phy_enable(ch);
|
||||
|
||||
/* clear any interrupts pending on this channel */
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
|
||||
ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
|
||||
|
||||
/* start operations on this channel */
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
|
||||
(ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
|
||||
ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
|
||||
}
|
||||
|
||||
static void
|
||||
ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
|
||||
{
|
||||
struct ata_dmasetprd_args *args = xsc;
|
||||
struct ata_ahci_dma_prd *prd = args->dmatab;
|
||||
int i;
|
||||
|
||||
if (!(args->error = error)) {
|
||||
for (i = 0; i < nsegs; i++) {
|
||||
prd[i].dba = htole64(segs[i].ds_addr);
|
||||
prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
|
||||
}
|
||||
}
|
||||
args->nsegs = nsegs;
|
||||
}
|
||||
|
||||
static void
|
||||
ata_ahci_dmainit(device_t dev)
|
||||
{
|
||||
struct ata_channel *ch = device_get_softc(dev);
|
||||
|
||||
ata_dmainit(dev);
|
||||
if (ch->dma) {
|
||||
/* note start and stop are not used here */
|
||||
ch->dma->setprd = ata_ahci_dmasetprd;
|
||||
ch->dma->max_iosize = 8192 * DEV_BSIZE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Acard chipset support functions
|
||||
*/
|
||||
@ -1083,10 +1418,42 @@ ata_intel_chipinit(device_t dev)
|
||||
ctlr->setmode = ata_intel_new_setmode;
|
||||
}
|
||||
else {
|
||||
/* if we have BAR(5) as a memory resource we should use AHCI mode */
|
||||
ctlr->r_type2 = SYS_RES_MEMORY;
|
||||
ctlr->r_rid2 = PCIR_BAR(5);
|
||||
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
|
||||
&ctlr->r_rid2, RF_ACTIVE))) {
|
||||
if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
|
||||
bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
|
||||
ata_ahci_intr, ctlr, &ctlr->handle)) {
|
||||
device_printf(dev, "unable to setup interrupt\n");
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
/* force all ports active "the legacy way" */
|
||||
pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
|
||||
|
||||
/* enable AHCI mode */
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
|
||||
|
||||
/* get the number of HW channels */
|
||||
ctlr->channels = (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) &
|
||||
ATA_AHCI_NPMASK) + 1;
|
||||
|
||||
/* enable AHCI interrupts */
|
||||
ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
|
||||
ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
|
||||
|
||||
ctlr->reset = ata_ahci_reset;
|
||||
ctlr->dmainit = ata_ahci_dmainit;
|
||||
ctlr->allocate = ata_ahci_allocate;
|
||||
}
|
||||
else {
|
||||
ctlr->reset = ata_intel_reset;
|
||||
}
|
||||
ctlr->setmode = ata_sata_setmode;
|
||||
pci_write_config(dev, PCIR_COMMAND,
|
||||
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
|
||||
ctlr->reset = ata_intel_reset;
|
||||
ctlr->setmode = ata_sata_setmode;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user