Properly handle case where firmware dump returns more registers on second pass
in mlx5core. Submitted by: kib@ MFC after: 1 week Sponsored by: Mellanox Technologies // NVIDIA Networking
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@ -115,11 +115,15 @@ mlx5_fwdump_prep(struct mlx5_core_dev *mdev)
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mlx5_core_warn(mdev, "no output from scan space\n");
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goto unlock_vsc;
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}
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mdev->dump_rege = malloc(sz * sizeof(struct mlx5_crspace_regmap),
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/*
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* We add a sentinel element at the end of the array to
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* terminate the read loop in mlx5_fwdump(), so allocate sz + 1.
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*/
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mdev->dump_rege = malloc((sz + 1) * sizeof(struct mlx5_crspace_regmap),
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M_MLX5_DUMP, M_WAITOK | M_ZERO);
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for (i = 0, addr = 0;;) {
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MPASS(i < sz);
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mdev->dump_rege[i].cnt++;
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MLX5_VSC_SET(vsc_addr, &in, address, addr);
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pci_write_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, in, 4);
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@ -137,13 +141,21 @@ mlx5_fwdump_prep(struct mlx5_core_dev *mdev)
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next_addr = MLX5_VSC_GET(vsc_addr, &out, address);
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if (next_addr == 0 || next_addr == addr)
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break;
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if (next_addr != addr + 4)
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mdev->dump_rege[++i].addr = next_addr;
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if (next_addr != addr + 4) {
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if (++i == sz) {
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mlx5_core_err(mdev,
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"Inconsistent hw crspace reads (1): sz %u i %u addr %#lx",
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sz, i, (unsigned long)addr);
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break;
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}
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mdev->dump_rege[i].addr = next_addr;
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}
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addr = next_addr;
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}
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if (i + 1 != sz) {
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/* i == sz case already reported by loop above */
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if (i + 1 != sz && i != sz) {
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mlx5_core_err(mdev,
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"Inconsistent hw crspace reads: sz %u i %u addr %#lx",
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"Inconsistent hw crspace reads (2): sz %u i %u addr %#lx",
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sz, i, (unsigned long)addr);
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}
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