diff --git a/sys/ia64/include/vmparam.h b/sys/ia64/include/vmparam.h
index edf5710fcd8f..98dfdda42af3 100644
--- a/sys/ia64/include/vmparam.h
+++ b/sys/ia64/include/vmparam.h
@@ -45,7 +45,7 @@
  * USRSTACK is the top (end) of the user stack.  Immediately above the user
  * stack resides the syscall gateway page.
  */
-#define	USRSTACK	VM_MAX_ADDRESS
+#define	USRSTACK	VM_MAXUSER_ADDRESS
 
 /*
  * Virtual memory related constants, all in bytes
@@ -128,7 +128,8 @@
 #define IA64_RR_BASE(n)         (((uint64_t) (n)) << 61)
 #define IA64_RR_MASK(x)         ((x) & ((1L << 61) - 1))
 
-#define IA64_PHYS_TO_RR7(x)     ((x) | IA64_RR_BASE(7))
+#define	IA64_PHYS_TO_RR6(x)	((x) | IA64_RR_BASE(6))
+#define	IA64_PHYS_TO_RR7(x)	((x) | IA64_RR_BASE(7))
 
 /*
  * Page size of the identity mappings in region 7.
@@ -141,21 +142,68 @@
 #define	IA64_ID_PAGE_SIZE	(1<<(LOG2_ID_PAGE_SIZE))
 #define	IA64_ID_PAGE_MASK	(IA64_ID_PAGE_SIZE-1)
 
-#define	IA64_BACKINGSTORE	IA64_RR_BASE(4)
+/*
+ * The Itanium architecture defines that all implementations support at
+ * least 51 virtual address bits (i.e. IMPL_VA_MSB=50). The unimplemented
+ * bits are sign-extended from VA{IMPL_VA_MSB}. As such, there's a gap in
+ * the virtual address range, which extends at most from 0x0004000000000000
+ * to 0x1ffbffffffffffff. We define the top half of a region in terms of
+ * this worst-case gap.
+ */
+#define	IA64_REGION_TOP_HALF	0x1ffc000000000000
+
+/* Place the backing store in the top of half if region 0. */
+#define	IA64_BACKINGSTORE	IA64_REGION_TOP_HALF
+
+/*
+ * Parameters for Pre-Boot Virtual Memory (PBVM).
+ * The kernel, its modules and metadata are loaded in the PBVM by the loader.
+ * The PBVM consists of pages for which the mapping is maintained in a page
+ * table. The page table is at least 1 EFI page large (i.e. 4KB), but can be
+ * larger to accommodate more PBVM. The maximum page table size is 1MB. With
+ * 8 bytes per page table entry, this means that the PBVM has at least 512
+ * pages and at most 128K pages.
+ * The GNU toolchain (in particular GNU ld) does not support an alignment
+ * larger than 64K. This means that we cannot guarantee page alignment for
+ * a page size that's larger than 64K. We do want to have text and data in
+ * different pages, which means that the maximum usable page size is 64KB.
+ * Consequently:
+ * The maximum total PBVM size is 8GB -- enough for a DVD image. A page table
+ * of a single EFI page (4KB) allows for 32MB of PBVM.
+ *
+ * The kernel is given the PA and size of the page table that provides the
+ * mapping of the PBVM. The page table itself is assumed to be mapped at a
+ * known virtual address and using a single translation wired into the CPU.
+ * As such, the page table is assumed to be a power of 2 and naturally aligned.
+ * The kernel also assumes that a good portion of the kernel text is mapped
+ * and wired into the CPU, but does not assume that the mapping covers the
+ * whole of PBVM.
+ */
+#define	IA64_PBVM_RR		4
+#define	IA64_PBVM_BASE		\
+		(IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_TOP_HALF)
+
+#define	IA64_PBVM_PGTBL_MAXSZ	1048576
+#define	IA64_PBVM_PGTBL		\
+		(IA64_RR_BASE(IA64_PBVM_RR + 1) - IA64_PBVM_PGTBL_MAXSZ)
+
+#define	IA64_PBVM_PAGE_SHIFT	16	/* 64KB */
+#define	IA64_PBVM_PAGE_SIZE	(1U << IA64_PBVM_PAGE_SHIFT)
+#define	IA64_PBVM_PAGE_MASK	(IA64_PBVM_PAGE_SIZE - 1)
 
 /*
  * Mach derived constants
  */
 
 /* user/kernel map constants */
-#define VM_MIN_ADDRESS		0
-#define	VM_MAX_ADDRESS		IA64_RR_BASE(5)
+#define	VM_MIN_ADDRESS		0
+#define	VM_MAXUSER_ADDRESS	IA64_RR_BASE(IA64_PBVM_RR)
+#define	VM_MAX_ADDRESS		VM_MAXUSER_ADDRESS	/* XXX */
 #define	VM_GATEWAY_SIZE		PAGE_SIZE
-#define	VM_MAXUSER_ADDRESS	(VM_MAX_ADDRESS + VM_GATEWAY_SIZE)
-#define	VM_MIN_KERNEL_ADDRESS	VM_MAXUSER_ADDRESS
-#define VM_MAX_KERNEL_ADDRESS	(IA64_RR_BASE(6) - 1)
+#define	VM_MIN_KERNEL_ADDRESS	IA64_RR_BASE(5)
+#define	VM_MAX_KERNEL_ADDRESS	(IA64_RR_BASE(6) - 1)
 
-#define	KERNBASE		VM_MAX_ADDRESS
+#define	KERNBASE		VM_MAXUSER_ADDRESS
 
 /* virtual sizes (bytes) for various kernel submaps */
 #ifndef VM_KMEM_SIZE