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- Initial release of bxe(4) to support Broadcom NetXtreme II 10GbE.

Browse Source 
(BCM57710, BCM57711, BCM57711E)

MFC after:	One month
This commit is contained in:
David Christensen 2011-03-14 22:42:41 +00:00
parent 856e88c1f5
commit dd46ab31de
25 changed files with 107849 additions and 0 deletions
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1
MAINTAINERS
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@ -47,6 +47,7 @@ cd(4) ken Pre-commit review requested.
pass(4) ken Pre-commit review requested.
ch(4) ken Pre-commit review requested.
em(4) jfv Pre-commit review requested.
bxe(4) davidch Pre-commit review requested.
tdfx(4) cokane Just keep me informed of changes, try not to break it.
sendmail gshapiro Pre-commit review requested.
etc/mail gshapiro Pre-commit review requested.

1
sys/amd64/conf/GENERIC
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@ -193,6 +193,7 @@ device ppi # Parallel port interface device
#device puc
# PCI Ethernet NICs.
device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel PRO/1000 Gigabit Ethernet Family
device igb # Intel PRO/1000 PCIE Server Gigabit Family

1
sys/boot/forth/loader.conf
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@ -268,6 +268,7 @@ if_bge_load="NO" # Broadcom BCM570x PCI Gigabit Ethernet
if_bridge_load="NO" # if_bridge(4) devices
if_bwi_load="NO" # Broadcom BCM53xx IEEE 802.11b/g wireness NICs
if_bwn_load="NO" # Broadcom BCM43xx IEEE 802.11 wireless NICs
if_bxe_load="NO" # Broadcom NetXtreme II 10Gb Ethernet
if_carp_load="NO" # carp(4) devices
if_cas_load="NO" # Sun Cassini/Cassini+ and NS DP83065 Saturn
if_cm_load="NO" # SMC (90c26, 90c56, 90c66)

3
sys/conf/NOTES
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@ -1900,6 +1900,8 @@ device xmphy # XaQti XMAC II
# BCM570x family of controllers, including the 3Com 3c996-T,
# the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41, and
# the embedded gigE NICs on Dell PowerEdge 2550 servers.
# bxe: Broadcom NetXtreme II (BCM57710/57711/57711E) PCIe 10b Ethernet
# adapters.
# bwi: Broadcom BCM430* and BCM431* family of wireless adapters.
# bwn: Broadcom BCM43xx family of wireless adapters.
# cas: Sun Cassini/Cassini+ and National Semiconductor DP83065 Saturn
@ -2078,6 +2080,7 @@ device wb # Winbond W89C840F
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
# PCI Ethernet NICs.
device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
device cxgbe # Chelsio T4 10GbE PCIe adapter
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel Pro/1000 Gigabit Ethernet

2
sys/conf/files
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@ -819,6 +819,8 @@ dev/bwi/bwirf.c optional bwi
dev/bwi/if_bwi.c optional bwi
dev/bwi/if_bwi_pci.c optional bwi pci
dev/bwn/if_bwn.c optional bwn siba_bwn
dev/bxe/if_bxe.c optional bxe
dev/bxe/bxe_link.c optional bxe
dev/cardbus/cardbus.c optional cardbus
dev/cardbus/cardbus_cis.c optional cardbus
dev/cardbus/cardbus_device.c optional cardbus

5
sys/conf/options
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@ -702,8 +702,13 @@ ED_SIC opt_ed.h
BCE_DEBUG opt_bce.h
BCE_NVRAM_WRITE_SUPPORT opt_bce.h
# bxe driver
BXE_DEBUG opt_bxe.h
BXE_NVRAM_WRITE_SUPPORT opt_bxe.h
SOCKBUF_DEBUG opt_global.h
# options for ubsec driver
UBSEC_DEBUG opt_ubsec.h
UBSEC_RNDTEST opt_ubsec.h

357
sys/dev/bxe/bxe_debug.h Executable file
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@ -0,0 +1,357 @@
/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _BXE_DEBUG_H
#define _BXE_DEBUG_H
extern uint32_t bxe_debug;
/*
* Debugging macros and definitions.
*/
#define BXE_CP_LOAD 0x00000001
#define BXE_CP_SEND 0x00000002
#define BXE_CP_RECV 0x00000004
#define BXE_CP_INTR 0x00000008
#define BXE_CP_UNLOAD 0x00000010
#define BXE_CP_RESET 0x00000020
#define BXE_CP_IOCTL 0x00000040
#define BXE_CP_STATS 0x00000080
#define BXE_CP_MISC 0x00000100
#define BXE_CP_PHY 0x00000200
#define BXE_CP_RAMROD 0x00000400
#define BXE_CP_NVRAM 0x00000800
#define BXE_CP_REGS 0x00001000
#define BXE_CP_ALL 0x00FFFFFF
#define BXE_CP_MASK 0x00FFFFFF
#define BXE_LEVEL_FATAL 0x00000000
#define BXE_LEVEL_WARN 0x01000000
#define BXE_LEVEL_INFO 0x02000000
#define BXE_LEVEL_VERBOSE 0x03000000
#define BXE_LEVEL_EXTREME 0x04000000
#define BXE_LEVEL_INSANE 0x05000000
#define BXE_LEVEL_MASK 0xFF000000
#define BXE_WARN_LOAD (BXE_CP_LOAD | BXE_LEVEL_WARN)
#define BXE_INFO_LOAD (BXE_CP_LOAD | BXE_LEVEL_INFO)
#define BXE_VERBOSE_LOAD (BXE_CP_LOAD | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_LOAD (BXE_CP_LOAD | BXE_LEVEL_EXTREME)
#define BXE_INSANE_LOAD (BXE_CP_LOAD | BXE_LEVEL_INSANE)
#define BXE_WARN_SEND (BXE_CP_SEND | BXE_LEVEL_WARN)
#define BXE_INFO_SEND (BXE_CP_SEND | BXE_LEVEL_INFO)
#define BXE_VERBOSE_SEND (BXE_CP_SEND | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_SEND (BXE_CP_SEND | BXE_LEVEL_EXTREME)
#define BXE_INSANE_SEND (BXE_CP_SEND | BXE_LEVEL_INSANE)
#define BXE_WARN_RECV (BXE_CP_RECV | BXE_LEVEL_WARN)
#define BXE_INFO_RECV (BXE_CP_RECV | BXE_LEVEL_INFO)
#define BXE_VERBOSE_RECV (BXE_CP_RECV | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_RECV (BXE_CP_RECV | BXE_LEVEL_EXTREME)
#define BXE_INSANE_RECV (BXE_CP_RECV | BXE_LEVEL_INSANE)
#define BXE_WARN_INTR (BXE_CP_INTR | BXE_LEVEL_WARN)
#define BXE_INFO_INTR (BXE_CP_INTR | BXE_LEVEL_INFO)
#define BXE_VERBOSE_INTR (BXE_CP_INTR | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_INTR (BXE_CP_INTR | BXE_LEVEL_EXTREME)
#define BXE_INSANE_INTR (BXE_CP_INTR | BXE_LEVEL_INSANE)
#define BXE_WARN_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_WARN)
#define BXE_INFO_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_INFO)
#define BXE_VERBOSE_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_EXTREME)
#define BXE_INSANE_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_INSANE)
#define BXE_WARN_RESET (BXE_CP_RESET | BXE_LEVEL_WARN)
#define BXE_INFO_RESET (BXE_CP_RESET | BXE_LEVEL_INFO)
#define BXE_VERBOSE_RESET (BXE_CP_RESET | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_RESET (BXE_CP_RESET | BXE_LEVEL_EXTREME)
#define BXE_INSANE_RESET (BXE_CP_RESET | BXE_LEVEL_INSANE)
#define BXE_WARN_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_WARN)
#define BXE_INFO_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_INFO)
#define BXE_VERBOSE_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_EXTREME)
#define BXE_INSANE_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_INSANE)
#define BXE_WARN_STATS (BXE_CP_STATS | BXE_LEVEL_WARN)
#define BXE_INFO_STATS (BXE_CP_STATS | BXE_LEVEL_INFO)
#define BXE_VERBOSE_STATS (BXE_CP_STATS | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_STATS (BXE_CP_STATS | BXE_LEVEL_EXTREME)
#define BXE_INSANE_STATS (BXE_CP_STATS | BXE_LEVEL_INSANE)
#define BXE_WARN_MISC (BXE_CP_MISC | BXE_LEVEL_WARN)
#define BXE_INFO_MISC (BXE_CP_MISC | BXE_LEVEL_INFO)
#define BXE_VERBOSE_MISC (BXE_CP_MISC | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_MISC (BXE_CP_MISC | BXE_LEVEL_EXTREME)
#define BXE_INSANE_MISC (BXE_CP_MISC | BXE_LEVEL_INSANE)
#define BXE_WARN_PHY (BXE_CP_PHY | BXE_LEVEL_WARN)
#define BXE_INFO_PHY (BXE_CP_PHY | BXE_LEVEL_INFO)
#define BXE_VERBOSE_PHY (BXE_CP_PHY | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_PHY (BXE_CP_PHY | BXE_LEVEL_EXTREME)
#define BXE_INSANE_PHY (BXE_CP_PHY | BXE_LEVEL_INSANE)
#define BXE_WARN_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_WARN)
#define BXE_INFO_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_INFO)
#define BXE_VERBOSE_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_EXTREME)
#define BXE_INSANE_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_INSANE)
#define BXE_WARN_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_WARN)
#define BXE_INFO_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_INFO)
#define BXE_VERBOSE_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_EXTREME)
#define BXE_INSANE_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_INSANE)
#define BXE_WARN_REGS (BXE_CP_REGS | BXE_LEVEL_WARN)
#define BXE_INFO_REGS (BXE_CP_REGS | BXE_LEVEL_INFO)
#define BXE_VERBOSE_REGS (BXE_CP_REGS | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME_REGS (BXE_CP_REGS | BXE_LEVEL_EXTREME)
#define BXE_INSANE_REGS (BXE_CP_REGS | BXE_LEVEL_INSANE)
#define BXE_FATAL (BXE_CP_ALL | BXE_LEVEL_FATAL)
#define BXE_WARN (BXE_CP_ALL | BXE_LEVEL_WARN)
#define BXE_INFO (BXE_CP_ALL | BXE_LEVEL_INFO)
#define BXE_VERBOSE (BXE_CP_ALL | BXE_LEVEL_VERBOSE)
#define BXE_EXTREME (BXE_CP_ALL | BXE_LEVEL_EXTREME)
#define BXE_INSANE (BXE_CP_ALL | BXE_LEVEL_INSANE)
#define BXE_CODE_PATH(cp) ((cp & BXE_CP_MASK) & bxe_debug)
#define BXE_MSG_LEVEL(lv) ((lv & BXE_LEVEL_MASK) <= (bxe_debug & BXE_LEVEL_MASK))
#define BXE_LOG_MSG(m) (BXE_CODE_PATH(m) && BXE_MSG_LEVEL(m))
#ifdef BXE_DEBUG
/* Print a message based on the logging level and code path. */
#define DBPRINT(sc, level, format, args...) \
do { \
if (BXE_LOG_MSG(level)) { \
device_printf(sc->bxe_dev, format, ## args); \
} \
} while (0)
/* Runs a particular command when debugging is enabled. */
#define DBRUN(args...) \
do { \
args; \
} while (0)
/* Runs a particular command based on the logging level. */
#define DBRUNLV(level, args...) \
if (BXE_MSG_LEVEL(level)) { \
args; \
}
/* Runs a particular command based on the code path. */
#define DBRUNCP(cp, args...) \
if (BXE_CODE_PATH(cp)) { \
args; \
}
/* Runs a particular command based on a condition. */
#define DBRUNIF(cond, args...) \
if (cond) { \
args; \
}
/* Runs a particular command based on the logging level and code path. */
#define DBRUNMSG(msg, args...) \
if (BXE_LOG_MSG(msg)) { \
args; \
}
/* Announces function entry. */
#define DBENTER(cond) \
DBPRINT(sc, (cond), "%s(enter:%d)\n", __FUNCTION__, curcpu) \
/* Announces function exit. */
#define DBEXIT(cond) \
DBPRINT(sc, (cond), "%s(exit:%d)\n", __FUNCTION__, curcpu) \
/* Needed for random() function which is only used in debugging. */
#include <sys/random.h>
/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
#define DB_RANDOMFALSE(defects) (random() > defects)
#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
#define DB_RANDOMTRUE(defects) (random() < defects)
#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
#else
#define DBPRINT(...)
#define DBRUN(...)
#define DBRUNLV(...)
#define DBRUNCP(...)
#define DBRUNIF(...)
#define DBRUNMSG(...)
#define DBENTER(...)
#define DBENTER_UNLOCKED(...)
#define DBEXIT(...)
#define DBEXIT_UNLOCKED(...)
#define DB_RANDOMFALSE(...)
#define DB_OR_RANDOMFALSE(...)
#define DB_AND_RANDOMFALSE(...)
#define DB_RANDOMTRUE(...)
#define DB_OR_RANDOMTRUE(...)
#define DB_AND_RANDOMTRUE(...)
#endif /* BXE_DEBUG */
/* Generic bit decoding for printf("%b"). */
#define BXE_DWORD_PRINTFB \
"\020" \
"\40b31" \
"\37b30" \
"\36b29" \
"\35b28" \
"\34b27" \
"\33b26" \
"\32b25" \
"\31b24" \
"\30b23" \
"\27b22" \
"\26b21" \
"\25b20" \
"\24b19" \
"\23b18" \
"\22b17" \
"\21b16" \
"\20b15" \
"\17b14" \
"\16b13" \
"\15b12" \
"\14b11" \
"\13b10" \
"\12b9" \
"\11b8" \
"\10b7" \
"\07b6" \
"\06b5" \
"\05b4" \
"\04b3" \
"\03b2" \
"\02b1" \
"\01b0"
/* Supported link settings bit decoding for printf("%b"). */
#define BXE_SUPPORTED_PRINTFB \
"\020" \
"\040b31" \
"\037b30" \
"\036b29" \
"\035b28" \
"\034b27" \
"\033b26" \
"\032b25" \
"\031b24" \
"\030b23" \
"\027b22" \
"\026b21" \
"\025b20" \
"\024b19" \
"\023b18" \
"\022b17" \
"\02110000BaseT-Full" \
"\0202500BaseX-Full" \
"\017b14" \
"\016b13" \
"\015b12" \
"\014Pause" \
"\013Asym-Pause" \
"\012Autoneg" \
"\011Fiber" \
"\010TP" \
"\0071000BaseT-Full" \
"\0061000BaseT-Half" \
"\005100BaseTX-Full" \
"\004100BaseTX-Half" \
"\00310BaseT-Full" \
"\00210BaseT-Half" \
"\001b0"
/* Transmit BD TCP flags bit decoding for printf("%b"). */
#define BXE_ETH_TX_PARSE_BD_TCP_FLAGS_PRINTFB \
"\020" \
"\10CWR" \
"\07ECE" \
"\06URG" \
"\05ACK" \
"\04PSH" \
"\03RST" \
"\02SYN" \
"\01FIN"
/* Parsing BD global data bit decoding for printf("%b"). */
#define BXE_ETH_TX_PARSE_BD_GLOBAL_DATA_PRINTFB \
"\020" \
"\10NS" \
"\07LLC_SNAP" \
"\06PSEUDO_CS_WO_LEN" \
"\05CS_ANY"
/* Transmit BD flags bit decoding for printf("%b"). */
#define BXE_ETH_TX_BD_FLAGS_PRINTFB \
"\020" \
"\10IPv6" \
"\07LSO" \
"\06HDR_POOL" \
"\05START" \
"\04END" \
"\03TCP_CSUM" \
"\02IP_CSUM" \
"\01VLAN"
/* Receive CQE error flags bit decoding for printf("%b"). */
#define BXE_ETH_FAST_PATH_RX_CQE_ERROR_FLAGS_PRINTFB \
"\020" \
"\10RSRVD" \
"\07RSRVD" \
"\06END_FLAG" \
"\05START_FLAG" \
"\04L4_BAD_XSUM" \
"\03IP_BAD_XSUM" \
"\02PHY_DECODE_ERR" \
"\01SP"
#endif /* _BXE_DEBUG_H */

624
sys/dev/bxe/bxe_fw_defs.h Executable file
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@ -0,0 +1,624 @@
/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _BXE_FW_DEFS_H
#define _BXE_FW_DEFS_H
#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x7000 : 0x1000)
#define CSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
0x40) + (index * 0x4)))
#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
0x80) + (index * 0x4)))
#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
#define CSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
#define CSTORM_HC_BTR_C_OFFSET(port) \
(IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
#define CSTORM_HC_BTR_U_OFFSET(port) \
(IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
(function * 0x8)))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
(function * 0x8)))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x241c + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
(function * 0x8)))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
(function * 0x8)))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
(function * 0x8)))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
(function * 0x8)))
#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)))
#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)))
#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x3040 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
(0x4000 + (port * 0x800) + (cpu_id * 0x80)))
#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x3048 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
(0x4008 + (port * 0x800) + (cpu_id * 0x80)))
#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
#define CSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
(function * 0x8)))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
(IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0xa000 : 0x1000)
#define TSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
: (0x9c0 + (port * 0x120) + (client_id * 0x10)))
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
(IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
(IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
0x28) + (index * 0x4)))
#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
(function * 0x8)))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
(function * 0x40)))
#define TSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
#define TSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
(function * 0x80)))
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
(IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
: (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
(function * 0x8)))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
(function * 0x8)))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
(function * 0x8)))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
(function * 0x8)))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
(function * 0x8)))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
(function * 0x40)))
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
(function * 0x8)))
#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
(IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
(function * 0x8)))
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
#define USTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x8000 : 0x1000)
#define USTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
(0x4010 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
(0x4028 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
(IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
0xffffffff)
#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
(function * 0x8)))
#define USTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
(function * 0x8)))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
(function * 0x8)))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
(function * 0x8)))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
(function * 0x8)))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
(function * 0x8)))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
(function * 0x8)))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
(function * 0x8)))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
(function * 0x8)))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
(function * 0x8)))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
(function * 0x8)))
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
(0x4018 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
(function * 0x8)))
#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
#define USTORM_RX_PRODS_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
: (0x4000 + (port * 0x360) + (client_id * 0x30)))
#define USTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
(function * 0x8)))
#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
#define USTORM_TPA_BTR_SIZE 0x1
#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x9000 : 0x1000)
#define XSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
0x28) + (index * 0x4)))
#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define XSTORM_E1HOV_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
(function * 0x8)))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
(function * 0x90)))
#define XSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
#define XSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
(function * 0x8)))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
(function * 0x8)))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
(function * 0x8)))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
(function * 0x8)))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
(function * 0x8)))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
(function * 0x8)))
#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
(function * 0x90)))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
(function * 0x10)))
#define XSTORM_SPQ_PROD_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
(function * 0x10)))
#define XSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
(function * 0x8)))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
(IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
(IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
* 0x4)) : (0x1978 + (function * 0x4)))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/**
* This file defines HSI constants for the ETH flow
*/
#ifdef _EVEREST_MICROCODE
#include "microcode_constants.h"
#include "eth_rx_bd.h"
#include "eth_tx_bd.h"
#include "eth_rx_cqe.h"
#include "eth_rx_sge.h"
#include "eth_rx_cqe_next_page.h"
#endif
/* RSS hash types */
#define DEFAULT_HASH_TYPE 0
#define IPV4_HASH_TYPE 1
#define TCP_IPV4_HASH_TYPE 2
#define IPV6_HASH_TYPE 3
#define TCP_IPV6_HASH_TYPE 4
#define VLAN_PRI_HASH_TYPE 5
#define E1HOV_PRI_HASH_TYPE 6
#define DSCP_HASH_TYPE 7
/* Ethernet Ring parameters */
#define X_ETH_LOCAL_RING_SIZE 13
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
#define U_ETH_NUM_OF_SGES_TO_FETCH 8
#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 8
#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF
/* values of command IDs in the ramrod message */
#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
#define RAMROD_CMD_ID_ETH_UPDATE 100
#define RAMROD_CMD_ID_ETH_HALT 105
#define RAMROD_CMD_ID_ETH_SET_MAC 110
#define RAMROD_CMD_ID_ETH_CFC_DEL 115
#define RAMROD_CMD_ID_ETH_PORT_DEL 120
#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
/* command values for set mac command */
#define T_ETH_MAC_COMMAND_SET 0
#define T_ETH_MAC_COMMAND_INVALIDATE 1
#define T_ETH_INDIRECTION_TABLE_SIZE 128
/*The CRC32 seed, that is used for the hash(reduction) multicast address */
#define T_ETH_CRC32_HASH_SEED 0x00000000
/* Maximal L2 clients supported */
#define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 26
/* Maximal aggregation queues supported */
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
/* ETH RSS modes */
#define ETH_RSS_MODE_DISABLED 0
#define ETH_RSS_MODE_REGULAR 1
#define ETH_RSS_MODE_VLAN_PRI 2
#define ETH_RSS_MODE_E1HOV_PRI 3
#define ETH_RSS_MODE_IP_DSCP 4
/**
* This file defines HSI constants common to all microcode flows
*/
/* Connection types */
#define ETH_CONNECTION_TYPE 0
#define TOE_CONNECTION_TYPE 1
#define RDMA_CONNECTION_TYPE 2
#define ISCSI_CONNECTION_TYPE 3
#define FCOE_CONNECTION_TYPE 4
#define RESERVED_CONNECTION_TYPE_0 5
#define RESERVED_CONNECTION_TYPE_1 6
#define RESERVED_CONNECTION_TYPE_2 7
#define PROTOCOL_STATE_BIT_OFFSET 6
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
/* microcode fixed page page size 4K (chains and ring segments) */
#define MC_PAGE_SIZE 4096
/* Host coalescing constants */
#define HC_IGU_BC_MODE 0
#define HC_IGU_NBC_MODE 1
#define HC_REGULAR_SEGMENT 0
#define HC_DEFAULT_SEGMENT 1
/* index numbers */
#define HC_USTORM_DEF_SB_NUM_INDICES 8
#define HC_CSTORM_DEF_SB_NUM_INDICES 8
#define HC_XSTORM_DEF_SB_NUM_INDICES 4
#define HC_TSTORM_DEF_SB_NUM_INDICES 4
#define HC_USTORM_SB_NUM_INDICES 4
#define HC_CSTORM_SB_NUM_INDICES 4
/* index values - which counter to update */
#define HC_INDEX_U_TOE_RX_CQ_CONS 0
#define HC_INDEX_U_ETH_RX_CQ_CONS 1
#define HC_INDEX_U_ETH_RX_BD_CONS 2
#define HC_INDEX_U_FCOE_EQ_CONS 3
#define HC_INDEX_C_TOE_TX_CQ_CONS 0
#define HC_INDEX_C_ETH_TX_CQ_CONS 1
#define HC_INDEX_C_ISCSI_EQ_CONS 2
#define HC_INDEX_DEF_X_SPQ_CONS 0
#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
/* used by the driver to get the SB offset */
#define USTORM_ID 0
#define CSTORM_ID 1
#define XSTORM_ID 2
#define TSTORM_ID 3
#define ATTENTION_ID 4
/* max number of slow path commands per port */
#define MAX_RAMRODS_PER_PORT 8
/* values for RX ETH CQE type field */
#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define EMULATION_FREQUENCY_FACTOR 1600
#define FPGA_FREQUENCY_FACTOR 100
#define TIMERS_TICK_SIZE_CHIP (1e-3)
#define TIMERS_TICK_SIZE_EMUL \
((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
#define TIMERS_TICK_SIZE_FPGA \
((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
#define TSEMI_CLK1_RESUL_CHIP (1e-3)
#define TSEMI_CLK1_RESUL_EMUL \
((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define TSEMI_CLK1_RESUL_FPGA \
((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
#define XSEMI_CLK1_RESUL_CHIP (1e-3)
#define XSEMI_CLK1_RESUL_EMUL \
((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define XSEMI_CLK1_RESUL_FPGA \
((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define XSEMI_CLK2_RESUL_CHIP (1e-6)
#define XSEMI_CLK2_RESUL_EMUL \
((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define XSEMI_CLK2_RESUL_FPGA \
((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
#define SDM_TIMER_TICK_RESUL_EMUL \
((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define SDM_TIMER_TICK_RESUL_FPGA \
((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define XSTORM_IP_ID_ROLL_HALF 0x8000
#define XSTORM_IP_ID_ROLL_ALL 0
#define FW_LOG_LIST_SIZE 50
#define NUM_OF_PROTOCOLS 4
#define NUM_OF_SAFC_BITS 16
#define MAX_COS_NUMBER 4
#define MAX_T_STAT_COUNTER_ID 18
#define MAX_X_STAT_COUNTER_ID 18
#define MAX_U_STAT_COUNTER_ID 18
#define UNKNOWN_ADDRESS 0
#define UNICAST_ADDRESS 1
#define MULTICAST_ADDRESS 2
#define BROADCAST_ADDRESS 3
#define SINGLE_FUNCTION 0
#define MULTI_FUNCTION 1
#define IP_V4 0
#define IP_V6 1
#endif

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/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _BXE_INCLUDE_H
#define _BXE_INCLUDE_H
#include <sys/param.h>
#include <sys/types.h>
#include <sys/endian.h>
#include <machine/bus.h>
/*
* Convert FreeBSD byte order to match generated code usage.
*/
#if BYTE_ORDER == BIG_ENDIAN
#define __BIG_ENDIAN 1
#undef __LITTLE_ENDIAN
#else
#undef __BIG_ENDIAN
#define __LITTLE_ENDIAN 1
#endif
#include "bxe_debug.h"
#include "bxe_reg.h"
#include "bxe_fw_defs.h"
#include "bxe_hsi.h"
#include "bxe_link.h"
/*
* Convenience definitions used in multiple files.
*/
#define BXE_PRINTF(fmt, args...) \
do { \
device_printf(sc->bxe_dev, fmt, ##args);\
}while(0)
#ifdef BXE_DEBUG
#define REG_WR(sc, offset, val) \
bxe_reg_write32(sc, offset, val)
#define REG_WR8(sc, offset, val) \
bxe_reg_write8(sc, offset, val)
#define REG_WR16(sc, offset, val) \
bxe_reg_write16(sc, offset, val)
#define REG_WR32(sc, offset, val) \
bxe_reg_write32(sc, offset, val)
#define REG_RD(sc, offset) \
bxe_reg_read32(sc, offset)
#define REG_RD8(sc, offset) \
bxe_reg_read8(sc, offset)
#define REG_RD16(sc, offset) \
bxe_reg_read16(sc, offset)
#define REG_RD32(sc, offset) \
bxe_reg_read32(sc, offset)
#define REG_RD_IND(sc, offset) \
bxe_reg_rd_ind(sc, offset)
#define REG_WR_IND(sc, offset, val) \
bxe_reg_wr_ind(sc, offset, val)
#else
#define REG_WR(sc, offset, val) \
bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
#define REG_WR8(sc, offset, val) \
bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val)
#define REG_WR16(sc, offset, val) \
bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val)
#define REG_WR32(sc, offset, val) \
bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
#define REG_RD(sc, offset) \
bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
#define REG_RD8(sc, offset) \
bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset)
#define REG_RD16(sc, offset) \
bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset)
#define REG_RD32(sc, offset) \
bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
#define REG_RD_IND(sc, offset) \
bxe_reg_rd_ind(sc, offset)
#define REG_WR_IND(sc, offset, val) \
bxe_reg_wr_ind(sc, offset, val)
#endif /* BXE_DEBUG */
#define REG_RD_DMAE(sc, offset, val, len32) \
do { \
bxe_read_dmae(sc, offset, len32); \
memcpy(val, BXE_SP(sc, wb_data[0]), len32 * 4); \
} while (0)
#define REG_WR_DMAE(sc, offset, val, len32) \
do { \
memcpy(BXE_SP(sc, wb_data[0]), val, len32 * 4); \
bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), \
offset, len32); \
} while (0)
#define SHMEM_ADDR(sc, field) (sc->common.shmem_base + \
offsetof(struct shmem_region, field))
#define SHMEM_RD(sc, field) \
REG_RD(sc, SHMEM_ADDR(sc, field))
#define SHMEM_RD16(sc, field) \
REG_RD16(sc, SHMEM_ADDR(sc, field))
#define SHMEM_WR(sc, field, val) \
REG_WR(sc, SHMEM_ADDR(sc, field), val)
#define SHMEM2_ADDR(sc, field) (sc->common.shmem2_base + \
offsetof(struct shmem2_region, field))
#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
#define EMAC_RD(sc, reg) \
REG_RD(sc, emac_base + (uint32_t) reg)
#define EMAC_WR(sc, reg, val) \
REG_WR(sc, emac_base + (uint32_t) reg, val)
#define BMAC_WR(sc, reg, val) \
REG_WR(sc, GRCBASE_NIG + bmac_addr + reg, val)
#endif /* _BXE_INCLUDE_H */

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/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef BXE_INIT_H
#define BXE_INIT_H
/*
* bxe_init.h: Broadcom Everest network driver.
* Structures and macros needed during the initialization.
*/
/* RAM0 size in bytes */
#define STORM_INTMEM_SIZE_E1 0x5800
#define STORM_INTMEM_SIZE_E1H 0x10000
#define STORM_INTMEM_SIZE(sc) \
((CHIP_IS_E1(sc) ? STORM_INTMEM_SIZE_E1 : STORM_INTMEM_SIZE_E1H) / 4)
/* Init operation types and structures */
/* Common for both E1 and E1H */
#define OP_RD 0x1 /* read single register */
#define OP_WR 0x2 /* write single register */
#define OP_IW 0x3 /* write single register using mailbox */
#define OP_SW 0x4 /* copy a string to the device */
#define OP_SI 0x5 /* copy a string using mailbox */
#define OP_ZR 0x6 /* clear memory */
#define OP_ZP 0x7 /* unzip then copy with DMAE */
#define OP_WR_64 0x8 /* write 64 bit pattern */
#define OP_WB 0x9 /* copy a string using DMAE */
/* FPGA and EMUL specific operations */
#define OP_WR_EMUL 0xa /* write single register on Emulation */
#define OP_WR_FPGA 0xb /* write single register on FPGA */
#define OP_WR_ASIC 0xc /* write single register on ASIC */
/* Init stages */
/* Never reorder stages !!! */
#define COMMON_STAGE 0
#define PORT0_STAGE 1
#define PORT1_STAGE 2
#define FUNC0_STAGE 3
#define FUNC1_STAGE 4
#define FUNC2_STAGE 5
#define FUNC3_STAGE 6
#define FUNC4_STAGE 7
#define FUNC5_STAGE 8
#define FUNC6_STAGE 9
#define FUNC7_STAGE 10
#define STAGE_IDX_MAX 11
#define STAGE_START 0
#define STAGE_END 1
/* Indices of blocks */
#define PRS_BLOCK 0
#define SRCH_BLOCK 1
#define TSDM_BLOCK 2
#define TCM_BLOCK 3
#define BRB1_BLOCK 4
#define TSEM_BLOCK 5
#define PXPCS_BLOCK 6
#define EMAC0_BLOCK 7
#define EMAC1_BLOCK 8
#define DBU_BLOCK 9
#define MISC_BLOCK 10
#define DBG_BLOCK 11
#define NIG_BLOCK 12
#define MCP_BLOCK 13
#define UPB_BLOCK 14
#define CSDM_BLOCK 15
#define USDM_BLOCK 16
#define CCM_BLOCK 17
#define UCM_BLOCK 18
#define USEM_BLOCK 19
#define CSEM_BLOCK 20
#define XPB_BLOCK 21
#define DQ_BLOCK 22
#define TIMERS_BLOCK 23
#define XSDM_BLOCK 24
#define QM_BLOCK 25
#define PBF_BLOCK 26
#define XCM_BLOCK 27
#define XSEM_BLOCK 28
#define CDU_BLOCK 29
#define DMAE_BLOCK 30
#define PXP_BLOCK 31
#define CFC_BLOCK 32
#define HC_BLOCK 33
#define PXP2_BLOCK 34
#define MISC_AEU_BLOCK 35
#define PGLUE_B_BLOCK 36
#define IGU_BLOCK 37
/* Returns the index of start or end of a specific block stage in ops array. */
#define BLOCK_OPS_IDX(block, stage, end) \
(2 * (((block) * STAGE_IDX_MAX) + (stage)) + (end))
struct raw_op {
uint32_t op:8;
uint32_t offset:24;
uint32_t raw_data;
};
struct op_read {
uint32_t op:8;
uint32_t offset:24;
uint32_t pad;
};
struct op_write {
uint32_t op:8;
uint32_t offset:24;
uint32_t val;
};
struct op_string_write {
uint32_t op:8;
uint32_t offset:24;
#ifdef __LITTLE_ENDIAN
uint16_t data_off;
uint16_t data_len;
#else /* __BIG_ENDIAN */
uint16_t data_len;
uint16_t data_off;
#endif
};
struct op_zero {
uint32_t op:8;
uint32_t offset:24;
uint32_t len;
};
union init_op {
struct op_read read;
struct op_write write;
struct op_string_write str_wr;
struct op_zero zero;
struct raw_op raw;
};
#include "bxe_init_values_e1.h"
#include "bxe_init_values_e1h.h"
#endif /* BXE_INIT_H */

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/*-
* Copyright (c) 2007-2010 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef BXE_LINK_H
#define BXE_LINK_H
/*
* Defines
*/
#define DEFAULT_PHY_DEV_ADDR 3
#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
#define SPEED_AUTO_NEG 0
#define SPEED_12000 12000
#define SPEED_12500 12500
#define SPEED_13000 13000
#define SPEED_15000 15000
#define SPEED_16000 16000
#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE 16
#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE 3
#define SFP_EEPROM_PART_NO_ADDR 0x28
#define SFP_EEPROM_PART_NO_SIZE 16
#define PWR_FLT_ERR_MSG_LEN 250
/*
* Structs
*/
/* Inputs parameters to the CLC. */
struct link_params {
uint8_t port;
/* Default / User Configuration */
uint8_t loopback_mode;
#define LOOPBACK_NONE 0
#define LOOPBACK_EMAC 1
#define LOOPBACK_BMAC 2
#define LOOPBACK_XGXS_10 3
#define LOOPBACK_EXT_PHY 4
#define LOOPBACK_EXT 5
uint16_t req_duplex;
uint16_t req_flow_ctrl;
/* Should be set to TX / BOTH when req_flow_ctrl is set to AUTO. */
uint16_t req_fc_auto_adv;
/* Also determine AutoNeg. */
uint16_t req_line_speed;
/* Device parameters */
uint8_t mac_addr[6];
/* shmem parameters */
uint32_t shmem_base;
uint32_t speed_cap_mask;
uint32_t switch_cfg;
#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
/* Part of the hw_config read from the shmem. */
uint16_t hw_led_mode;
/* phy_addr populated by the CLC. */
uint8_t phy_addr;
/* uint8_t reserved1; */
uint32_t lane_config;
uint32_t ext_phy_config;
#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
/* Phy register parameter */
uint32_t chip_id;
uint16_t xgxs_config_rx[4]; /* preemphasis values for the rx side */
uint16_t xgxs_config_tx[4]; /* preemphasis values for the tx side */
uint32_t feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
/* Device pointer passed to all callback functions. */
struct bxe_softc *sc;
};
/* Output parameters */
struct link_vars {
uint8_t phy_flags;
uint8_t mac_type;
#define MAC_TYPE_NONE 0
#define MAC_TYPE_EMAC 1
#define MAC_TYPE_BMAC 2
/* Internal phy link indication. */
uint8_t phy_link_up;
uint8_t link_up;
uint16_t line_speed;
uint16_t duplex;
uint16_t flow_ctrl;
uint16_t ieee_fc;
uint32_t autoneg;
#define AUTO_NEG_DISABLED 0x0
#define AUTO_NEG_ENABLED 0x1
#define AUTO_NEG_COMPLETE 0x2
#define AUTO_NEG_PARALLEL_DETECTION_USED 0x4
/* The same definitions as the shmem parameter. */
uint32_t link_status;
};
/*
* Functions
*/
/* Initialize the phy. */
uint8_t bxe_phy_init(struct link_params *input, struct link_vars *output);
/*
* Reset the link. Should be called when driver or interface goes down
* Before calling phy firmware upgrade, the reset_ext_phy should be set
* to 0.
*/
uint8_t bxe_link_reset(struct link_params *params, struct link_vars *vars,
uint8_t reset_ext_phy);
/* bxe_link_update should be called upon link interrupt */
uint8_t bxe_link_update(struct link_params *input, struct link_vars *output);
/*
* Use the following cl45 functions to read/write from external_phy
* In order to use it to read/write internal phy registers, use
* DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
* Use ext_phy_type of 0 in case of cl22 over cl45
* the register.
*/
uint8_t bxe_cl45_read(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t *ret_val);
uint8_t bxe_cl45_write(struct bxe_softc *sc, uint8_t port,
uint32_t ext_phy_type, uint8_t phy_addr, uint8_t devad, uint16_t reg,
uint16_t val);
/*
* Reads the link_status from the shmem, and update the link vars accordingly.
*/
void bxe_link_status_update(struct link_params *input,
struct link_vars *output);
/* Returns string representing the fw_version of the external phy. */
uint8_t bxe_get_ext_phy_fw_version(struct link_params *params,
uint8_t driver_loaded, uint8_t *version, uint16_t len);
/*
* Set/Unset the led
* Basically, the CLC takes care of the led for the link, but in case one needs
* to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink
* the led, and LED_MODE_OFF to set the led off.
*/
uint8_t bxe_set_led(struct link_params *params, uint8_t mode, uint32_t speed);
#define LED_MODE_OFF 0
#define LED_MODE_OPER 2
uint8_t bxe_override_led_value(struct bxe_softc *sc, uint8_t port,
uint32_t led_idx, uint32_t value);
/*
* bxe_handle_module_detect_int should be called upon module detection
* interrupt.
*/
void bxe_handle_module_detect_int(struct link_params *params);
/*
* Get the actual link status. In case it returns 0, link is up, otherwise
* link is down.
*/
uint8_t bxe_test_link(struct link_params *input, struct link_vars *vars);
/* One-time initialization for external phy after power up. */
uint8_t bxe_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base);
/* Reset the external PHY using GPIO. */
void bxe_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
void bxe_sfx7101_sp_sw_reset(struct bxe_softc *sc, uint8_t port,
uint8_t phy_addr);
uint8_t bxe_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
uint8_t byte_cnt, uint8_t *o_buf);
#endif /* BXE_LINK_H */

6391
sys/dev/bxe/bxe_reg.h Executable file
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1049
sys/dev/bxe/bxe_self_test.h Executable file
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131
sys/dev/bxe/dump_e1.h Executable file
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@ -0,0 +1,131 @@
/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
uint32_t regs_count_e1=319;
struct reg_addr reg_addrs_e1[319] = {
{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
{0x00008800,6}, {0x0000a000,223}, {0x0000a388,1}, {0x0000a398,1},
{0x0000a400,69}, {0x0000a518,1}, {0x0000a520,1}, {0x0000a528,1},
{0x0000a530,1}, {0x0000a538,1}, {0x0000a540,1}, {0x0000a548,1},
{0x0000a550,1}, {0x0000a558,1}, {0x0000a560,1}, {0x0000a568,1},
{0x0000a570,1}, {0x0000a580,1}, {0x0000a590,1}, {0x0000a5a0,1},
{0x0000a5c0,1}, {0x0000c000,35}, {0x0000c098,1}, {0x0000c0a8,1},
{0x0000c100,11}, {0x0000c130,2}, {0x0000c140,2}, {0x0000c160,4},
{0x0000c180,4}, {0x0000c1a0,4}, {0x0000c800,4}, {0x00010000,236},
{0x000103bc,1}, {0x000103cc,1}, {0x000103dc,1}, {0x00010400,57},
{0x000104e8,2}, {0x000104f4,2}, {0x00010500,146}, {0x00010750,2},
{0x00010760,2}, {0x00010770,2}, {0x00010780,2}, {0x00010790,2},
{0x000107a0,2}, {0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2},
{0x000107e0,2}, {0x00010880,2}, {0x00010900,2}, {0x00010c00,2},
{0x00011000,2}, {0x00012000,1}, {0x00014000,1}, {0x00020000,170},
{0x000202b4,1}, {0x000202c4,1}, {0x00020400,2}, {0x0002040c,8},
{0x00020480,1}, {0x00020500,1}, {0x00020600,1}, {0x00028000,24674},
{0x00040194,1}, {0x000401a4,1}, {0x00040200,4}, {0x00040400,43},
{0x000404b8,1}, {0x000404c8,1}, {0x00040500,2}, {0x00040510,2},
{0x00040520,2}, {0x00040530,2}, {0x00040540,2}, {0x00042000,164},
{0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1}, {0x00042400,49},
{0x000424c8,38}, {0x00042568,2}, {0x00042800,1}, {0x00050000,116},
{0x000501dc,1}, {0x000501ec,1}, {0x00050200,2}, {0x0005020c,7},
{0x00050240,1}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
{0x00058000,8263}, {0x00060128,1}, {0x00060138,1}, {0x00060200,1},
{0x00061000,512}, {0x00070000,32768}, {0x000a0000,16384},
{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
{0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2}, {0x000c4600,1},
{0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1}, {0x000d0200,2},
{0x000d020c,7}, {0x000d0280,1}, {0x000d0300,1}, {0x000d0400,1},
{0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1}, {0x000e01e4,1},
{0x000e0200,2}, {0x000e020c,8}, {0x000e0280,1}, {0x000e0300,1},
{0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384}, {0x00101000,12},
{0x0010103c,1}, {0x0010104c,1}, {0x00101100,1}, {0x00101800,8},
{0x00102000,18}, {0x00102054,1}, {0x00102064,1}, {0x00102080,17},
{0x00102400,1}, {0x00103000,26}, {0x00103074,1}, {0x00103084,1},
{0x00103094,1}, {0x00103800,8}, {0x00104000,63}, {0x00104108,1},
{0x00104118,1}, {0x00104200,17}, {0x00104400,512}, {0x00105000,1024},
{0x00108000,33}, {0x00108090,1}, {0x001080a0,1}, {0x00108100,5},
{0x00108120,5}, {0x00108200,74}, {0x00108400,74}, {0x00108800,152},
{0x00109000,1}, {0x00120000,347}, {0x00120578,1}, {0x00120588,1},
{0x00120598,1}, {0x0012080c,65}, {0x00120a00,2}, {0x00122000,2},
{0x00140000,114}, {0x001401d4,1}, {0x001401e4,1}, {0x00140200,6},
{0x00144000,4}, {0x00148000,4}, {0x0014c000,4}, {0x00150000,4},
{0x00154000,4}, {0x00158000,4}, {0x00161000,7}, {0x00161028,1},
{0x00161038,1}, {0x00161800,2}, {0x00164000,60}, {0x001640fc,1},
{0x0016410c,1}, {0x00164200,1}, {0x00164208,1}, {0x00164210,1},
{0x00164218,1}, {0x00164220,1}, {0x00164228,1}, {0x00164230,1},
{0x00164238,1}, {0x00164240,1}, {0x00164248,1}, {0x00164250,1},
{0x00164258,1}, {0x00164260,1}, {0x00164270,2}, {0x00164280,2},
{0x00164800,2}, {0x00165000,2}, {0x00166000,164}, {0x0016629c,1},
{0x001662ac,1}, {0x001662bc,1}, {0x00166400,49}, {0x001664c8,38},
{0x00166568,2}, {0x00166800,1}, {0x00168000,270}, {0x00168444,1},
{0x00168454,1}, {0x00168800,19}, {0x00168900,1}, {0x00168a00,128},
{0x0016a000,1536}, {0x0016c000,1536}, {0x00170000,93}, {0x00170180,1},
{0x00170190,1}, {0x00170200,4}, {0x00170214,1}, {0x00178000,1},
{0x00180000,61}, {0x00180100,1}, {0x00180110,1}, {0x00180120,1},
{0x00180130,1}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
{0x00181000,1024}, {0x001a0000,5632}, {0x001a8000,64},
{0x001b1800,128}, {0x001b1c00,128}, {0x001b2000,1}, {0x001b8200,1},
{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x00200200,58},
{0x00200340,4}, {0x00200400,1}, {0x00202000,2048}, {0x00220000,5632},
{0x00228000,64}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
{0x00238200,1}, {0x00238240,1}, {0x00238280,1}, {0x002382c0,1},
{0x00238a00,1}, {0x00238a80,1}, {0x00240000,2}, {0x00280000,65},
{0x00280110,1}, {0x00280120,1}, {0x00280130,1}, {0x00280140,1},
{0x00280200,58}, {0x00280340,4}, {0x00280400,1}, {0x00282000,2048},
{0x002a0000,5632}, {0x002a8000,64}, {0x002b1800,128}, {0x002b1c00,128},
{0x002b2000,1}, {0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1},
{0x002b82c0,1}, {0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2},
{0x00300000,65}, {0x00300110,1}, {0x00300120,1}, {0x00300130,1},
{0x00300140,1}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
{0x00302000,2048}, {0x00320000,5632}, {0x00328000,64},
{0x00331800,128}, {0x00331c00,128}, {0x00332000,1}, {0x00338200,1},
{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
{0x00338a80,1}, {0x00340000,2}};
uint32_t wregs_count_e1=1;
static uint32_t const_reg0_e1[1] = {0x001b1000};
struct wreg_addr wreg_addrs_e1[1] = {{0x001b0c00, 192, 1, const_reg0_e1}};
struct hd_param hd_param_e1={0x497e2e43, 0x00040802, 0x0000001f};

140
sys/dev/bxe/dump_e1h.h Executable file
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@ -0,0 +1,140 @@
/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
uint32_t regs_count_e1h=354;
struct reg_addr reg_addrs_e1h[354] = {
{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
{0x0000a000,223}, {0x0000a388,1}, {0x0000a398,8}, {0x0000a3c0,3},
{0x0000a3d0,1}, {0x0000a3d8,1}, {0x0000a3e0,1}, {0x0000a3e8,1},
{0x0000a3f0,1}, {0x0000a3f8,1}, {0x0000a400,69}, {0x0000a518,1},
{0x0000a520,1}, {0x0000a528,1}, {0x0000a530,1}, {0x0000a538,1},
{0x0000a540,1}, {0x0000a548,1}, {0x0000a550,1}, {0x0000a558,1},
{0x0000a560,1}, {0x0000a568,1}, {0x0000a570,1}, {0x0000a580,1},
{0x0000a590,1}, {0x0000a5a0,1}, {0x0000a5c0,1}, {0x0000a5e0,1},
{0x0000a5e8,1}, {0x0000a5f0,1}, {0x0000a5f8,10}, {0x0000c000,35},
{0x0000c098,1}, {0x0000c0a8,1}, {0x0000c100,11}, {0x0000c130,2},
{0x0000c140,2}, {0x0000c160,4}, {0x0000c180,4}, {0x0000c1a0,4},
{0x0000c800,4}, {0x0000d000,347}, {0x00010000,236}, {0x000103bc,1},
{0x000103cc,1}, {0x000103dc,1}, {0x00010400,57}, {0x000104e8,2},
{0x000104f4,2}, {0x00010500,146}, {0x00010750,2}, {0x00010760,2},
{0x00010770,2}, {0x00010780,2}, {0x00010790,2}, {0x000107a0,2},
{0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2}, {0x000107e0,2},
{0x00010880,2}, {0x00010900,2}, {0x00010c00,2}, {0x00011000,2},
{0x00012000,1}, {0x00014000,1}, {0x00016000,26}, {0x00016070,18},
{0x000160c0,27}, {0x00016140,1}, {0x00016160,1}, {0x00016180,2},
{0x000161c0,2}, {0x00016204,5}, {0x00018000,1}, {0x00018008,1},
{0x00020000,170}, {0x000202b4,1}, {0x000202c4,1}, {0x00020400,2},
{0x0002040c,26}, {0x00020480,1}, {0x00020500,1}, {0x00020600,1},
{0x00028000,24674}, {0x00040194,1}, {0x000401a4,12}, {0x00040200,4},
{0x00040400,43}, {0x000404b8,1}, {0x000404c8,4}, {0x00040500,2},
{0x00040510,2}, {0x00040520,2}, {0x00040530,2}, {0x00040540,2},
{0x00042000,164}, {0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1},
{0x000422d4,5}, {0x00042400,49}, {0x000424c8,38}, {0x00042568,2},
{0x00042800,1}, {0x00050000,116}, {0x000501dc,1}, {0x000501ec,7},
{0x0005020c,14}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
{0x00058000,8263}, {0x00060128,1}, {0x00060138,25}, {0x00060200,1},
{0x00061000,512}, {0x00070000,32768}, {0x000a0000,32768},
{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
{0x000c42e0,7}, {0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2},
{0x000c4600,1}, {0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1},
{0x000d0200,2}, {0x000d020c,25}, {0x000d0280,1}, {0x000d0300,1},
{0x000d0400,1}, {0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1},
{0x000e01e4,1}, {0x000e0200,2}, {0x000e020c,26}, {0x000e0280,1},
{0x000e0300,1}, {0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384},
{0x00101000,12}, {0x0010103c,1}, {0x0010104c,2}, {0x00101100,1},
{0x00101800,8}, {0x00102000,18}, {0x00102054,1}, {0x00102064,1},
{0x00102080,17}, {0x001020c8,8}, {0x00102400,1}, {0x00103000,26},
{0x00103074,1}, {0x00103084,1}, {0x00103094,6}, {0x00103800,8},
{0x00104000,63}, {0x00104108,1}, {0x00104118,1}, {0x00104200,17},
{0x00104400,512}, {0x00105000,1024}, {0x00108000,33}, {0x00108090,1},
{0x001080a0,1}, {0x001080ac,5}, {0x00108100,5}, {0x00108120,5},
{0x00108200,74}, {0x00108400,74}, {0x00108800,152}, {0x00109000,1},
{0x00120000,347}, {0x00120578,1}, {0x00120588,1}, {0x00120598,24},
{0x00120614,1}, {0x0012061c,30}, {0x0012080c,65}, {0x00120a00,2},
{0x00122000,2}, {0x00128000,2}, {0x00140000,114}, {0x001401d4,1},
{0x001401e4,1}, {0x00140200,6}, {0x00144000,4}, {0x00148000,4},
{0x0014c000,4}, {0x00150000,4}, {0x00154000,4}, {0x00158000,4},
{0x0015c000,7}, {0x00161000,7}, {0x00161028,1}, {0x00161038,1},
{0x00161800,2}, {0x00164000,60}, {0x001640fc,1}, {0x0016410c,3},
{0x00164200,1}, {0x00164208,1}, {0x00164210,1}, {0x00164218,1},
{0x00164220,1}, {0x00164228,1}, {0x00164230,1}, {0x00164238,1},
{0x00164240,1}, {0x00164248,1}, {0x00164250,1}, {0x00164258,1},
{0x00164260,1}, {0x00164270,2}, {0x00164280,2}, {0x00164800,2},
{0x00165000,2}, {0x00166000,164}, {0x0016629c,1}, {0x001662ac,1},
{0x001662bc,1}, {0x00166400,49}, {0x001664c8,38}, {0x00166568,2},
{0x00166800,1}, {0x00168000,270}, {0x00168444,1}, {0x00168454,1},
{0x00168800,19}, {0x00168900,1}, {0x00168a00,128}, {0x0016a000,1536},
{0x0016c000,1536}, {0x0016e000,16}, {0x0016e100,1}, {0x0016e200,2},
{0x0016e400,183}, {0x00170000,93}, {0x00170180,1}, {0x00170190,1},
{0x00170200,4}, {0x00170214,1}, {0x00178000,1}, {0x00180000,61},
{0x00180100,1}, {0x00180110,1}, {0x00180120,1}, {0x00180130,1},
{0x0018013c,2}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
{0x00181000,1024}, {0x001a0000,16896}, {0x001b1800,128},
{0x001b1c00,128}, {0x001b2000,1}, {0x001b2400,64}, {0x001b8200,1},
{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x0020014c,2},
{0x00200200,58}, {0x00200340,4}, {0x00200400,1}, {0x00202000,2048},
{0x00220000,16896}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
{0x00232400,64}, {0x00238200,1}, {0x00238240,1}, {0x00238280,1},
{0x002382c0,1}, {0x00238a00,1}, {0x00238a80,1}, {0x00240000,2},
{0x00280000,65}, {0x00280110,1}, {0x00280120,1}, {0x00280130,1},
{0x00280140,1}, {0x0028014c,2}, {0x00280200,58}, {0x00280340,4},
{0x00280400,1}, {0x00282000,2048}, {0x002a0000,16896},
{0x002b1800,128}, {0x002b1c00,128}, {0x002b2000,1}, {0x002b2400,64},
{0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1}, {0x002b82c0,1},
{0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2}, {0x00300000,65},
{0x00300110,1}, {0x00300120,1}, {0x00300130,1}, {0x00300140,1},
{0x0030014c,2}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
{0x00302000,2048}, {0x00320000,16896}, {0x00331800,128},
{0x00331c00,128}, {0x00332000,1}, {0x00332400,64}, {0x00338200,1},
{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
{0x00338a80,1}, {0x00340000,2}};
uint32_t wregs_count_e1h=1;
static uint32_t const_reg0_e1h[2] = {0x001b1040, 0x001b1000};
struct wreg_addr wreg_addrs_e1h[1] = {{0x001b0c00, 256, 2, const_reg0_e1h}};
struct hd_param hd_param_e1h={0x497e2efb, 0x00040802, 0x0000001f};

80
sys/dev/bxe/hw_dump_reg_st.h Executable file
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@ -0,0 +1,80 @@
/*-
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
*
* Gary Zambrano <zambrano@broadcom.com>
* David Christensen <davidch@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD$*/
#ifndef _HW_DUMP_REG_ST_H
#define _HW_DUMP_REG_ST_H
#define BXE_GRCDUMP_BUF_SIZE 0xE0000
#define XSTORM_WAITP_ADDRESS 0x2b8a80
#define TSTORM_WAITP_ADDRESS 0x2b8a80
#define USTORM_WAITP_ADDRESS 0x2b8a80
#define CSTORM_WAITP_ADDRESS 0x2b8a80
#define TSTORM_CAM_MODE 0x1B1440
/* Register address structure. */
typedef struct reg_addr {
uint32_t addr;
uint32_t size;
}*preg_addr;
/* Wide register address structure. */
typedef struct wreg_addr {
uint32_t addr;
uint32_t size;
uint32_t const_regs_count;
uint32_t * const_regs;
}*pwreg_addr;
/* Dump header parameters. */
struct hd_param {
uint32_t time_stamp;
uint32_t diag_ver;
uint32_t grc_dump_ver;
};
/* Global parameters. */
extern struct wreg_addr wreg_addrs_e1[];
extern struct reg_addr reg_addrs_e1[];
extern uint32_t regs_count_e1;
extern uint32_t wregs_count_e1;
extern struct hd_param hd_param_e1;
extern struct wreg_addr wreg_addrs_e1h[];
extern struct reg_addr reg_addrs_e1h[];
extern uint32_t regs_count_e1h;
extern uint32_t wregs_count_e1h;
extern struct hd_param hd_param_e1h;
#endif //_HW_DUMP_REG_ST_H

17294
sys/dev/bxe/if_bxe.c Executable file
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1853
sys/dev/bxe/if_bxe.h Executable file
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File diff suppressed because it is too large Load Diff

1
sys/i386/conf/GENERIC
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@ -203,6 +203,7 @@ device ppi # Parallel port interface device
#device puc
# PCI Ethernet NICs.
device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel PRO/1000 Gigabit Ethernet Family
device igb # Intel PRO/1000 PCIE Server Gigabit Family

13
sys/modules/bxe/Makefile Executable file
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@ -0,0 +1,13 @@
# $FreeBSD$
BXE = ${.CURDIR}/../../dev/bxe
.PATH: ${BXE}
KMOD= if_bxe
SRCS = opt_bxe.h device_if.h bus_if.h pci_if.h miibus_if.h miidevs.h
SRCS += if_bxe.c bxe_link.c
CFLAGS += -I${BXE} -DBXE_TASK
#CFLAGS += -DBXE_DEBUG
#CFLAGS += -DBXE_NVRAM_WRITE_SUPPORT
.include <bsd.kmod.mk>

1
usr.sbin/sysinstall/devices.c
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@ -106,6 +106,7 @@ static struct _devname {
NETWORK("bge", "Broadcom BCM570x PCI Gigabit Ethernet card"),
NETWORK("bm", "Apple BMAC Built-in Ethernet"),
NETWORK("bwn", "Broadcom BCM43xx IEEE 802.11 wireless adapter"),
NETWORK("bxe", "Broadcom NetXtreme II 10Gb Ethernet card"),
NETWORK("cas", "Sun Cassini/Cassini+ or NS DP83065 Saturn Ethernet"),
NETWORK("cue", "CATC USB Ethernet adapter"),
NETWORK("cxgb", "Chelsio T3 10Gb Ethernet card"),