cxgbe(4): Update T5 and T4 firmwares to 1.15.28.0.
These firmwares were obtained from the beta "Chelsio T5/T4 Unified Wire v2.12.0.2 for Linux" release. Changes since last release are listed in the "Release Notes" accompanying the beta release and are copy-pasted here as well. The plan is to have only GA'd firmwares in any -STABLE FreeBSD branch so I'll MFC this (after 2 months) only if it ends up in a GA release. ================================================================================ ================================================================================ 22.1. T5 Firmware +++++++++++++++++++++++++++++++++ Version : 1.15.28.0 Date : 02/29/2016 ================================================================================ FIXES ----- BASE: - Fixed an issue in FW_RSS_VI_CONFIG_CMD handling where the default ingress queue was ignored. - Fixed an issue where adapter failed to load fw by adjusting DRAM frequency. - Fixed an issue in watchdog which was causing VM bring-up failure after reboot. - Fixed 40G link failures with some switches when auto-negotiation enabled. - Fixed to improve on link bring-up time. - Per port buffer groups size doubled to improve performance. - Fixed an issue where bogus d3hot bits were set causing traffic stall. - Fixed an issue where sometimes adapter was not seen after reboot. - Fixed an issue where iWARP was crashing in conjunction with traffic management. - Fixed an issue where link failed to come up after removing twinax cable and inserting optical module. OFLD - Fixed a potential iSCSI data corruption issue by disabling RxFragEn flag. FOiSCSI - Fixed an issue in recovery path where connection was getting closed before recovery processing was done. - Fixed an issue in TCP port reuse. - Fixed an issue in recovery path when large number (>64) of iSCSI connections were in use. - Returned ENETUNREACH if IP was not been provisioned yet and driver tried to use given inerface. ENHANCEMENTS ------------ BASE: - Added new interface to program DCA settings in SGE contexts; allow 32-byte IQE size - Added PTP interface fw_ptp_ts to support PTP Frequeny and Offset adjustment. - Added MPS raw interface. ETH: - New mailbox command FW_DCB_IEEE_CMD api added for IEEE dcbx. OFLD: - WR opcode is returned to host in cqe error response. ================================================================================ ================================================================================ 22.2. T4 Firmware +++++++++++++++++ Version : 1.15.28.0 Date : 02/29/2016 ================================================================================ FIXES ----- BASE: - Fixed an issue in FW_RSS_VI_CONFIG_CMD handling where default ingress queue was ignored. - Fixed an issue in watchdog which was causing VM bring-up failure after reboot. - Per port buffer groups size doubled to improve performance. - Fixed an issue where iWARP was crashing in conjunction with traffic management. FOiSCSI: - Fixed an issue in recovery path where connection was getting closed before recovery processing was done. - Fixed an issue in TCP port reuse. - Fixed an issue in recovery path when large number (>64) of iSCSI connections were in use. - Returned ENETUNREACH if IP had not been provisioned yet and driver tried to use given inerface. ENHANCEMENTS ------------ BASE: - Added MPS raw interface. ETH: - New mailbox command FW_DCB_IEEE_CMD api added for IEEE dcbx. ================================================================================ Obtained from: Chelsio Communications MFC after: 2 months Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
54ac2713d5
commit
dd991bd5a1
@ -1212,7 +1212,7 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.14.4.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.15.28.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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@ -1236,7 +1236,7 @@ t5fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.14.4.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.15.28.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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@ -5218,13 +5218,14 @@ int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
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bool ucast, u64 vec, bool sleep_ok)
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{
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struct fw_vi_mac_cmd c;
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u32 val;
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memset(&c, 0, sizeof(c));
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c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_MAC_CMD) | F_FW_CMD_REQUEST |
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F_FW_CMD_WRITE | V_FW_VI_ENABLE_CMD_VIID(viid));
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c.freemacs_to_len16 = htonl(F_FW_VI_MAC_CMD_HASHVECEN |
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V_FW_VI_MAC_CMD_HASHUNIEN(ucast) |
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V_FW_CMD_LEN16(1));
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val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
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V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
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c.freemacs_to_len16 = cpu_to_be32(val);
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c.u.hash.hashvec = cpu_to_be64(vec);
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return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
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}
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File diff suppressed because it is too large
Load Diff
9540
sys/dev/cxgbe/firmware/t4fw-1.15.28.0.bin.uu
Normal file
9540
sys/dev/cxgbe/firmware/t4fw-1.15.28.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -17,6 +17,9 @@
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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# disable TP_PARA_REG3.RxFragEn
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reg[0x7d6c] = 0x00000000/0x00007000
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# TP_SHIFT_CNT
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reg[0x7dc0] = 0x62f8849
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@ -163,7 +166,7 @@
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[fini]
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version = 0x1
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checksum = 0xc5e9ef34
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checksum = 0x98210e18
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#
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# $FreeBSD$
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#
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@ -112,6 +112,9 @@
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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# disable TP_PARA_REG3.RxFragEn
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reg[0x7d6c] = 0x00000000/0x00007000
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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# TP_VLAN_PRI_MAP to select filter tuples
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@ -548,7 +551,7 @@
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[fini]
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version = 0x1425001c
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checksum = 0x63a652b3
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checksum = 0x5ceab41e
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2012-2014 Chelsio Communications, Inc.
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* Copyright (c) 2012-2016 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -135,7 +135,13 @@ enum fw_wr_opcodes {
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FW_POFCOE_ULPTX_WR = 0x43,
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FW_ISCSI_TX_DATA_WR = 0x45,
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FW_PTP_TX_PKT_WR = 0x46,
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FW_LASTC2E_WR = 0x70
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FW_SEC_LOOKASIDE_LPBK_WR= 0x63,
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FW_COiSCSI_TGT_WR = 0x70,
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FW_COiSCSI_TGT_CONN_WR = 0x71,
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FW_COiSCSI_TGT_XMIT_WR = 0x72,
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FW_ISNS_WR = 0x75,
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FW_ISNS_XMIT_WR = 0x76,
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FW_LASTC2E_WR = 0x80
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};
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/*
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@ -1376,6 +1382,7 @@ enum fw_ri_res_type {
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FW_RI_RES_TYPE_SQ,
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FW_RI_RES_TYPE_RQ,
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FW_RI_RES_TYPE_CQ,
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FW_RI_RES_TYPE_SRQ,
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};
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enum fw_ri_res_op {
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@ -1409,6 +1416,20 @@ struct fw_ri_res {
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__be32 r6_lo;
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__be64 r7;
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} cq;
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struct fw_ri_res_srq {
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__u8 restype;
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__u8 op;
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__be16 r3;
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__be32 eqid;
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__be32 r4[2];
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__be32 fetchszm_to_iqid;
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__be32 dcaen_to_eqsize;
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__be64 eqaddr;
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__be32 srqid;
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__be32 pdid;
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__be32 hwsrqsize;
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__be32 hwsrqaddr;
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} srq;
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} u;
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};
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@ -1874,6 +1895,10 @@ enum fw_ri_init_p2ptype {
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FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
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};
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enum fw_ri_init_rqeqid_srq {
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FW_RI_INIT_RQEQID_SRQ = 1 << 31,
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};
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struct fw_ri_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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@ -2512,6 +2537,163 @@ struct fw_foiscsi_chap_wr {
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__u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
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};
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/******************************************************************************
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* C O i S C S I W O R K R E Q U E S T S
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********************************************/
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enum fw_chnet_addr_type {
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FW_CHNET_ADDD_TYPE_NONE = 0,
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FW_CHNET_ADDR_TYPE_IPV4,
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FW_CHNET_ADDR_TYPE_IPV6,
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};
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struct fw_coiscsi_tgt_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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__u64 cookie;
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__u8 subop;
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__u8 status;
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__be16 r4;
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__be32 flags;
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struct fw_coiscsi_tgt_conn_attr {
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__be32 in_tid;
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__be16 in_port;
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__u8 in_type;
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__u8 r6;
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union fw_coiscsi_tgt_conn_attr_addr {
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struct fw_coiscsi_tgt_conn_attr_in_addr {
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__be32 addr;
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__be32 r7;
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__be32 r8[2];
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} in_addr;
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struct fw_coiscsi_tgt_conn_attr_in_addr6 {
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__be64 addr[2];
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} in_addr6;
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} u;
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} conn_attr;
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};
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struct fw_coiscsi_tgt_conn_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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__u64 cookie;
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__u8 subop;
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__u8 status;
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__be16 iq_id;
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__be32 in_stid;
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__be32 io_id;
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__be32 flags;
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struct fw_coiscsi_tgt_conn_tcp {
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__be16 in_sport;
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__be16 in_dport;
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__be32 r4;
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union fw_coiscsi_tgt_conn_tcp_addr {
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struct fw_coiscsi_tgt_conn_tcp_in_addr {
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__be32 saddr;
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__be32 daddr;
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} in_addr;
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struct fw_coiscsi_tgt_conn_tcp_in_addr6 {
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__be64 saddr[2];
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__be64 daddr[2];
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} in_addr6;
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} u;
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} conn_tcp;
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struct fw_coiscsi_tgt_conn_iscsi {
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__be32 hdigest_to_ddp_pgsz;
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__be32 tgt_id;
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__be16 max_r2t;
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__be16 max_rcv_dsl;
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__be32 max_burst;
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__be32 nxt_statsn;
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__be32 r6;
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} conn_iscsi;
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};
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struct fw_coiscsi_tgt_xmit_wr {
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__be32 op_to_immdlen;
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__be32 flowid_len16;
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__be64 cookie;
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__be16 iq_id;
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__be16 r4;
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__be32 datasn;
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__be32 t_xfer_len;
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__be32 flags;
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};
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#define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23
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#define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1
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#define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
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((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
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#define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
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(((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
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#define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
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#define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22
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#define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1
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#define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
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((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
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#define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
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(((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
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#define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
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#define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20
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#define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1
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#define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
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#define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \
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(((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
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#define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
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#define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0
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#define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff
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#define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
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((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
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#define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
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(((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
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M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
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struct fw_isns_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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__u64 cookie;
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__u8 subop;
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__u8 status;
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__be16 iq_id;
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__be32 r4;
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struct fw_tcp_conn_attr {
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__be32 in_tid;
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__be16 in_port;
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__u8 in_type;
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__u8 r6;
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union fw_tcp_conn_attr_addr {
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struct fw_tcp_conn_attr_in_addr {
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__be32 addr;
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__be32 r7;
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__be32 r8[2];
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} in_addr;
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struct fw_tcp_conn_attr_in_addr6 {
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__be64 addr[2];
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} in_addr6;
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} u;
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} conn_attr;
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};
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struct fw_isns_xmit_wr {
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__be32 op_to_immdlen;
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__be32 flowid_len16;
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__be64 cookie;
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__be16 iq_id;
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__be16 r4;
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__be32 xfer_len;
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__be64 r5;
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};
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#define S_FW_ISNS_XMIT_WR_IMMDLEN 0
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#define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff
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#define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
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#define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \
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(((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
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/******************************************************************************
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* F O F C O E W O R K R E Q U E S T s
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*******************************************/
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@ -3168,6 +3350,127 @@ struct fw_pi_error {
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(((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
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struct fw_sec_lookaside_lpbk_wr {
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__be32 op_to_cctx_size;
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__be32 len16_pkd;
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__be32 session_id;
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__be32 rx_chid_to_rx_q_id;
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__be32 key_addr;
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__be32 pld_size_hash_size;
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__be64 cookie;
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};
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#define S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 24
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#define M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 0xff
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#define V_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
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((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
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#define G_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
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(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) & \
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M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
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#define S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 23
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#define M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 0x1
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#define V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
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((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
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#define G_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
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(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) & \
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M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
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#define F_FW_SEC_LOOKASIDE_LPBK_WR_COMPL V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(1U)
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#define S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 15
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#define M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 0xff
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#define V_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
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((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
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#define G_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
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(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) & \
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M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
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#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 5
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#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 0x3
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#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
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((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
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#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0x1f
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 29
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_LCB 27
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_LCB 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) & M_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 25
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_IV 23
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_IV 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IV)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IV) & M_FW_SEC_LOOKASIDE_LPBK_WR_IV)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 10
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0x3ff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 24
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 17
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 0x7f
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
|
||||
|
||||
/******************************************************************************
|
||||
* C O M M A N D s
|
||||
*********************/
|
||||
@ -3233,6 +3536,7 @@ enum fw_cmd_opcodes {
|
||||
FW_FCOE_STATS_CMD = 0x37,
|
||||
FW_FCOE_FCF_CMD = 0x38,
|
||||
FW_PTP_CMD = 0x39,
|
||||
FW_DCB_IEEE_CMD = 0x3a,
|
||||
FW_LASTC2E_CMD = 0x40,
|
||||
FW_ERROR_CMD = 0x80,
|
||||
FW_DEBUG_CMD = 0x81,
|
||||
@ -3703,6 +4007,7 @@ enum fw_caps_config_hm {
|
||||
#define FW_T4VF_MPS_BASE_ADDR 0x0100
|
||||
#define FW_T4VF_PL_BASE_ADDR 0x0200
|
||||
#define FW_T4VF_MBDATA_BASE_ADDR 0x0240
|
||||
#define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */
|
||||
#define FW_T4VF_CIM_BASE_ADDR 0x0300
|
||||
|
||||
#define FW_T4VF_REGMAP_START 0x0000
|
||||
@ -3751,6 +4056,12 @@ enum fw_caps_config_iscsi {
|
||||
FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
|
||||
FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
|
||||
FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
|
||||
FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
|
||||
FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
|
||||
};
|
||||
|
||||
enum fw_caps_config_tls {
|
||||
FW_CAPS_CONFIG_TLSKEYS = 0x00000001,
|
||||
};
|
||||
|
||||
enum fw_caps_config_fcoe {
|
||||
@ -3782,7 +4093,7 @@ struct fw_caps_config_cmd {
|
||||
__be16 niccaps;
|
||||
__be16 toecaps;
|
||||
__be16 rdmacaps;
|
||||
__be16 r4;
|
||||
__be16 tlscaps;
|
||||
__be16 iscsicaps;
|
||||
__be16 fcoecaps;
|
||||
__be32 cfcsum;
|
||||
@ -3923,6 +4234,8 @@ enum fw_params_param_pfvf {
|
||||
FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
|
||||
FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
|
||||
FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
|
||||
FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
|
||||
FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
|
||||
FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
|
||||
FW_PARAMS_PARAM_PFVF_VIID = 0x24,
|
||||
FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
|
||||
@ -3937,7 +4250,13 @@ enum fw_params_param_pfvf {
|
||||
FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
|
||||
FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
|
||||
FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
|
||||
FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
|
||||
FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
|
||||
FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
|
||||
FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
|
||||
FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
|
||||
FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
|
||||
FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
|
||||
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3947,11 +4266,14 @@ enum fw_params_param_dmaq {
|
||||
FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
|
||||
FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
|
||||
FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
|
||||
FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03,
|
||||
FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
|
||||
FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
|
||||
FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
|
||||
FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
|
||||
FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
|
||||
FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
|
||||
FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
|
||||
FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4003,6 +4325,29 @@ enum fw_params_param_chnet_flags {
|
||||
#define G_FW_PARAMS_PARAM_YZ(x) \
|
||||
(((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
|
||||
|
||||
#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
|
||||
#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
|
||||
#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
|
||||
((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
|
||||
#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
|
||||
(((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
|
||||
M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
|
||||
|
||||
#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
|
||||
#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
|
||||
#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
|
||||
((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
|
||||
#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
|
||||
(((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
|
||||
M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
|
||||
|
||||
#define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0
|
||||
#define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff
|
||||
#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
|
||||
((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
|
||||
#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
|
||||
(((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
|
||||
|
||||
struct fw_params_cmd {
|
||||
__be32 op_to_vfn;
|
||||
__be32 retval_len16;
|
||||
@ -5546,6 +5891,12 @@ enum fw_vi_mac_result {
|
||||
FW_VI_MAC_R_F_ACL_CHECK
|
||||
};
|
||||
|
||||
enum fw_vi_mac_entry_types {
|
||||
FW_VI_MAC_TYPE_EXACTMAC,
|
||||
FW_VI_MAC_TYPE_HASHVEC,
|
||||
FW_VI_MAC_TYPE_RAW,
|
||||
};
|
||||
|
||||
struct fw_vi_mac_cmd {
|
||||
__be32 op_to_viid;
|
||||
__be32 freemacs_to_len16;
|
||||
@ -5557,6 +5908,13 @@ struct fw_vi_mac_cmd {
|
||||
struct fw_vi_mac_hash {
|
||||
__be64 hashvec;
|
||||
} hash;
|
||||
struct fw_vi_mac_raw {
|
||||
__be32 raw_idx_pkd;
|
||||
__be32 data0_pkd;
|
||||
__be32 data1[2];
|
||||
__be64 data0m_pkd;
|
||||
__be32 data1m[2];
|
||||
} raw;
|
||||
} u;
|
||||
};
|
||||
|
||||
@ -5573,12 +5931,11 @@ struct fw_vi_mac_cmd {
|
||||
(((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
|
||||
#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
|
||||
|
||||
#define S_FW_VI_MAC_CMD_HASHVECEN 23
|
||||
#define M_FW_VI_MAC_CMD_HASHVECEN 0x1
|
||||
#define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN)
|
||||
#define G_FW_VI_MAC_CMD_HASHVECEN(x) \
|
||||
(((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN)
|
||||
#define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U)
|
||||
#define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
|
||||
#define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
|
||||
#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
|
||||
#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \
|
||||
(((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
|
||||
|
||||
#define S_FW_VI_MAC_CMD_HASHUNIEN 22
|
||||
#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
|
||||
@ -5612,6 +5969,18 @@ struct fw_vi_mac_cmd {
|
||||
#define G_FW_VI_MAC_CMD_IDX(x) \
|
||||
(((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
|
||||
|
||||
#define S_FW_VI_MAC_CMD_RAW_IDX 16
|
||||
#define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
|
||||
#define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
|
||||
#define G_FW_VI_MAC_CMD_RAW_IDX(x) \
|
||||
(((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
|
||||
|
||||
#define S_FW_VI_MAC_CMD_DATA0 0
|
||||
#define M_FW_VI_MAC_CMD_DATA0 0xffff
|
||||
#define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0)
|
||||
#define G_FW_VI_MAC_CMD_DATA0(x) \
|
||||
(((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
|
||||
|
||||
/* T4 max MTU supported */
|
||||
#define T4_MAX_MTU_SUPPORTED 9600
|
||||
#define FW_RXMODE_MTU_NO_CHG 65535
|
||||
@ -6827,9 +7196,9 @@ struct fw_ptp_cmd {
|
||||
} init;
|
||||
struct fw_ptp_ts {
|
||||
__u8 sc;
|
||||
__u8 r3;
|
||||
__be16 ppb;
|
||||
__be32 r4;
|
||||
__u8 sign;
|
||||
__be16 r3;
|
||||
__be32 ppb;
|
||||
__be64 tm;
|
||||
} ts;
|
||||
} u;
|
||||
@ -7369,7 +7738,8 @@ enum fw_devlog_facility {
|
||||
FW_DEVLOG_FACILITY_FOISCSI = 0x30,
|
||||
FW_DEVLOG_FACILITY_FOFCOE = 0x32,
|
||||
FW_DEVLOG_FACILITY_CHNET = 0x34,
|
||||
FW_DEVLOG_FACILITY_MAX = 0x34
|
||||
FW_DEVLOG_FACILITY_COiSCSI = 0x36,
|
||||
FW_DEVLOG_FACILITY_MAX = 0x38,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -7882,6 +8252,180 @@ enum fw_error_type {
|
||||
FW_ERROR_TYPE_ACL = 0x3,
|
||||
};
|
||||
|
||||
enum fw_dcb_ieee_locations {
|
||||
FW_IEEE_LOC_LOCAL,
|
||||
FW_IEEE_LOC_PEER,
|
||||
FW_IEEE_LOC_OPERATIONAL,
|
||||
};
|
||||
|
||||
struct fw_dcb_ieee_cmd {
|
||||
__be32 op_to_location;
|
||||
__be32 changed_to_len16;
|
||||
union fw_dcbx_stats {
|
||||
struct fw_dcbx_pfc_stats_ieee {
|
||||
__be32 pfc_mbc_pkd;
|
||||
__be32 pfc_willing_to_pfc_en;
|
||||
} dcbx_pfc_stats;
|
||||
struct fw_dcbx_ets_stats_ieee {
|
||||
__be32 cbs_to_ets_max_tc;
|
||||
__be32 pg_table;
|
||||
__u8 pg_percent[8];
|
||||
__u8 tsa[8];
|
||||
} dcbx_ets_stats;
|
||||
struct fw_dcbx_app_stats_ieee {
|
||||
__be32 num_apps_pkd;
|
||||
__be32 r6;
|
||||
__be32 app[4];
|
||||
} dcbx_app_stats;
|
||||
struct fw_dcbx_control {
|
||||
__be32 multi_peer_invalidated;
|
||||
__be32 r5_lo;
|
||||
} dcbx_control;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_PORT 8
|
||||
#define M_FW_DCB_IEEE_CMD_PORT 0x7
|
||||
#define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT)
|
||||
#define G_FW_DCB_IEEE_CMD_PORT(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_FEATURE 2
|
||||
#define M_FW_DCB_IEEE_CMD_FEATURE 0x7
|
||||
#define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE)
|
||||
#define G_FW_DCB_IEEE_CMD_FEATURE(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_LOCATION 0
|
||||
#define M_FW_DCB_IEEE_CMD_LOCATION 0x3
|
||||
#define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION)
|
||||
#define G_FW_DCB_IEEE_CMD_LOCATION(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_CHANGED 20
|
||||
#define M_FW_DCB_IEEE_CMD_CHANGED 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED)
|
||||
#define G_FW_DCB_IEEE_CMD_CHANGED(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
|
||||
#define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_RECEIVED 19
|
||||
#define M_FW_DCB_IEEE_CMD_RECEIVED 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
|
||||
#define G_FW_DCB_IEEE_CMD_RECEIVED(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
|
||||
#define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_APPLY 18
|
||||
#define M_FW_DCB_IEEE_CMD_APPLY 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY)
|
||||
#define G_FW_DCB_IEEE_CMD_APPLY(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
|
||||
#define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_DISABLED 17
|
||||
#define M_FW_DCB_IEEE_CMD_DISABLED 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED)
|
||||
#define G_FW_DCB_IEEE_CMD_DISABLED(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
|
||||
#define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_MORE 16
|
||||
#define M_FW_DCB_IEEE_CMD_MORE 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE)
|
||||
#define G_FW_DCB_IEEE_CMD_MORE(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
|
||||
#define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_PFC_MBC 0
|
||||
#define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
|
||||
#define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
|
||||
#define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_PFC_WILLING 16
|
||||
#define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
|
||||
((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
|
||||
#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
|
||||
#define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8
|
||||
#define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff
|
||||
#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
|
||||
#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_PFC_EN 0
|
||||
#define M_FW_DCB_IEEE_CMD_PFC_EN 0xff
|
||||
#define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
|
||||
#define G_FW_DCB_IEEE_CMD_PFC_EN(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_CBS 16
|
||||
#define M_FW_DCB_IEEE_CMD_CBS 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS)
|
||||
#define G_FW_DCB_IEEE_CMD_CBS(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
|
||||
#define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_ETS_WILLING 8
|
||||
#define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
|
||||
((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
|
||||
#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
|
||||
#define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0
|
||||
#define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff
|
||||
#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
|
||||
#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_NUM_APPS 0
|
||||
#define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7
|
||||
#define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
|
||||
#define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_MULTI_PEER 31
|
||||
#define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
|
||||
#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
|
||||
#define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_INVALIDATED 30
|
||||
#define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1
|
||||
#define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \
|
||||
((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
|
||||
#define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
|
||||
#define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
|
||||
|
||||
/* Hand-written */
|
||||
#define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16
|
||||
#define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff
|
||||
#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
|
||||
#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_APP_SELECT 3
|
||||
#define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7
|
||||
#define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
|
||||
#define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
|
||||
|
||||
#define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0
|
||||
#define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7
|
||||
#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
|
||||
#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \
|
||||
(((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
|
||||
|
||||
|
||||
struct fw_error_cmd {
|
||||
__be32 op_to_type;
|
||||
__be32 len16_pkd;
|
||||
@ -8197,13 +8741,13 @@ enum fw_hdr_chip {
|
||||
|
||||
enum {
|
||||
T4FW_VERSION_MAJOR = 0x01,
|
||||
T4FW_VERSION_MINOR = 0x0e,
|
||||
T4FW_VERSION_MICRO = 0x04,
|
||||
T4FW_VERSION_MINOR = 0x05,
|
||||
T4FW_VERSION_MICRO = 0x1c,
|
||||
T4FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T5FW_VERSION_MAJOR = 0x01,
|
||||
T5FW_VERSION_MINOR = 0x0e,
|
||||
T5FW_VERSION_MICRO = 0x04,
|
||||
T5FW_VERSION_MINOR = 0x05,
|
||||
T5FW_VERSION_MICRO = 0x1c,
|
||||
T5FW_VERSION_BUILD = 0x00,
|
||||
};
|
||||
|
||||
@ -8251,4 +8795,24 @@ enum fw_hdr_flags {
|
||||
FW_HDR_FLAGS_RESET_HALT = 0x00000001,
|
||||
};
|
||||
|
||||
/*
|
||||
* External PHY firmware binary header format
|
||||
*/
|
||||
struct fw_ephy_hdr {
|
||||
__u8 ver;
|
||||
__u8 reserved;
|
||||
__be16 len512; /* bin length in units of 512-bytes */
|
||||
__be32 magic;
|
||||
|
||||
__be16 vendor_id;
|
||||
__be16 device_id;
|
||||
__be32 version;
|
||||
|
||||
__be32 reserved1[4];
|
||||
};
|
||||
|
||||
enum {
|
||||
FW_EPHY_HDR_MAGIC = 0x65706879,
|
||||
};
|
||||
|
||||
#endif /* _T4FW_INTERFACE_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
10510
sys/dev/cxgbe/firmware/t5fw-1.15.28.0.bin.uu
Normal file
10510
sys/dev/cxgbe/firmware/t5fw-1.15.28.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -20,6 +20,12 @@
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
# disable TP_PARA_REG3.RxFragEn
|
||||
reg[0x7d6c] = 0x00000000/0x00007000
|
||||
|
||||
# enable TP_PARA_REG6.EnableCSnd
|
||||
reg[0x7d78] = 0x00000400/0x00000000
|
||||
|
||||
# TP_SHIFT_CNT
|
||||
reg[0x7dc0] = 0x62f8849
|
||||
|
||||
@ -52,6 +58,10 @@
|
||||
mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# ULP_TX_CONFIG
|
||||
reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
|
||||
# TPT error.
|
||||
|
||||
# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
|
||||
# these 4 PFs only. Not used here at all.
|
||||
[function "0"]
|
||||
@ -176,7 +186,7 @@
|
||||
|
||||
[fini]
|
||||
version = 0x1
|
||||
checksum = 0x6b54f66d
|
||||
checksum = 0x7044b7fd
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
@ -121,6 +121,12 @@
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
# disable TP_PARA_REG3.RxFragEn
|
||||
reg[0x7d6c] = 0x00000000/0x00007000
|
||||
|
||||
# enable TP_PARA_REG6.EnableCSnd
|
||||
reg[0x7d78] = 0x00000400/0x00000000
|
||||
|
||||
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
|
||||
|
||||
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
|
||||
@ -176,6 +182,10 @@
|
||||
mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# ULP_TX_CONFIG
|
||||
reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
|
||||
# TPT error.
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
@ -592,7 +602,7 @@
|
||||
|
||||
[fini]
|
||||
version = 0x1425001c
|
||||
checksum = 0xb1c3ae38
|
||||
checksum = 0xa4a80156
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER= 1.14.4.0
|
||||
T4FW_VER= 1.15.28.0
|
||||
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES+= t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER= 1.14.4.0
|
||||
T5FW_VER= 1.15.28.0
|
||||
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES+= t5fw.fw
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user