Use PTR_* macros to deal with pointers.
This commit is contained in:
Warner Losh
parent
df92abe375
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de13b5d0f9
@ -139,12 +139,14 @@ VECTOR_END(MipsTLBMiss)
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*----------------------------------------------------------------------------
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*/
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MipsDoTLBMiss:
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#xxx mips64 unsafe?
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#ifndef SMP
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lui k1, %hi(_C_LABEL(pcpup))
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#endif
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#k0 already has BadVA
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bltz k0, 1f #02: k0<0 -> 1f (kernel fault)
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srl k0, k0, SEGSHIFT - 2 #03: k0=seg offset (almost)
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#xxx mips64 unsafe?
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#ifdef SMP
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GET_CPU_PCPU(k1)
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#else
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@ -153,6 +155,7 @@ MipsDoTLBMiss:
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lw k1, PC_SEGBASE(k1)
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beqz k1, 2f #05: make sure segbase is not null
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andi k0, k0, 0x7fc #06: k0=seg offset (mask 0x3)
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#xxx mips64 unsafe?
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addu k1, k0, k1 #07: k1=seg entry address
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lw k1, 0(k1) #08: k1=seg entry
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mfc0 k0, COP_0_BAD_VADDR #09: k0=bad address (again)
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@ -160,6 +163,7 @@ MipsDoTLBMiss:
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srl k0, PGSHIFT - 2 #0b: k0=VPN (aka va>>10)
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andi k0, k0, ((NPTEPG/2) - 1) << 3 #0c: k0=page tab offset
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#xxx mips64 unsafe?
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addu k1, k1, k0 #0d: k1=pte address
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lw k0, 0(k1) #0e: k0=lo0 pte
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lw k1, 4(k1) #0f: k1=lo1 pte
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@ -199,8 +203,8 @@ VECTOR(MipsException, unknown)
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and k1, k1, CR_EXC_CODE # Mask out the cause bits.
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or k1, k1, k0 # change index to user table
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1:
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la k0, _C_LABEL(machExceptionTable) # get base of the jump table
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addu k0, k0, k1 # Get the address of the
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PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table
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PTR_ADDU k0, k0, k1 # Get the address of the
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# function entry. Note that
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# the cause is already
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# shifted left by 2 bits so
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@ -315,10 +319,10 @@ SlowFault:
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SAVE_REG(ra, RA, sp) ;\
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SAVE_REG(a2, BADVADDR, sp) ;\
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SAVE_REG(a3, PC, sp) ;\
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addu v0, sp, KERN_EXC_FRAME_SIZE ;\
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PTR_ADDU v0, sp, KERN_EXC_FRAME_SIZE ;\
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SAVE_REG(v0, SP, sp) ;\
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CLEAR_STATUS ;\
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addu a0, sp, STAND_ARG_SIZE ;\
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PTR_ADDU a0, sp, STAND_ARG_SIZE ;\
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ITLBNOPFIX
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#define RESTORE_REG(reg, offs, base) \
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@ -361,7 +365,7 @@ SlowFault:
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RESTORE_REG(s8, S8, sp) ;\
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RESTORE_REG(gp, GP, sp) ;\
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RESTORE_REG(ra, RA, sp) ;\
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addu sp, sp, KERN_EXC_FRAME_SIZE;\
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PTR_ADDU sp, sp, KERN_EXC_FRAME_SIZE;\
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mtc0 k0, COP_0_STATUS_REG
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@ -384,8 +388,8 @@ NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra)
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/*
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* Call the exception handler. a0 points at the saved frame.
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*/
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la gp, _C_LABEL(_gp)
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la k0, _C_LABEL(trap)
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PTR_LA gp, _C_LABEL(_gp)
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PTR_LA k0, _C_LABEL(trap)
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jalr k0
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sw a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp) # for debugging
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@ -481,20 +485,20 @@ NNON_LEAF(MipsUserGenException, STAND_FRAME_SIZE, ra)
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SAVE_U_PCB_REG(a2, BADVADDR, k1)
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SAVE_U_PCB_REG(a3, PC, k1)
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sw a3, STAND_RA_OFFSET(sp) # for debugging
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la gp, _C_LABEL(_gp) # switch to kernel GP
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PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
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# Turn off fpu and enter kernel mode
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and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB)
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#ifdef TARGET_OCTEON
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or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
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#endif
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mtc0 t0, COP_0_STATUS_REG
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addu a0, k1, U_PCB_REGS
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PTR_ADDU a0, k1, U_PCB_REGS
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ITLBNOPFIX
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/*
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* Call the exception handler.
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*/
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la k0, _C_LABEL(trap)
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PTR_LA k0, _C_LABEL(trap)
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jalr k0
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nop
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@ -615,9 +619,9 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
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/*
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* Call the interrupt handler.
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*/
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la gp, _C_LABEL(_gp)
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addu a0, sp, STAND_ARG_SIZE
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la k0, _C_LABEL(cpu_intr)
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PTR_LA gp, _C_LABEL(_gp)
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PTR_ADDU a0, sp, STAND_ARG_SIZE
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PTR_LA k0, _C_LABEL(cpu_intr)
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jalr k0
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sw a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp)
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/* Why no AST processing here? */
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@ -717,7 +721,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
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SAVE_U_PCB_REG(a1, CAUSE, k1)
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SAVE_U_PCB_REG(a3, PC, k1) # PC in a3, note used later!
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subu sp, k1, STAND_FRAME_SIZE # switch to kernel SP
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la gp, _C_LABEL(_gp) # switch to kernel GP
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PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
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# Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
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and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
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@ -726,11 +730,11 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
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#endif
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mtc0 t0, COP_0_STATUS_REG
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ITLBNOPFIX
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addu a0, k1, U_PCB_REGS
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PTR_ADDU a0, k1, U_PCB_REGS
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/*
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* Call the interrupt handler.
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*/
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la k0, _C_LABEL(cpu_intr)
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PTR_LA k0, _C_LABEL(cpu_intr)
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jalr k0
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sw a3, STAND_RA_OFFSET(sp) # for debugging
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@ -879,6 +883,7 @@ NLEAF(MipsKernTLBInvalidException)
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2:
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srl k0, 20 # k0=seg offset (almost)
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andi k0, k0, 0xffc # k0=seg offset (mask 0x3)
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#xxx mips64 unsafe?
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addu k1, k0, k1 # k1=seg entry address
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lw k1, 0(k1) # k1=seg entry
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mfc0 k0, COP_0_BAD_VADDR # k0=bad address (again)
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@ -886,6 +891,7 @@ NLEAF(MipsKernTLBInvalidException)
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srl k0, k0, PGSHIFT-2
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andi k0, k0, 0xffc # compute offset from index
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tlbp # Probe the invalid entry
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#xxx mips64 unsafe?
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addu k1, k1, k0
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and k0, k0, 4 # check even/odd page
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nop # required for QED 5230
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@ -951,6 +957,7 @@ NLEAF(MipsUserTLBInvalidException)
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sltu k1, k0, k1
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beqz k1, _C_LABEL(MipsUserGenException)
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nop
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#xxx mips64 unsafe?
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#ifdef SMP
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GET_CPU_PCPU(k1)
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#else
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@ -963,6 +970,7 @@ NLEAF(MipsUserTLBInvalidException)
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2:
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srl k0, 20 # k0=seg offset (almost)
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andi k0, k0, 0xffc # k0=seg offset (mask 0x3)
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#xxx mips64 unsafe?
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addu k1, k0, k1 # k1=seg entry address
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lw k1, 0(k1) # k1=seg entry
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mfc0 k0, COP_0_BAD_VADDR # k0=bad address (again)
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@ -970,6 +978,7 @@ NLEAF(MipsUserTLBInvalidException)
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srl k0, k0, PGSHIFT-2
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andi k0, k0, 0xffc # compute offset from index
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tlbp # Probe the invalid entry
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#xxx mips64 unsafe?
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addu k1, k1, k0
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and k0, k0, 4 # check even/odd page
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nop # required for QED 5230
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@ -1053,12 +1062,14 @@ NLEAF(MipsTLBMissException)
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lw k1, %lo(_C_LABEL(kernel_segmap))(k1) # k1=segment tab base
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beq k1, zero, _C_LABEL(MipsKernGenException) # ==0 -- no seg tab
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andi k0, k0, 0xffc # k0=seg offset (mask 0x3)
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#xxx mips64 unsafe
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addu k1, k0, k1 # k1=seg entry address
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lw k1, 0(k1) # k1=seg entry
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mfc0 k0, COP_0_BAD_VADDR # k0=bad address (again)
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beq k1, zero, _C_LABEL(MipsKernGenException) # ==0 -- no page table
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srl k0, 10 # k0=VPN (aka va>>10)
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andi k0, k0, 0xff8 # k0=page tab offset
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#xxx mips64 unsafe
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addu k1, k1, k0 # k1=pte address
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lw k0, 0(k1) # k0=lo0 pte
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lw k1, 4(k1) # k1=lo1 pte
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@ -1083,31 +1094,31 @@ sys_stk_chk:
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nop
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# stack overflow
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la a0, _C_LABEL(_start) - START_FRAME - 8 # set sp to a valid place
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PTR_LA a0, _C_LABEL(_start) - START_FRAME - 8 # set sp to a valid place
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sw sp, 24(a0)
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move sp, a0
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la a0, 1f
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PTR_LA a0, 1f
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mfc0 a2, COP_0_STATUS_REG
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mfc0 a3, COP_0_CAUSE_REG
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_MFC0 a1, COP_0_EXC_PC
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sw a2, 16(sp)
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sw a3, 20(sp)
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move a2, ra
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la k0, _C_LABEL(printf)
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PTR_LA k0, _C_LABEL(printf)
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jalr k0
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mfc0 a3, COP_0_BAD_VADDR
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la sp, _C_LABEL(_start) - START_FRAME # set sp to a valid place
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PTR_LA sp, _C_LABEL(_start) - START_FRAME # set sp to a valid place
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#if !defined(SMP) && defined(DDB)
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la a0, 2f
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la k0, _C_LABEL(trapDump)
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PTR_LA a0, 2f
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PTR_LA k0, _C_LABEL(trapDump)
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jalr k0
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nop
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li a0, 0
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lw a1, _C_LABEL(num_tlbentries)
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la k0, _C_LABEL(db_dump_tlb)
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PTR_LA k0, _C_LABEL(db_dump_tlb)
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jalr k0
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addu a1, -1
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@ -1184,11 +1195,12 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, ra)
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*/
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sw a2, STAND_FRAME_SIZE + 8(sp)
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GET_CPU_PCPU(a0)
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#mips64 unsafe?
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lw a0, PC_CURPCB(a0)
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addu a0, a0, U_PCB_REGS # first arg is ptr to CPU registers
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PTR_ADDU a0, a0, U_PCB_REGS # first arg is ptr to CPU registers
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move a1, a2 # second arg is instruction PC
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move a2, t1 # third arg is floating point CSR
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la t3, _C_LABEL(MipsEmulateBranch) # compute PC after branch
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PTR_LA t3, _C_LABEL(MipsEmulateBranch) # compute PC after branch
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jalr t3 # compute PC after branch
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move a3, zero # fourth arg is FALSE
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/*
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@ -1204,6 +1216,7 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, ra)
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*/
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1:
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lw a0, 0(a2) # a0 = coproc instruction
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#xxx mips64 unsafe?
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addu v0, a2, 4 # v0 = next pc
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2:
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GET_CPU_PCPU(t2)
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@ -1224,7 +1237,7 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, ra)
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lw a0, PC_CURTHREAD(a0) # get current thread
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cfc1 a2, FPC_CSR # code = FP execptions
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ctc1 zero, FPC_CSR # Clear exceptions
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la t3, _C_LABEL(trapsignal)
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PTR_LA t3, _C_LABEL(trapsignal)
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jalr t3
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li a1, SIGFPE
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b FPReturn
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@ -1234,7 +1247,7 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, ra)
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* Finally, we can call MipsEmulateFP() where a0 is the instruction to emulate.
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*/
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4:
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la t3, _C_LABEL(MipsEmulateFP)
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PTR_LA t3, _C_LABEL(MipsEmulateFP)
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jalr t3
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nop
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@ -1248,26 +1261,9 @@ FPReturn:
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mtc0 t0, COP_0_STATUS_REG
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ITLBNOPFIX
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j ra
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addu sp, sp, STAND_FRAME_SIZE
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PTR_ADDU sp, sp, STAND_FRAME_SIZE
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END(MipsFPTrap)
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#if 0
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/*
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* Atomic ipending update
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*/
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LEAF(set_sint)
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la v1, ipending
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1:
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ll v0, 0(v1)
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or v0, a0
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sc v0, 0(v1)
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beqz v0, 1b
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j ra
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nop
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END(set_sint)
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#endif
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/*
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* Interrupt counters for vmstat.
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*/
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@ -1294,7 +1290,7 @@ eintrcnt:
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*/
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.text
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VECTOR(MipsCache, unknown)
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la k0, _C_LABEL(MipsCacheException)
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PTR_LA k0, _C_LABEL(MipsCacheException)
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li k1, MIPS_PHYS_MASK
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and k0, k1
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li k1, MIPS_UNCACHED_MEMORY_ADDR
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@ -1313,8 +1309,8 @@ VECTOR_END(MipsCache)
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NESTED_NOPROFILE(MipsCacheException, KERN_EXC_FRAME_SIZE, ra)
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.set noat
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.mask 0x80000000, -4
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la k0, _C_LABEL(panic) # return to panic
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la a0, 9f # panicstr
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PTR_LA k0, _C_LABEL(panic) # return to panic
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PTR_LA a0, 9f # panicstr
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_MFC0 a1, COP_0_ERROR_PC
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mfc0 a2, COP_0_CACHE_ERR # 3rd arg cache error
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