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mlx5_core: Import PDDR register definitions

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PDDR (Port Diagnostics Database Register) is used to read the physical
layer debug database, which contains helpful troubleshooting information
regarding the state of the link.

PDDR register can only be queried when PCAM register reports it as
supported in its register mask. A new helper macro was added to
the MLX5_CAP_* infrastructure in order to access this mask.

Sponsored by:	Mellanox Technologies - Nvidia
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2020-08-31 16:23:51 +00:00
parent 76cc4c2047
commit e088db5eae
3 changed files with 74 additions and 18 deletions
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1
sys/dev/mlx5/driver.h
View File

@ -145,6 +145,7 @@ enum {
MLX5_REG_PMPE = 0x5010,
MLX5_REG_PMAOS = 0x5012,
MLX5_REG_PPLM = 0x5023,
MLX5_REG_PDDR = 0x5031,
MLX5_REG_PBSR = 0x5038,
MLX5_REG_PCAM = 0x507f,
MLX5_REG_NODE_DESC = 0x6001,

29
sys/dev/mlx5/mlx5_core/mlx5_core.h
View File

@ -79,6 +79,35 @@ enum mlx5_semaphore_space_address {
struct mlx5_core_dev;
enum mlx5_pddr_page_select {
MLX5_PDDR_OPERATIONAL_INFO_PAGE = 0x0,
MLX5_PDDR_TROUBLESHOOTING_INFO_PAGE = 0x1,
MLX5_PDDR_MODULE_INFO_PAGE = 0x3,
};
enum mlx5_pddr_monitor_opcodes {
MLX5_LINK_NO_ISSUE_OBSERVED = 0x0,
MLX5_LINK_PORT_CLOSED = 0x1,
MLX5_LINK_AN_FAILURE = 0x2,
MLX5_LINK_TRAINING_FAILURE = 0x5,
MLX5_LINK_LOGICAL_MISMATCH = 0x9,
MLX5_LINK_REMOTE_FAULT_INDICATION = 0xe,
MLX5_LINK_BAD_SIGNAL_INTEGRITY = 0xf,
MLX5_LINK_CABLE_COMPLIANCE_CODE_MISMATCH = 0x10,
MLX5_LINK_INTERNAL_ERR = 0x17,
MLX5_LINK_INFO_NOT_AVAIL = 0x3ff,
MLX5_LINK_CABLE_UNPLUGGED = 0x400,
MLX5_LINK_LONG_RANGE_FOR_NON_MLX_CABLE = 0x401,
MLX5_LINK_BUS_STUCK = 0x402,
MLX5_LINK_UNSUPP_EEPROM = 0x403,
MLX5_LINK_PART_NUM_LIST = 0x404,
MLX5_LINK_UNSUPP_CABLE = 0x405,
MLX5_LINK_MODULE_TEMP_SHUTDOWN = 0x406,
MLX5_LINK_SHORTED_CABLE = 0x407,
MLX5_LINK_POWER_BUDGET_EXCEEDED = 0x408,
MLX5_LINK_MNG_FORCED_DOWN = 0x409,
};
int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
int mlx5_query_board_id(struct mlx5_core_dev *dev);
int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,

62
sys/dev/mlx5/mlx5_ifc.h
View File

@ -872,23 +872,6 @@ struct mlx5_ifc_pddr_module_info_bits {
u8 reserved_at_4c0[0x300];
};
union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
u8 reserved_at_0[0x7c0];
};
struct mlx5_ifc_pddr_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];
u8 pnat[0x2];
u8 reserved_at_12[0xe];
u8 reserved_at_20[0x18];
u8 page_select[0x8];
union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
};
struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 csum_cap[0x1];
u8 vlan_cap[0x1];
@ -8755,7 +8738,10 @@ struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
u8 port_access_reg_cap_mask_127_to_96[0x20];
u8 port_access_reg_cap_mask_95_to_64[0x20];
u8 port_access_reg_cap_mask_63_to_36[0x1c];
u8 reserved_at_40[0xe];
u8 pddr[0x1];
u8 reserved_at_4f[0xd];
u8 pplm[0x1];
u8 port_access_reg_cap_mask_34_to_32[0x3];
@ -10347,6 +10333,46 @@ struct mlx5_ifc_mpcnt_reg_ext_bits {
union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
};
struct mlx5_ifc_monitor_opcodes_layout_bits {
u8 reserved_at_0[0x10];
u8 monitor_opcode[0x10];
};
union mlx5_ifc_pddr_status_opcode_bits {
struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
u8 reserved_at_0[0x20];
};
struct mlx5_ifc_troubleshooting_info_page_layout_bits {
u8 reserved_at_0[0x10];
u8 group_opcode[0x10];
union mlx5_ifc_pddr_status_opcode_bits status_opcode;
u8 user_feedback_data[0x10];
u8 user_feedback_index[0x10];
u8 status_message[0x760];
};
union mlx5_ifc_pddr_page_data_bits {
struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
u8 reserved_at_0[0x7c0];
};
struct mlx5_ifc_pddr_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];
u8 pnat[0x2];
u8 reserved_at_12[0xe];
u8 reserved_at_20[0x18];
u8 page_select[0x8];
union mlx5_ifc_pddr_page_data_bits page_data;
};
enum {
MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
MLX5_MPEIN_PWR_STATUS_INVALID = 0,