Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada SoC family. Current in-tree support for PJ4Bv6 will not work and also there should be no platforms in active use that would incorporate that CPU revision.
This commit is contained in:
Zbigniew Bodek
parent
d7b0107591
commit
e0b4b3a74f
@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
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pj4bv7_setup /* cpu setup */
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};
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struct cpu_functions pj4bv6_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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arm11_drain_writebuf, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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pj4b_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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arm11_tlb_flushID, /* tlb_flushID */
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arm11_tlb_flushID_SE, /* tlb_flushID_SE */
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arm11_tlb_flushI, /* tlb_flushI */
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arm11_tlb_flushI_SE, /* tlb_flushI_SE */
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arm11_tlb_flushD, /* tlb_flushD */
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arm11_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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armv6_icache_sync_all, /* icache_sync_all */
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pj4b_icache_sync_range, /* icache_sync_range */
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armv6_dcache_wbinv_all, /* dcache_wbinv_all */
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pj4b_dcache_wbinv_range, /* dcache_wbinv_range */
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pj4b_dcache_inv_range, /* dcache_inv_range */
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pj4b_dcache_wb_range, /* dcache_wb_range */
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armv6_idcache_wbinv_all, /* idcache_wbinv_all */
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pj4b_idcache_wbinv_range, /* idcache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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/* Other functions */
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pj4b_drain_readbuf, /* flush_prefetchbuf */
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arm11_drain_writebuf, /* drain_writebuf */
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pj4b_flush_brnchtgt_all, /* flush_brnchtgt_C */
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pj4b_flush_brnchtgt_va, /* flush_brnchtgt_E */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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cpufunc_null_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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arm11_context_switch, /* context_switch */
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pj4bv6_setup /* cpu setup */
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};
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#endif /* CPU_MV_PJ4B */
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#ifdef CPU_SA110
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@ -1497,27 +1438,14 @@ set_cpufuncs()
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#endif /* CPU_CORTEXA */
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#if defined(CPU_MV_PJ4B)
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if (cputype == CPU_ID_MV88SV581X_V6 ||
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cputype == CPU_ID_MV88SV581X_V7 ||
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if (cputype == CPU_ID_MV88SV581X_V7 ||
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cputype == CPU_ID_MV88SV584X_V7 ||
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cputype == CPU_ID_ARM_88SV581X_V6 ||
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cputype == CPU_ID_ARM_88SV581X_V7) {
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if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)
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cpufuncs = pj4bv7_cpufuncs;
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else
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cpufuncs = pj4bv6_cpufuncs;
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get_cachetype_cp15();
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pmap_pte_init_mmu_v6();
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goto out;
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} else if (cputype == CPU_ID_ARM_88SV584X_V6 ||
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cputype == CPU_ID_MV88SV584X_V6) {
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cpufuncs = pj4bv6_cpufuncs;
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get_cachetype_cp15();
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pmap_pte_init_mmu_v6();
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goto out;
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}
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#endif /* CPU_MV_PJ4B */
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#ifdef CPU_SA110
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if (cputype == CPU_ID_SA110) {
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@ -2446,44 +2374,6 @@ arm11x6_setup(char *args)
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#endif /* CPU_ARM1136 || CPU_ARM1176 */
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#ifdef CPU_MV_PJ4B
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void
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pj4bv6_setup(char *args)
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{
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int cpuctrl;
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pj4b_config();
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cpuctrl = CPU_CONTROL_MMU_ENABLE;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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#endif
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cpuctrl |= CPU_CONTROL_DC_ENABLE;
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cpuctrl |= (0xf << 3);
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#ifdef __ARMEB__
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cpuctrl |= CPU_CONTROL_BEND_ENABLE;
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#endif
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cpuctrl |= CPU_CONTROL_SYST_ENABLE;
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cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
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cpuctrl |= CPU_CONTROL_IC_ENABLE;
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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cpuctrl |= (0x5 << 16);
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cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
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/* XXX not yet */
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/* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
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/* Make sure caches are clean. */
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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/* Set the control register */
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ctrl = cpuctrl;
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cpu_control(0xffffffff, cpuctrl);
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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}
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void
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pj4bv7_setup(args)
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char *args;
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@ -34,9 +34,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/param.h>
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.Lpj4b_cache_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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.Lpj4b_sf_ctrl_reg:
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.word 0xf1021820
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@ -52,135 +49,6 @@ ENTRY(pj4b_setttb)
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RET
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END(pj4b_setttb)
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ENTRY_NP(armv6_icache_sync_all)
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache cleaning code.
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
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mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv6_icache_sync_all)
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ENTRY(pj4b_icache_sync_range)
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sub r1, r1, #1
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add r1, r0, r1
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mcrr p15, 0, r1, r0, c5 /* invalidate IC range */
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mcrr p15, 0, r1, r0, c12 /* clean DC range */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(pj4b_icache_sync_range)
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ENTRY(pj4b_dcache_inv_range)
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ldr ip, .Lpj4b_cache_line_size
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */
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1:
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mcr p15, 0, r0, c7, c6, 1
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(pj4b_dcache_inv_range)
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ENTRY(armv6_idcache_wbinv_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */
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mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv6_idcache_wbinv_all)
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ENTRY(armv6_dcache_wbinv_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv6_dcache_wbinv_all)
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ENTRY(pj4b_idcache_wbinv_range)
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ldr ip, .Lpj4b_cache_line_size
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
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1:
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#ifdef SMP
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/* Request for ownership */
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ldr r2, [r0]
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str r2, [r0]
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#endif
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mcr p15, 0, r0, c7, c5, 1
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mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(pj4b_idcache_wbinv_range)
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ENTRY(pj4b_dcache_wbinv_range)
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ldr ip, .Lpj4b_cache_line_size
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
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1:
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#ifdef SMP
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/* Request for ownership */
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ldr r2, [r0]
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str r2, [r0]
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#endif
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mcr p15, 0, r0, c7, c14, 1
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(pj4b_dcache_wbinv_range)
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ENTRY(pj4b_dcache_wb_range)
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ldr ip, .Lpj4b_cache_line_size
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
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1:
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#ifdef SMP
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/* Request for ownership */
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ldr r2, [r0]
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str r2, [r0]
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#endif
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mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(pj4b_dcache_wb_range)
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ENTRY(pj4b_drain_readbuf)
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mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
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RET
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@ -323,18 +323,10 @@ const struct cpuidtab cpuids[] = {
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{ CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD",
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generic_steppings },
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{ CPU_ID_MV88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
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generic_steppings },
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{ CPU_ID_ARM_88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
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generic_steppings },
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{ CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
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generic_steppings },
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{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
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generic_steppings },
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{ CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
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generic_steppings },
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{ CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
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generic_steppings },
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{ CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
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generic_steppings },
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@ -173,14 +173,10 @@
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#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
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#endif
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#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */
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#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
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#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */
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#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
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/* Marvell's CPUIDs with ARM ID in implementor field */
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#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
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#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
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#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */
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#define CPU_ID_FA526 0x66015260
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#define CPU_ID_FA626TE 0x66056260
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@ -482,14 +482,6 @@ void arm11_drain_writebuf (void);
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void pj4b_setttb (u_int);
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void pj4b_icache_sync_range (vm_offset_t, vm_size_t);
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void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void pj4b_dcache_inv_range (vm_offset_t, vm_size_t);
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void pj4b_dcache_wb_range (vm_offset_t, vm_size_t);
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void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void pj4b_drain_readbuf (void);
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void pj4b_flush_brnchtgt_all (void);
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void pj4b_flush_brnchtgt_va (u_int);
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@ -523,7 +515,6 @@ void armv7_drain_writebuf (void);
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void armv7_sev (void);
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u_int armv7_auxctrl (u_int, u_int);
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void pj4bv7_setup (char *string);
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void pj4bv6_setup (char *string);
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void pj4b_config (void);
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int get_core_id (void);
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