Optimise host channel disabling:
- For non-periodic traffic we only need to wait two SOFs before disabling the channel. - Make sure we release the TX FIFO tracking level after the host channel is disabled. - Make sure the host channel state gets reset/disabled initially. - Two minor code style changes. MFC after: 2 weeks
This commit is contained in:
Hans Petter Selasky
parent
fa5ff59a78
commit
e2192fdfc6
@ -141,6 +141,7 @@ static void dwc_otg_do_poll(struct usb_bus *);
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static void dwc_otg_standard_done(struct usb_xfer *);
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static void dwc_otg_root_intr(struct dwc_otg_softc *);
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static void dwc_otg_interrupt_poll(struct dwc_otg_softc *);
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static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t);
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/*
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* Here is a configuration that the chip supports.
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@ -210,6 +211,13 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
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return (EINVAL);
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}
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/* disable any leftover host channels */
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for (x = 0; x != sc->sc_host_ch_max; x++) {
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if (sc->sc_chan_state[x].wait_sof == 0)
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continue;
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dwc_otg_host_channel_disable(sc, x);
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}
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if (mode == DWC_MODE_HOST) {
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/* reset active endpoints */
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@ -236,6 +244,9 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
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((fifo_size / 4) << 16) |
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(tx_start / 4));
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/* reset host channel state */
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memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
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/* reset FIFO TX levels */
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sc->sc_tx_cur_p_level = 0;
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sc->sc_tx_cur_np_level = 0;
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@ -326,6 +337,9 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
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/* reset periodic and non-periodic FIFO TX size */
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sc->sc_tx_max_size = fifo_size;
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/* reset host channel state */
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memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
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/* reset FIFO TX levels */
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sc->sc_tx_cur_p_level = 0;
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sc->sc_tx_cur_np_level = 0;
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@ -569,7 +583,7 @@ dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
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}
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static uint8_t
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dwc_otg_host_channel_alloc(struct dwc_otg_td *td, uint8_t which)
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dwc_otg_host_channel_alloc(struct dwc_otg_td *td, uint8_t which, uint8_t is_out)
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{
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struct dwc_otg_softc *sc;
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uint32_t tx_p_size;
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@ -587,11 +601,7 @@ dwc_otg_host_channel_alloc(struct dwc_otg_td *td, uint8_t which)
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sc = DWC_OTG_PC2SC(td->pc);
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/* compute needed TX FIFO size */
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if (td->ep_type == UE_CONTROL) {
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/* RX and TX transactions */
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tx_p_size = 0;
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tx_np_size = td->max_packet_size;
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} else if ((td->hcchar & HCCHAR_EPDIR) == HCCHAR_EPDIR_OUT) {
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if (is_out != 0) {
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if (td->ep_type == UE_INTERRUPT ||
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td->ep_type == UE_ISOCHRONOUS) {
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tx_p_size = td->max_packet_size;
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@ -669,12 +679,22 @@ dwc_otg_host_channel_free(struct dwc_otg_td *td, uint8_t which)
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/* get pointer to softc */
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sc = DWC_OTG_PC2SC(td->pc);
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sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX;
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sc->sc_chan_state[x].allocated = 0;
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/* keep track of used TX FIFO, if any */
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sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size;
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sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size;
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/*
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* We need to let programmed host channels run till complete
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* else the host channel will stop functioning. Assume that
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* after a fixed given amount of time the host channel is no
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* longer doing any USB traffic:
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*/
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if (td->ep_type == UE_ISOCHRONOUS || td->ep_type == UE_INTERRUPT) {
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/* double buffered */
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sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX;
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} else {
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/* single buffered */
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sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN;
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}
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sc->sc_chan_state[x].allocated = 0;
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/* ack any pending messages */
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if (sc->sc_last_rx_status != 0 &&
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@ -810,7 +830,7 @@ dwc_otg_host_setup_tx(struct dwc_otg_td *td)
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, 0)) {
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if (dwc_otg_host_channel_alloc(td, 0, 1)) {
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td->state = DWC_CHAN_ST_START;
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goto busy;
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}
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@ -863,7 +883,7 @@ dwc_otg_host_setup_tx(struct dwc_otg_td *td)
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goto complete;
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, 0)) {
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if (dwc_otg_host_channel_alloc(td, 0, 0)) {
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td->state = DWC_CHAN_ST_WAIT_C_PKT;
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goto busy;
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}
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@ -1322,7 +1342,7 @@ dwc_otg_host_data_rx(struct dwc_otg_td *td)
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, td->tt_channel_tog)) {
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if (dwc_otg_host_channel_alloc(td, td->tt_channel_tog, 0)) {
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td->state = DWC_CHAN_ST_WAIT_C_PKT;
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goto busy;
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}
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@ -1404,7 +1424,7 @@ dwc_otg_host_data_rx(struct dwc_otg_td *td)
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, 0)) {
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if (dwc_otg_host_channel_alloc(td, 0, 0)) {
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td->state = DWC_CHAN_ST_START;
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goto busy;
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}
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@ -1616,8 +1636,7 @@ dwc_otg_host_data_tx(struct dwc_otg_td *td)
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td->did_nak = 1;
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td->tt_scheduled = 0;
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goto send_pkt;
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}
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if (hcint & (HCINT_ACK | HCINT_NYET)) {
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} else if (hcint & (HCINT_ACK | HCINT_NYET)) {
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td->offset += td->tx_bytes;
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td->remainder -= td->tx_bytes;
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td->toggle ^= 1;
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@ -1642,8 +1661,7 @@ dwc_otg_host_data_tx(struct dwc_otg_td *td)
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td->did_nak = 1;
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td->tt_scheduled = 0;
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goto send_pkt;
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}
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if (hcint & (HCINT_ACK | HCINT_NYET))
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} else if (hcint & (HCINT_ACK | HCINT_NYET))
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goto send_cpkt;
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break;
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@ -1698,7 +1716,7 @@ dwc_otg_host_data_tx(struct dwc_otg_td *td)
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/* FALLTHROUGH */
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case DWC_CHAN_ST_TX_PKT_ISOC:
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if (dwc_otg_host_channel_alloc(td, 0))
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if (dwc_otg_host_channel_alloc(td, 0, 1))
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break;
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channel = td->channel[0];
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goto send_isoc_pkt;
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@ -1731,7 +1749,7 @@ dwc_otg_host_data_tx(struct dwc_otg_td *td)
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, 0)) {
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if (dwc_otg_host_channel_alloc(td, 0, 1)) {
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td->state = DWC_CHAN_ST_START;
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goto busy;
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}
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@ -1896,7 +1914,7 @@ dwc_otg_host_data_tx(struct dwc_otg_td *td)
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}
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/* allocate a new channel */
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if (dwc_otg_host_channel_alloc(td, td->tt_channel_tog)) {
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if (dwc_otg_host_channel_alloc(td, td->tt_channel_tog, 0)) {
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td->state = DWC_CHAN_ST_WAIT_C_PKT;
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goto busy;
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}
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@ -2306,6 +2324,31 @@ dwc_otg_timer_stop(struct dwc_otg_softc *sc)
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usb_callout_stop(&sc->sc_timer);
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}
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static void
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dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x)
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{
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uint32_t hcchar;
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hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
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/* disable host channel, if any */
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if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) {
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/* disable channel */
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DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
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HCCHAR_CHENA | HCCHAR_CHDIS);
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/* wait for chip to get its brains in order */
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sc->sc_chan_state[x].wait_sof = 2;
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}
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/* release TX FIFO usage, if any */
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sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size;
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sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size;
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/* don't release TX FIFO usage twice */
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sc->sc_chan_state[x].tx_p_size = 0;
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sc->sc_chan_state[x].tx_np_size = 0;
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}
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static uint8_t
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dwc_otg_update_host_transfer_schedule(struct dwc_otg_softc *sc)
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{
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@ -2326,26 +2369,12 @@ dwc_otg_update_host_transfer_schedule(struct dwc_otg_softc *sc)
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TAILQ_INIT(&head);
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for (x = 0; x != sc->sc_host_ch_max; x++) {
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uint32_t hcchar;
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if (sc->sc_chan_state[x].wait_sof == 0)
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continue;
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sc->sc_needsof = 1;
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sc->sc_chan_state[x].wait_sof--;
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if (sc->sc_chan_state[x].wait_sof != 0)
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continue;
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hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
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/* disable host channel, if any */
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if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) {
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/* disable channel */
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DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
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HCCHAR_CHENA | HCCHAR_CHDIS);
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/* wait for chip to get its brains in order */
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sc->sc_chan_state[x].wait_sof = 2;
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}
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if (--(sc->sc_chan_state[x].wait_sof) == 0)
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dwc_otg_host_channel_disable(sc, x);
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}
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if ((temp & 7) == 0) {
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@ -36,6 +36,7 @@
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#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */
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#define DWC_OTG_TT_SLOT_MAX 8
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#define DWC_OTG_SLOT_IDLE_MAX 4
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#define DWC_OTG_SLOT_IDLE_MIN 2
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#define DWC_OTG_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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