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Join chip depended methods for arge0 and arge1 into single call with unit.

Browse Source 
Approved by: adrian (mentor)
This commit is contained in:
Aleksandr Rybalko 2011-11-27 11:15:59 +00:00
parent ee295a1f5b
commit e319e32c90
5 changed files with 101 additions and 118 deletions
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71
sys/mips/atheros/ar71xx_chip.c
View File

@ -140,7 +140,7 @@ ar71xx_chip_device_stopped(uint32_t mask)
/* Speed is either 10, 100 or 1000 */ /* Speed is either 10, 100 or 1000 */
static void static void
ar71xx_chip_set_pll_ge0(int speed) ar71xx_chip_set_pll_ge(int unit, int speed)
{ {
uint32_t pll; uint32_t pll;
@ -155,46 +155,43 @@ ar71xx_chip_set_pll_ge0(int speed)
pll = PLL_ETH_INT_CLK_1000; pll = PLL_ETH_INT_CLK_1000;
break; break;
default: default:
printf("ar71xx_chip_set_pll_ge0: invalid speed %d\n", speed); printf("%s%d: invalid speed %d\n",
__func__, unit, speed);
return; return;
} }
switch (unit) {
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll, AR71XX_PLL_ETH0_SHIFT); case 0:
} ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT0_CLK, pll,
static void AR71XX_PLL_ETH0_SHIFT);
ar71xx_chip_set_pll_ge1(int speed) break;
{ case 1:
uint32_t pll; ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT1_CLK, pll,
switch(speed) { AR71XX_PLL_ETH1_SHIFT);
case 10: break;
pll = PLL_ETH_INT_CLK_10; default:
break; printf("%s: invalid PLL set for arge unit: %d\n",
case 100: __func__, unit);
pll = PLL_ETH_INT_CLK_100; return;
break;
case 1000:
pll = PLL_ETH_INT_CLK_1000;
break;
default:
printf("ar71xx_chip_set_pll_ge1: invalid speed %d\n", speed);
return;
} }
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll, AR71XX_PLL_ETH1_SHIFT);
} }
static void static void
ar71xx_chip_ddr_flush_ge0(void) ar71xx_chip_ddr_flush_ge(int unit)
{ {
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); switch (unit) {
} case 0:
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
static void break;
ar71xx_chip_ddr_flush_ge1(void) case 1:
{ ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); break;
default:
printf("%s: invalid DDR flush for arge unit: %d\n",
__func__, unit);
return;
}
} }
static void static void
@ -234,10 +231,8 @@ struct ar71xx_cpu_def ar71xx_chip_def = {
&ar71xx_chip_device_stop, &ar71xx_chip_device_stop,
&ar71xx_chip_device_start, &ar71xx_chip_device_start,
&ar71xx_chip_device_stopped, &ar71xx_chip_device_stopped,
&ar71xx_chip_set_pll_ge0, &ar71xx_chip_set_pll_ge,
&ar71xx_chip_set_pll_ge1, &ar71xx_chip_ddr_flush_ge,
&ar71xx_chip_ddr_flush_ge0,
&ar71xx_chip_ddr_flush_ge1,
&ar71xx_chip_get_eth_pll, &ar71xx_chip_get_eth_pll,
&ar71xx_chip_ddr_flush_ip2, &ar71xx_chip_ddr_flush_ip2,
&ar71xx_chip_init_usb_peripheral, &ar71xx_chip_init_usb_peripheral,

24
sys/mips/atheros/ar71xx_cpudef.h
View File

@ -35,10 +35,8 @@ struct ar71xx_cpu_def {
void (* ar71xx_chip_device_stop) (uint32_t); void (* ar71xx_chip_device_stop) (uint32_t);
void (* ar71xx_chip_device_start) (uint32_t); void (* ar71xx_chip_device_start) (uint32_t);
int (* ar71xx_chip_device_stopped) (uint32_t); int (* ar71xx_chip_device_stopped) (uint32_t);
void (* ar71xx_chip_set_pll_ge0) (int); void (* ar71xx_chip_set_pll_ge) (int, int);
void (* ar71xx_chip_set_pll_ge1) (int); void (* ar71xx_chip_ddr_flush_ge) (int);
void (* ar71xx_chip_ddr_flush_ge0) (void);
void (* ar71xx_chip_ddr_flush_ge1) (void);
uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
/* /*
@ -81,24 +79,14 @@ static inline int ar71xx_device_stopped(uint32_t mask)
return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
} }
static inline void ar71xx_device_set_pll_ge0(int speed) static inline void ar71xx_device_set_pll_ge(int unit, int speed)
{ {
ar71xx_cpu_ops->ar71xx_chip_set_pll_ge0(speed); ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed);
} }
static inline void ar71xx_device_set_pll_ge1(int speed) static inline void ar71xx_device_flush_ddr_ge(int unit)
{ {
ar71xx_cpu_ops->ar71xx_chip_set_pll_ge1(speed); ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
}
static inline void ar71xx_device_flush_ddr_ge0(void)
{
ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge0();
}
static inline void ar71xx_device_flush_ddr_ge1(void)
{
ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge1();
} }
static inline void ar71xx_init_usb_peripheral(void) static inline void ar71xx_init_usb_peripheral(void)

46
sys/mips/atheros/ar724x_chip.c
View File

@ -123,25 +123,37 @@ ar724x_chip_device_stopped(uint32_t mask)
} }
static void static void
ar724x_chip_set_pll_ge0(int speed) ar724x_chip_set_pll_ge(int unit, int speed)
{ {
switch (unit) {
case 0:
/* TODO */
break;
case 1:
/* TODO */
break;
default:
printf("%s: invalid PLL set for arge unit: %d\n",
__func__, unit);
return;
}
} }
static void static void
ar724x_chip_set_pll_ge1(int speed) ar724x_chip_ddr_flush_ge(int unit)
{ {
} switch (unit) {
case 0:
static void ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
ar724x_chip_ddr_flush_ge0(void) break;
{ case 1:
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
} break;
default:
static void printf("%s: invalid DDR flush for arge unit: %d\n",
ar724x_chip_ddr_flush_ge1(void) __func__, unit);
{ return;
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); }
} }
static void static void
@ -207,10 +219,8 @@ struct ar71xx_cpu_def ar724x_chip_def = {
&ar724x_chip_device_stop, &ar724x_chip_device_stop,
&ar724x_chip_device_start, &ar724x_chip_device_start,
&ar724x_chip_device_stopped, &ar724x_chip_device_stopped,
&ar724x_chip_set_pll_ge0, &ar724x_chip_set_pll_ge,
&ar724x_chip_set_pll_ge1, &ar724x_chip_ddr_flush_ge,
&ar724x_chip_ddr_flush_ge0,
&ar724x_chip_ddr_flush_ge1,
&ar724x_chip_get_eth_pll, &ar724x_chip_get_eth_pll,
&ar724x_chip_ddr_flush_ip2, &ar724x_chip_ddr_flush_ip2,
&ar724x_chip_init_usb_peripheral &ar724x_chip_init_usb_peripheral

73
sys/mips/atheros/ar91xx_chip.c
View File

@ -113,7 +113,7 @@ ar91xx_chip_device_stopped(uint32_t mask)
} }
static void static void
ar91xx_chip_set_pll_ge0(int speed) ar91xx_chip_set_pll_ge(int unit, int speed)
{ {
uint32_t pll; uint32_t pll;
@ -128,48 +128,43 @@ ar91xx_chip_set_pll_ge0(int speed)
pll = AR91XX_PLL_VAL_1000; pll = AR91XX_PLL_VAL_1000;
break; break;
default: default:
printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n", printf("%s%d: invalid speed %d\n",
speed); __func__, unit, speed);
return; return;
} }
ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, switch (unit) {
AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT); case 0:
} ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
static void AR91XX_ETH0_PLL_SHIFT);
ar91xx_chip_set_pll_ge1(int speed) break;
{ case 1:
uint32_t pll; ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
switch(speed) { AR91XX_ETH1_PLL_SHIFT);
case 10: break;
pll = AR91XX_PLL_VAL_10; default:
break; printf("%s: invalid PLL set for arge unit: %d\n",
case 100: __func__, unit);
pll = AR91XX_PLL_VAL_100; return;
break;
case 1000:
pll = AR91XX_PLL_VAL_1000;
break;
default:
printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
return;
} }
ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
} }
static void static void
ar91xx_chip_ddr_flush_ge0(void) ar91xx_chip_ddr_flush_ge(int unit)
{ {
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); switch (unit) {
} case 0:
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
static void break;
ar91xx_chip_ddr_flush_ge1(void) case 1:
{ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); break;
default:
printf("%s: invalid DDR flush for arge unit: %d\n",
__func__, unit);
return;
}
} }
static void static void
@ -211,10 +206,8 @@ struct ar71xx_cpu_def ar91xx_chip_def = {
&ar91xx_chip_device_stop, &ar91xx_chip_device_stop,
&ar91xx_chip_device_start, &ar91xx_chip_device_start,
&ar91xx_chip_device_stopped, &ar91xx_chip_device_stopped,
&ar91xx_chip_set_pll_ge0, &ar91xx_chip_set_pll_ge,
&ar91xx_chip_set_pll_ge1, &ar91xx_chip_ddr_flush_ge,
&ar91xx_chip_ddr_flush_ge0,
&ar91xx_chip_ddr_flush_ge1,
&ar91xx_chip_get_eth_pll, &ar91xx_chip_get_eth_pll,
&ar91xx_chip_ddr_flush_ip2, &ar91xx_chip_ddr_flush_ip2,
&ar91xx_chip_init_usb_peripheral, &ar91xx_chip_init_usb_peripheral,

5
sys/mips/atheros/if_arge.c
View File

@ -774,10 +774,7 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx); ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
/* set PLL registers */ /* set PLL registers */
if (sc->arge_mac_unit == 0) ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed);
ar71xx_device_set_pll_ge0(if_speed);
else
ar71xx_device_set_pll_ge1(if_speed);
} }