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Explicitly reset GMAC Controls and initialize GM_GP_CTRL register.

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The GM_GP_CTRL register may have stale content from previous link
information so clearing it will make hardware update the register
correctly when it established a valid link.
While I'm here remove stale comment.
This commit is contained in:
Pyun YongHyeon 2009-05-25 06:39:48 +00:00
parent 846e6d79e5
commit e6e23ffecb
1 changed files with 8 additions and 10 deletions
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18
sys/dev/msk/if_msk.c
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@ -3535,18 +3535,16 @@ msk_init_locked(struct msk_if_softc *sc_if)
ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
} }
/* GMAC Control reset. */
CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
/* /*
* Initialize GMAC first. * Initialize GMAC first such that speed/duplex/flow-control
* Without this initialization, Rx MAC did not work as expected * parameters are renegotiated when interface is brought up.
* and Rx MAC garbled status LEs and it resulted in out-of-order
* or duplicated frame delivery which in turn showed very poor
* Rx performance.(I had to write a packet analysis code that
* could be embeded in driver to diagnose this issue.)
* I've spent almost 2 months to fix this issue. If I have had
* datasheet for Yukon II I wouldn't have encountered this. :-(
*/ */
gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
/* Dummy read the Interrupt Source Register. */ /* Dummy read the Interrupt Source Register. */
CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));