Add support for per device features and workarounds.
Approved by: jimharris Sponsored by: Intel
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@ -76,10 +76,18 @@ enum ntb_device_type {
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NTB_SOC
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};
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/* Device features and workarounds */
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#define HAS_FEATURE(feature) \
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((ntb->features & (feature)) != 0)
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#define NTB_BAR_SIZE_4K (1 << 0)
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#define NTB_REGS_THRU_MW (1 << 1)
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struct ntb_hw_info {
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uint32_t device_id;
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enum ntb_device_type type;
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const char *desc;
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enum ntb_device_type type;
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uint64_t features;
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};
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struct ntb_pci_bar_info {
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@ -108,6 +116,7 @@ struct ntb_db_cb {
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struct ntb_softc {
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device_t device;
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enum ntb_device_type type;
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uint64_t features;
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struct ntb_pci_bar_info bar_info[NTB_MAX_BARS];
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struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS];
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@ -190,13 +199,15 @@ static void ntb_handle_heartbeat(void *arg);
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static void ntb_handle_link_event(struct ntb_softc *ntb, int link_state);
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static void recover_soc_link(void *arg);
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static int ntb_check_link_status(struct ntb_softc *ntb);
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static bool is_bar_for_data_transfer(int bar_num);
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static void save_bar_parameters(struct ntb_pci_bar_info *bar);
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static struct ntb_hw_info pci_ids[] = {
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{ 0x3C0D8086, NTB_XEON, "Xeon E5/Core i7 Non-Transparent Bridge B2B" },
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{ 0x0C4E8086, NTB_SOC, "Atom Processor S1200 NTB Primary B2B" },
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{ 0x0E0D8086, NTB_XEON, "Xeon E5 V2 Non-Transparent Bridge B2B" },
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{ 0x00000000, NTB_SOC, NULL }
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{ 0x3C0D8086, "Xeon E5/Core i7 Non-Transparent Bridge B2B", NTB_XEON,
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NTB_REGS_THRU_MW },
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{ 0x0C4E8086, "Atom Processor S1200 NTB Primary B2B", NTB_SOC, 0 },
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{ 0x0E0D8086, "Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON,
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NTB_REGS_THRU_MW | NTB_BAR_SIZE_4K },
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{ 0x00000000, NULL, NTB_SOC, 0 }
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};
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/*
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@ -253,6 +264,7 @@ ntb_attach(device_t device)
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ntb->device = device;
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ntb->type = p->type;
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ntb->features = p->features;
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/* Heartbeat timer for NTB_SOC since there is no link interrupt */
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callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE);
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@ -301,7 +313,7 @@ ntb_map_pci_bars(struct ntb_softc *ntb)
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&ntb->bar_info[NTB_B2B_BAR_2]);
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if (rc != 0)
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return rc;
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return (0);
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}
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