Introduce DP83867 PHY driver
DP83867 is a 10/100/1000 Texas Instruments PHY. Only SGMII mode is supported. Link status changes can be checked through an interrupt generated by the PHY, if available Obtained from: Semihalf Sponsored by: Alstom Group Differential revision: https://reviews.freebsd.org/D32813
This commit is contained in:
Kornel Duleba
Wojciech Macek
parent
9174eab414
commit
e85c94b8d6
@ -2417,6 +2417,7 @@ dev/mii/axphy.c optional miibus | axphy
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dev/mii/bmtphy.c optional miibus | bmtphy
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dev/mii/brgphy.c optional miibus | brgphy
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dev/mii/ciphy.c optional miibus | ciphy
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dev/mii/dp83867phy.c optional miibus | dp83867phy
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dev/mii/e1000phy.c optional miibus | e1000phy
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dev/mii/gentbi.c optional miibus | gentbi
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dev/mii/icsphy.c optional miibus | icsphy
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294
sys/dev/mii/dp83867phy.c
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294
sys/dev/mii/dp83867phy.c
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@ -0,0 +1,294 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for TI DP83867 Ethernet PHY
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <machine/resource.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include "miibus_if.h"
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#define BIT(x) (1 << (x))
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#define DP83867_PHYCR 0x10
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#define DP83867_PHYSTS 0x11
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#define DP83867_MICR 0x12
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#define DP83867_ISR 0x13
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#define DP83867_CFG3 0x1E
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#define DP83867_CTRL 0x1F
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#define DP83867_CFG4 0x31
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#define DP83867_RGMIICTL 0x32
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#define DP83867_STRP_STS1 0x6E
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#define DP83867_STRP_STS2 0x6F
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#define DP83867_PHYSTS_LINK_UP BIT(10)
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#define DP83867_PHYSTS_ANEG_PENDING BIT(11)
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#define DP83867_PHYSTS_FD BIT(13)
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#define DP83867_PHYSTS_SPEED_MASK (BIT(15) | BIT(14))
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#define DP83867_PHYSTS_SPEED_1000 BIT(15)
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#define DP83867_PHYSTS_SPEED_100 BIT(14)
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#define DP83867_PHYSTS_SPEED_10 0
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#define DP83867_MICR_AN_ERR BIT(15)
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#define DP83867_MICR_SPEED_CHG BIT(14)
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#define DP83867_MICR_DP_MODE_CHG BIT(13)
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#define DP83867_MICR_AN_CMPL BIT(11)
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#define DP83867_MICR_LINK_CHG BIT(10)
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#define DP83867_CFG3_INT_OE BIT(7)
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#define DP83867_CFG4_TST_MODE1 BIT(7)
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#define DP83867_CFG4_ANEG_MASK (BIT(5) | BIT(6))
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#define DP83867_CFG4_ANEG_16MS (0 << 5)
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#define BMSR_100_MASK (BMSR_100T4 | BMSR_100TXFDX | BMSR_100TXHDX | \
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BMSR_100T2FDX | BMSR_100T2HDX)
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static int dp_probe(device_t);
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static int dp_attach(device_t);
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static int dp_service(struct mii_softc*, struct mii_data*, int);
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static void dp_status(struct mii_softc*);
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struct dp83867_softc {
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struct mii_softc mii_sc;
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struct resource *irq_res;
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void *irq_cookie;
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};
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static const struct mii_phydesc dpphys[] = {
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MII_PHY_DESC(xxTI, DP83867)
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};
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static const struct mii_phy_funcs dpphy_funcs = {
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dp_service,
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dp_status,
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mii_phy_reset
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};
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static void
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dp_intr(void *arg)
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{
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struct mii_softc *sc = (struct mii_softc *)arg;
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uint32_t status;
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status = PHY_READ(sc, DP83867_ISR);
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status &= PHY_READ(sc, DP83867_MICR);
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if (!status)
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return;
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PHY_STATUS(sc);
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mii_phy_update(sc, MII_MEDIACHG);
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}
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static int
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dp_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, dpphys, BUS_PROBE_DEFAULT));
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}
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static int
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dp_attach(device_t dev)
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{
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struct dp83867_softc *sc;
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struct mii_softc *mii_sc;
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uint32_t value, maxspeed;
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ssize_t size;
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int rid, error;
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sc = device_get_softc(dev);
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mii_sc = &sc->mii_sc;
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size = device_get_property(dev, "max-speed", &maxspeed, sizeof(maxspeed));
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if (size <= 0)
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maxspeed = 0;
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mii_sc->mii_maxspeed = maxspeed;
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mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &dpphy_funcs, 1);
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
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if (sc->irq_res == NULL)
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goto no_irq;
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error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
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NULL, dp_intr, sc, &sc->irq_cookie);
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if (error != 0) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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sc->irq_res = NULL;
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goto no_irq;
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}
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/* Ack and unmask all relevant interrupts. */
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(void)PHY_READ(mii_sc, DP83867_ISR);
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value = DP83867_MICR_AN_ERR |
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DP83867_MICR_SPEED_CHG |
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DP83867_MICR_DP_MODE_CHG |
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DP83867_MICR_AN_CMPL |
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DP83867_MICR_LINK_CHG;
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PHY_WRITE(mii_sc, DP83867_MICR, value);
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value = PHY_READ(mii_sc, DP83867_CFG3);
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value |= DP83867_CFG3_INT_OE;
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PHY_WRITE(mii_sc, DP83867_CFG3, value);
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no_irq:
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/* Set autonegotation timeout to max possible value. */
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value = PHY_READ(mii_sc, DP83867_CFG4);
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value &= ~DP83867_CFG4_ANEG_MASK;
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value &= ~DP83867_CFG4_TST_MODE1;
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value |= DP83867_CFG4_ANEG_16MS;
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PHY_WRITE(mii_sc, DP83867_CFG4, value);
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return (0);
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}
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static int
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dp_detach(device_t dev)
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{
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struct dp83867_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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return (mii_phy_detach(dev));
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}
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static int
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dp_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return (0);
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break;
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}
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PHY_STATUS(sc);
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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dp_status(struct mii_softc *sc)
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{
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struct mii_data *mii;
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int bmsr, bmcr, physts;
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mii = sc->mii_pdata;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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physts = PHY_READ(sc, DP83867_PHYSTS);
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if ((bmsr & BMSR_LINK) && (physts & DP83867_PHYSTS_LINK_UP))
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if (bmcr & BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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/* Autoneg in progress. */
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if (!(physts & DP83867_PHYSTS_ANEG_PENDING)) {
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch (physts & DP83867_PHYSTS_SPEED_MASK) {
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case DP83867_PHYSTS_SPEED_1000:
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mii->mii_media_active |= IFM_1000_T;
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break;
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case DP83867_PHYSTS_SPEED_100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case DP83867_PHYSTS_SPEED_10:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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break;
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}
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if (physts & DP83867_PHYSTS_FD)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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}
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static device_method_t dp_methods[] = {
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DEVMETHOD(device_probe, dp_probe),
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DEVMETHOD(device_attach, dp_attach),
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DEVMETHOD(device_detach, dp_detach),
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DEVMETHOD_END
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};
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static devclass_t dp_devclass;
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static driver_t dp_driver = {
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"dp83867phy",
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dp_methods,
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sizeof(struct dp83867_softc)
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};
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DRIVER_MODULE(dp83867phy, miibus, dp_driver, dp_devclass, 0, 0);
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@ -110,6 +110,7 @@ oui xxPMCSIERRA 0x0009c0 PMC-Sierra
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oui xxPMCSIERRA2 0x009057 PMC-Sierra
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oui xxREALTEK 0x000732 RealTek Semicondctor
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oui yyREALTEK 0x000004 RealTek Semicondctor
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oui xxTI 0x100014 Texas Instruments
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/*
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* List of known models. Grouped by oui.
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@ -335,6 +336,7 @@ model SIS 900 0x0000 SiS 900 10/100 media interface
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model TI TLAN10T 0x0001 ThunderLAN 10BASE-T media interface
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model TI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface
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model TI TNETE2101 0x0003 TNETE2101 media interface
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model xxTI DP83867 0x0023 High Immunity 10/100/1000 PHY
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/* TDK Semiconductor PHYs */
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model xxTSC 78Q2120 0x0014 78Q2120 10/100 media interface
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