Addition of support of the slightly rogue Promise IDE interface(Dyson), support
of multiple PCI IDE controllers(Dyson), and some updates and cleanups from John Hood, who originally made our IDE DMA stuff work :-). I have run tests with 7 IDE drives connected to my system, all in DMA mode, with no errors. Modulo any bugs, this stuff makes IDE look really good (within it's limitations.) Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
This commit is contained in:
John Dyson
parent
ab71361364
commit
e871e61fcf
@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.366 1997/09/16 07:45:31 joerg Exp $
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# $Id: LINT,v 1.367 1997/09/19 15:25:48 jmg Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -763,8 +763,23 @@ controller wds0 at isa? port 0x350 bio irq 15 drq 6 vector wdsintr
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# allowed to probe for 32 bit transfers, but will allow multi-sector
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# transfers up to the maximum that the drive supports.
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#
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# If you are using a PCI controller that is not running in compatibility
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# mode (for example, it is a 2nd IDE PCI interface), then use config line(s)
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# such as:
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#
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#controller wdc2 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd4 at wdc2 drive 0
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#disk wd5 at wdc2 drive 1
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#
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#controller wdc3 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd6 at wdc3 drive 0
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#disk wd7 at wdc3 drive 1
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#
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# Note that the above config would be useful for a Promise card, when used
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# on a MB that already has a PIIX controller. Note the bogus irq and port
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# entries. These are automatically filled in by the IDE/PCI support.
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#
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controller wdc0 at isa? port "IO_WD1" bio irq 14 vector wdintr
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disk wd0 at wdc0 drive 0
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disk wd1 at wdc0 drive 1
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@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcireg.h,v 1.17 1997/05/28 20:37:19 se Exp $
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* $Id: pcireg.h,v 1.18 1997/06/01 16:00:43 peter Exp $
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*
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*/
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@ -241,6 +241,7 @@
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#define PCI_CLASS_REG 0x08
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#define PCI_CLASS_MASK 0xff000000
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#define PCI_SUBCLASS_MASK 0x00ff0000
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#define PCI_REVISION_MASK 0x000000ff
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#define PCI_CLASS_PREHISTORIC 0x00000000
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#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
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#define PCI_CLASS_MASS_STORAGE 0x01000000
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.366 1997/09/16 07:45:31 joerg Exp $
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# $Id: LINT,v 1.367 1997/09/19 15:25:48 jmg Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -763,8 +763,23 @@ controller wds0 at isa? port 0x350 bio irq 15 drq 6 vector wdsintr
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# allowed to probe for 32 bit transfers, but will allow multi-sector
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# transfers up to the maximum that the drive supports.
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#
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# If you are using a PCI controller that is not running in compatibility
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# mode (for example, it is a 2nd IDE PCI interface), then use config line(s)
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# such as:
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#
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#controller wdc2 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd4 at wdc2 drive 0
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#disk wd5 at wdc2 drive 1
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#
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#controller wdc3 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd6 at wdc3 drive 0
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#disk wd7 at wdc3 drive 1
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#
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# Note that the above config would be useful for a Promise card, when used
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# on a MB that already has a PIIX controller. Note the bogus irq and port
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# entries. These are automatically filled in by the IDE/PCI support.
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#
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controller wdc0 at isa? port "IO_WD1" bio irq 14 vector wdintr
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disk wd0 at wdc0 drive 0
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disk wd1 at wdc0 drive 1
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.366 1997/09/16 07:45:31 joerg Exp $
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# $Id: LINT,v 1.367 1997/09/19 15:25:48 jmg Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -763,8 +763,23 @@ controller wds0 at isa? port 0x350 bio irq 15 drq 6 vector wdsintr
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# allowed to probe for 32 bit transfers, but will allow multi-sector
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# transfers up to the maximum that the drive supports.
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#
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# If you are using a PCI controller that is not running in compatibility
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# mode (for example, it is a 2nd IDE PCI interface), then use config line(s)
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# such as:
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#
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#controller wdc2 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd4 at wdc2 drive 0
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#disk wd5 at wdc2 drive 1
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#
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#controller wdc3 at isa? port "0" bio irq ? flags 0xa0ffa0ff vector wdintr
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#disk wd6 at wdc3 drive 0
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#disk wd7 at wdc3 drive 1
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#
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# Note that the above config would be useful for a Promise card, when used
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# on a MB that already has a PIIX controller. Note the bogus irq and port
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# entries. These are automatically filled in by the IDE/PCI support.
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#
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controller wdc0 at isa? port "IO_WD1" bio irq 14 vector wdintr
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disk wd0 at wdc0 drive 0
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disk wd1 at wdc0 drive 1
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)wd.c 7.2 (Berkeley) 5/9/91
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* $Id: wd.c,v 1.137 1997/09/10 12:31:38 joerg Exp $
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* $Id: wd.c,v 1.138 1997/09/13 16:12:12 joerg Exp $
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*/
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/* TODO:
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@ -66,6 +66,7 @@
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#if NWDC > 0
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#include "pci.h"
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#include <sys/param.h>
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#include <sys/dkbad.h>
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#include <sys/systm.h>
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@ -157,11 +158,13 @@ struct disk {
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#endif
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int dk_unit; /* physical unit number */
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int dk_lunit; /* logical unit number */
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int dk_interface; /* interface (two ctrlrs per interface) */
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char dk_state; /* control state */
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u_char dk_status; /* copy of status reg. */
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u_char dk_error; /* copy of error reg. */
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u_char dk_timeout; /* countdown to next timeout */
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int dk_port; /* i/o port base */
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int dk_altport; /* altstatus port base */
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#ifdef DEVFS
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void *dk_bdev; /* devfs token for whole disk */
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void *dk_cdev; /* devfs token for raw whole disk */
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@ -204,7 +207,7 @@ static struct {
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int b_active;
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} wdtab[NWDC];
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struct wddma wddma;
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struct wddma wddma[NWDC];
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#ifdef notyet
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static struct buf rwdbuf[NWD]; /* buffers for raw IO */
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@ -276,6 +279,8 @@ static int
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wdprobe(struct isa_device *dvp)
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{
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int unit = dvp->id_unit;
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void *cookie;
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int interface;
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struct disk *du;
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if (unit >= NWDC)
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@ -286,8 +291,21 @@ wdprobe(struct isa_device *dvp)
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return (0);
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bzero(du, sizeof *du);
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du->dk_ctrlr = dvp->id_unit;
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interface = du->dk_ctrlr / 2;
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du->dk_interface = interface;
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#if !defined(DISABLE_PCI_IDE) && (NPCI > 0)
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if (wddma[interface].wdd_candma) {
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du->dk_dmacookie = wddma[interface].wdd_candma(dvp->id_iobase, du->dk_ctrlr);
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du->dk_port = dvp->id_iobase;
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du->dk_altport = wddma[interface].wdd_altiobase(du->dk_dmacookie);
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} else {
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du->dk_port = dvp->id_iobase;
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du->dk_altport = du->dk_port + wd_ctlr;
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}
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#else
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du->dk_port = dvp->id_iobase;
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du->dk_altport = du->dk_port + wd_ctlr;
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#endif
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/* check if we have registers that work */
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outb(du->dk_port + wd_sdh, WDSD_IBM); /* set unit 0 */
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@ -317,14 +335,16 @@ wdprobe(struct isa_device *dvp)
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goto reset_ok;
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#endif
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DELAY(RECOVERYTIME);
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if (wdreset(du) != 0)
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if (wdreset(du) != 0) {
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goto nodevice;
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}
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reset_ok:
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/* execute a controller only command */
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if (wdcommand(du, 0, 0, 0, 0, WDCC_DIAGNOSE) != 0
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|| wdwait(du, 0, TIMEOUT) < 0)
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|| wdwait(du, 0, TIMEOUT) < 0) {
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goto nodevice;
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}
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/*
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* drive(s) did not time out during diagnostic :
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@ -338,7 +358,6 @@ reset_ok:
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* drive 2. (This seems to contradict the ATA spec.)
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*/
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du->dk_error = inb(du->dk_port + wd_error);
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/* printf("Error : %x\n", du->dk_error); */
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if(du->dk_error != 0x01) {
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if(du->dk_error & 0x80) { /* drive 1 failure */
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@ -776,7 +795,7 @@ wdstart(int ctrlr)
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(bp->b_flags & B_READ) ? "read" : "write",
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bp->b_bcount, blknum);
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else
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printf(" %d)%x", du->dk_skip, inb(du->dk_port + wd_altsts));
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printf(" %d)%x", du->dk_skip, inb(du->dk_altport));
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#endif
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lp = &du->dk_dd;
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@ -844,7 +863,7 @@ wdstart(int ctrlr)
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du->dk_currentiosize = 1;
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} else {
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if((du->dk_flags & DKFL_USEDMA) &&
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wddma.wdd_dmaverify(du->dk_dmacookie,
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wddma[du->dk_interface].wdd_dmaverify(du->dk_dmacookie,
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(void *)((int)bp->b_un.b_addr +
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du->dk_skip * DEV_BSIZE),
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du->dk_bc,
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@ -893,7 +912,7 @@ wdstart(int ctrlr)
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}
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if ((du->dk_flags & (DKFL_DMA|DKFL_SINGLE)) == DKFL_DMA) {
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wddma.wdd_dmaprep(du->dk_dmacookie,
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wddma[du->dk_interface].wdd_dmaprep(du->dk_dmacookie,
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(void *)((int)bp->b_un.b_addr +
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du->dk_skip * DEV_BSIZE),
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du->dk_bc,
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@ -909,7 +928,7 @@ wdstart(int ctrlr)
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printf("cylin %ld head %ld sector %ld addr %x sts %x\n",
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cylin, head, sector,
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(int)bp->b_un.b_addr + du->dk_skip * DEV_BSIZE,
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inb(du->dk_port + wd_altsts));
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inb(du->dk_altport));
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#endif
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}
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@ -937,7 +956,7 @@ wdstart(int ctrlr)
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/* if this is a DMA op, start DMA and go away until it's done. */
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if ((du->dk_flags & (DKFL_DMA|DKFL_SINGLE)) == DKFL_DMA) {
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wddma.wdd_dmastart(du->dk_dmacookie);
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wddma[du->dk_interface].wdd_dmastart(du->dk_dmacookie);
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return;
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}
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@ -1049,10 +1068,10 @@ wdintr(int unit)
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/* finish off DMA */
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if (du->dk_flags & (DKFL_DMA|DKFL_USEDMA)) {
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/* XXX SMP boxes sometimes generate an early intr. Why? */
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if ((wddma.wdd_dmastatus(du->dk_dmacookie) & WDDS_INTERRUPT)
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if ((wddma[du->dk_interface].wdd_dmastatus(du->dk_dmacookie) & WDDS_INTERRUPT)
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== 0)
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return;
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dmastat = wddma.wdd_dmadone(du->dk_dmacookie);
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dmastat = wddma[du->dk_interface].wdd_dmadone(du->dk_dmacookie);
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}
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du->dk_timeout = 0;
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@ -1834,20 +1853,22 @@ failed:
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du->dk_multi = wp->wdp_nsecperint & 0xff;
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wdsetmulti(du);
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du->dk_dmacookie = NULL;
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/*
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* check drive's DMA capability
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*/
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if (wddma[du->dk_interface].wdd_candma) {
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du->dk_dmacookie = wddma[du->dk_interface].wdd_candma(du->dk_port, du->dk_ctrlr);
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/* does user want this? */
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if ((du->cfg_flags & WDOPT_DMA) &&
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if ((du->cfg_flags & WDOPT_DMA) &&
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/* have we got a DMA controller? */
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(wddma.wdd_candma &&
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(du->dk_dmacookie = wddma.wdd_candma(du->dk_port,
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du->dk_unit))) &&
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/* can said drive do DMA? */
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(wddma.wdd_dmainit(du->dk_dmacookie, wp, wdsetmode, du)))
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du->dk_flags |= DKFL_USEDMA;
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du->dk_dmacookie &&
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/* can said drive do DMA? */
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wddma[du->dk_interface].wdd_dmainit(du->dk_dmacookie, wp, wdsetmode, du)) {
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du->dk_flags |= DKFL_USEDMA;
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}
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} else {
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du->dk_dmacookie = NULL;
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}
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#ifdef WDDEBUG
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printf(
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@ -2210,28 +2231,28 @@ wdflushirq(struct disk *du, int old_ipl)
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static int
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wdreset(struct disk *du)
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{
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int wdc, err = 0;
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int err = 0;
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if ((du->dk_flags & (DKFL_DMA|DKFL_USEDMA)) && du->dk_dmacookie)
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wddma.wdd_dmadone(du->dk_dmacookie);
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wddma[du->dk_interface].wdd_dmadone(du->dk_dmacookie);
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wdc = du->dk_port;
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(void)wdwait(du, 0, TIMEOUT);
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outb(wdc + wd_ctlr, WDCTL_IDS | WDCTL_RST);
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outb(du->dk_altport, WDCTL_IDS | WDCTL_RST);
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DELAY(10 * 1000);
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outb(wdc + wd_ctlr, WDCTL_IDS);
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outb(du->dk_altport, WDCTL_IDS);
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#ifdef ATAPI
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if (wdwait(du, WDCS_READY | WDCS_SEEKCMPLT, TIMEOUT) != 0)
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err = 1; /* no IDE drive found */
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du->dk_error = inb(wdc + wd_error);
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du->dk_error = inb(du->dk_port + wd_error);
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if (du->dk_error != 0x01)
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err = 1; /* the drive is incompatible */
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#else
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if (wdwait(du, WDCS_READY | WDCS_SEEKCMPLT, TIMEOUT) != 0
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|| (du->dk_error = inb(wdc + wd_error)) != 0x01)
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if (wdwait(du, WDCS_READY | WDCS_SEEKCMPLT, TIMEOUT) != 0) {
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printf("wdreset: error1: 0x%x\n", du->dk_error);
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return (1);
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}
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#endif
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outb(wdc + wd_ctlr, WDCTL_4BIT);
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outb(du->dk_altport, WDCTL_4BIT);
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return (err);
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}
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@ -2273,7 +2294,7 @@ wdtimeout(void *cdu)
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if (du->dk_dmacookie)
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printf("wd%d: wdtimeout() DMA status %b\n",
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du->dk_lunit,
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wddma.wdd_dmastatus(du->dk_dmacookie),
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wddma[du->dk_interface].wdd_dmastatus(du->dk_dmacookie),
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WDDS_BITS);
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}
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wdunwedge(du);
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@ -2384,8 +2405,9 @@ wdwait(struct disk *du, u_char bits_wanted, int timeout)
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* command completion.
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*/
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}
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if ((status & bits_wanted) == bits_wanted)
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if ((status & bits_wanted) == bits_wanted) {
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return (status & WDCS_ERR);
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}
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}
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if (timeout < TIMEOUT)
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/*
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
|
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*
|
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* from: @(#)wdreg.h 7.1 (Berkeley) 5/9/91
|
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* $Id: wdreg.h,v 1.12.2.3 1997/01/14 17:32:07 bde Exp $
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* $Id: wdreg.h,v 1.19 1997/09/04 18:49:48 sos Exp $
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*/
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/*
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@ -260,7 +260,7 @@ int wdformat(struct buf *bp);
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* WDDS_* constants below.
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*/
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struct wddma {
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void *(*wdd_candma) /* returns a cookie if can do DMA */
|
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void *(*wdd_candma) /* returns a cookie if PCI */
|
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__P((int ctlr, int drive));
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int (*wdd_dmaverify) /* verify that request is DMA-able */
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__P((void *cookie, char *vaddr, u_long len, int direction));
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@ -277,6 +277,10 @@ struct wddma {
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struct wdparams *wp,
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int(wdcmd)__P((int mode, void *wdinfo)),
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void *wdinfo));
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int (*wdd_iobase) /* returns iobase address */
|
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__P((void *cookie));
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int (*wdd_altiobase) /* returns altiobase address */
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__P((void *cookie));
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};
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||||
|
||||
/* logical status bits returned by wdd_dmastatus */
|
||||
@ -305,6 +309,6 @@ struct wddma {
|
||||
#define WDDMA_UDMA1 0x41
|
||||
#define WDDMA_UDMA2 0x42
|
||||
|
||||
extern struct wddma wddma;
|
||||
extern struct wddma wddma[];
|
||||
|
||||
#endif /* KERNEL */
|
||||
|
||||
1648
sys/pci/ide_pci.c
1648
sys/pci/ide_pci.c
File diff suppressed because it is too large
Load Diff
@ -26,7 +26,7 @@
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Id: pcireg.h,v 1.17 1997/05/28 20:37:19 se Exp $
|
||||
* $Id: pcireg.h,v 1.18 1997/06/01 16:00:43 peter Exp $
|
||||
*
|
||||
*/
|
||||
|
||||
@ -241,6 +241,7 @@
|
||||
#define PCI_CLASS_REG 0x08
|
||||
#define PCI_CLASS_MASK 0xff000000
|
||||
#define PCI_SUBCLASS_MASK 0x00ff0000
|
||||
#define PCI_REVISION_MASK 0x000000ff
|
||||
#define PCI_CLASS_PREHISTORIC 0x00000000
|
||||
#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
|
||||
#define PCI_CLASS_MASS_STORAGE 0x01000000
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user