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Provide for multiple, cascaded PICs on PowerPC systems, and extend the

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OFW interrupt map interface to also return the device's interrupt parent.

MFC after:	8.1-RELEASE
This commit is contained in:
Nathan Whitehorn 2010-06-18 14:06:27 +00:00
parent 5c1a5e740f
commit eaef5f0af8
35 changed files with 334 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
sys/dev/iicbus/iiconf.c
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@ -363,7 +363,7 @@ iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs)
int int
iicbus_transfer_gen(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) iicbus_transfer_gen(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
{ {
int i, error, lenread, lenwrote, nkid; int i, error, lenread, lenwrote, nkid, rpstart, addr;
device_t *children, bus; device_t *children, bus;
if ((error = device_get_children(dev, &children, &nkid)) != 0) if ((error = device_get_children(dev, &children, &nkid)) != 0)
@ -373,14 +373,38 @@ iicbus_transfer_gen(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
return (EIO); return (EIO);
} }
bus = children[0]; bus = children[0];
rpstart = 0;
free(children, M_TEMP); free(children, M_TEMP);
for (i = 0, error = 0; i < nmsgs && error == 0; i++) { for (i = 0, error = 0; i < nmsgs && error == 0; i++) {
addr = msgs[i].slave;
if (msgs[i].flags & IIC_M_RD) if (msgs[i].flags & IIC_M_RD)
error = iicbus_block_read(bus, msgs[i].slave, addr |= LSB;
msgs[i].buf, msgs[i].len, &lenread);
else else
error = iicbus_block_write(bus, msgs[i].slave, addr &= ~LSB;
msgs[i].buf, msgs[i].len, &lenwrote);
if (!(msgs[i].flags & IIC_M_NOSTART)) {
if (rpstart)
error = iicbus_repeated_start(bus, addr, 0);
else
error = iicbus_start(bus, addr, 0);
}
if (error)
break;
if (msgs[i].flags & IIC_M_RD)
error = iicbus_read(bus, msgs[i].buf, msgs[i].len,
&lenread, IIC_LAST_READ, 0);
else
error = iicbus_write(bus, msgs[i].buf, msgs[i].len,
&lenwrote, 0);
if (!(msgs[i].flags & IIC_M_NOSTOP)) {
rpstart = 0;
iicbus_stop(bus);
} else {
rpstart = 1; /* Next message gets repeated start */
}
} }
return (error); return (error);
} }

9
sys/dev/ofw/ofw_bus_subr.c
View File

@ -222,7 +222,7 @@ ofw_bus_setup_iinfo(phandle_t node, struct ofw_bus_iinfo *ii, int intrsz)
int int
ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg, ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg,
int regsz, void *pintr, int pintrsz, void *mintr, int mintrsz, int regsz, void *pintr, int pintrsz, void *mintr, int mintrsz,
void *maskbuf) phandle_t *iparent, void *maskbuf)
{ {
int rv; int rv;
@ -236,7 +236,7 @@ ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg,
panic("ofw_bus_lookup_imap: could not get reg property"); panic("ofw_bus_lookup_imap: could not get reg property");
return (ofw_bus_search_intrmap(pintr, pintrsz, reg, ii->opi_addrc, return (ofw_bus_search_intrmap(pintr, pintrsz, reg, ii->opi_addrc,
ii->opi_imap, ii->opi_imapsz, ii->opi_imapmsk, maskbuf, mintr, ii->opi_imap, ii->opi_imapsz, ii->opi_imapmsk, maskbuf, mintr,
mintrsz)); mintrsz, iparent));
} }
/* /*
@ -259,7 +259,7 @@ ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg,
int int
ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz, ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
void *imap, int imapsz, void *imapmsk, void *maskbuf, void *result, void *imap, int imapsz, void *imapmsk, void *maskbuf, void *result,
int rintrsz) int rintrsz, phandle_t *iparent)
{ {
phandle_t parent; phandle_t parent;
uint8_t *ref = maskbuf; uint8_t *ref = maskbuf;
@ -303,6 +303,9 @@ ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
if (bcmp(ref, mptr, physsz + intrsz) == 0) { if (bcmp(ref, mptr, physsz + intrsz) == 0) {
bcopy(mptr + physsz + intrsz + sizeof(parent), bcopy(mptr + physsz + intrsz + sizeof(parent),
result, rintrsz); result, rintrsz);
if (iparent != NULL)
*iparent = parent;
return (1); return (1);
} }
mptr += tsz; mptr += tsz;

7
sys/dev/ofw/ofw_bus_subr.h
View File

@ -63,9 +63,12 @@ bus_child_pnpinfo_str_t ofw_bus_gen_child_pnpinfo_str;
/* Routines for processing firmware interrupt maps */ /* Routines for processing firmware interrupt maps */
void ofw_bus_setup_iinfo(phandle_t, struct ofw_bus_iinfo *, int); void ofw_bus_setup_iinfo(phandle_t, struct ofw_bus_iinfo *, int);
int ofw_bus_lookup_imap(phandle_t, struct ofw_bus_iinfo *, void *, int, int ofw_bus_lookup_imap(phandle_t, struct ofw_bus_iinfo *, void *, int,
void *, int, void *, int, void *); void *, int, void *, int, phandle_t *, void *);
int ofw_bus_search_intrmap(void *, int, void *, int, void *, int, void *, int ofw_bus_search_intrmap(void *, int, void *, int, void *, int, void *,
void *, void *, int); void *, void *, int, phandle_t *);
/* Helper to get node's interrupt parent */
void ofw_bus_find_iparent(phandle_t);
/* Helper routine for checking compat prop */ /* Helper routine for checking compat prop */
int ofw_bus_is_compatible(device_t, const char *); int ofw_bus_is_compatible(device_t, const char *);

2
sys/powerpc/aim/interrupt.c
View File

@ -81,7 +81,7 @@ powerpc_interrupt(struct trapframe *framep)
switch (framep->exc) { switch (framep->exc) {
case EXC_EXI: case EXC_EXI:
critical_enter(); critical_enter();
PIC_DISPATCH(pic, framep); PIC_DISPATCH(root_pic, framep);
critical_exit(); critical_exit();
break; break;

2
sys/powerpc/aim/nexus.c
View File

@ -208,7 +208,7 @@ nexus_attach(device_t dev)
sc = device_get_softc(dev); sc = device_get_softc(dev);
start = 0; start = 0;
end = INTR_VECTORS - 1; end = MAX_PICS*INTR_VECTORS - 1;
sc->sc_rman.rm_start = start; sc->sc_rman.rm_start = start;
sc->sc_rman.rm_end = end; sc->sc_rman.rm_end = end;

2
sys/powerpc/booke/interrupt.c
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@ -134,7 +134,7 @@ powerpc_extr_interrupt(struct trapframe *framep)
{ {
critical_enter(); critical_enter();
PIC_DISPATCH(pic, framep); PIC_DISPATCH(root_pic, framep);
critical_exit(); critical_exit();
framep->srr1 &= ~PSL_WE; framep->srr1 &= ~PSL_WE;
} }

16
sys/powerpc/include/intr_machdep.h
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@ -29,26 +29,32 @@
#define _MACHINE_INTR_MACHDEP_H_ #define _MACHINE_INTR_MACHDEP_H_
#define INTR_VECTORS 256 #define INTR_VECTORS 256
#define MAX_PICS 5
#define IGN_SHIFT 8
#define INTR_INTLINE(irq) (irq & ((1 << IGN_SHIFT) - 1))
#define INTR_IGN(irq) (irq >> IGN_SHIFT)
#define INTR_VEC(pic_id, irq) ((powerpc_ign_lookup(pic_id) << IGN_SHIFT) | irq)
/* /*
* Default base address for MSI messages on PowerPC * Default base address for MSI messages on PowerPC
*/ */
#define MSI_INTEL_ADDR_BASE 0xfee00000 #define MSI_INTEL_ADDR_BASE 0xfee00000
extern device_t pic; extern device_t root_pic;
extern device_t pic8259;
struct trapframe; struct trapframe;
driver_filter_t powerpc_ipi_handler; driver_filter_t powerpc_ipi_handler;
void powerpc_register_pic(device_t, u_int); void powerpc_register_pic(device_t, u_int);
void powerpc_register_8259(device_t); int powerpc_ign_lookup(uint32_t pic_id);
void powerpc_dispatch_intr(u_int, struct trapframe *); void powerpc_dispatch_intr(u_int, struct trapframe *);
int powerpc_enable_intr(void); int powerpc_enable_intr(void);
int powerpc_setup_intr(const char *, u_int, driver_filter_t, int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t,
driver_intr_t, void *, enum intr_type, void **); void *, enum intr_type, void **);
int powerpc_teardown_intr(void *); int powerpc_teardown_intr(void *);
int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity); int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity);

4
sys/powerpc/include/ocpbus.h
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@ -44,4 +44,8 @@
#define OCPBUS_DEVTYPE_I2C 7 #define OCPBUS_DEVTYPE_I2C 7
#define OCPBUS_DEVTYPE_SEC 8 #define OCPBUS_DEVTYPE_SEC 8
/* PIC IDs */
#define OPIC_ID 0
#define ATPIC_ID 1
#endif /* _MACHINE_OCPBUS_H_ */ #endif /* _MACHINE_OCPBUS_H_ */

3
sys/powerpc/include/openpicvar.h
View File

@ -35,10 +35,13 @@
struct openpic_softc { struct openpic_softc {
device_t sc_dev; device_t sc_dev;
struct resource *sc_memr; struct resource *sc_memr;
struct resource *sc_intr;
bus_space_tag_t sc_bt; bus_space_tag_t sc_bt;
bus_space_handle_t sc_bh; bus_space_handle_t sc_bh;
char *sc_version; char *sc_version;
int sc_rid; int sc_rid;
int sc_irq;
void *sc_icookie;
u_int sc_ncpu; u_int sc_ncpu;
u_int sc_nirq; u_int sc_nirq;
int sc_psim; int sc_psim;

16
sys/powerpc/mpc85xx/atpic.c
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@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/intr.h> #include <machine/intr.h>
#include <machine/intr_machdep.h> #include <machine/intr_machdep.h>
#include <machine/ocpbus.h>
#include <machine/pio.h> #include <machine/pio.h>
#include <powerpc/mpc85xx/ocpbus.h> #include <powerpc/mpc85xx/ocpbus.h>
@ -79,6 +80,9 @@ static void atpic_eoi(device_t, u_int);
static void atpic_ipi(device_t, u_int); static void atpic_ipi(device_t, u_int);
static void atpic_mask(device_t, u_int); static void atpic_mask(device_t, u_int);
static void atpic_unmask(device_t, u_int); static void atpic_unmask(device_t, u_int);
static uint32_t atpic_id (device_t dev);
static device_t pic8259;
static device_method_t atpic_isa_methods[] = { static device_method_t atpic_isa_methods[] = {
/* Device interface */ /* Device interface */
@ -94,6 +98,7 @@ static device_method_t atpic_isa_methods[] = {
DEVMETHOD(pic_ipi, atpic_ipi), DEVMETHOD(pic_ipi, atpic_ipi),
DEVMETHOD(pic_mask, atpic_mask), DEVMETHOD(pic_mask, atpic_mask),
DEVMETHOD(pic_unmask, atpic_unmask), DEVMETHOD(pic_unmask, atpic_unmask),
DEVMETHOD(pic_id, atpic_id),
{ 0, 0 }, { 0, 0 },
}; };
@ -219,7 +224,8 @@ atpic_isa_attach(device_t dev)
atpic_init(sc, ATPIC_SLAVE); atpic_init(sc, ATPIC_SLAVE);
atpic_init(sc, ATPIC_MASTER); atpic_init(sc, ATPIC_MASTER);
powerpc_register_8259(dev); powerpc_register_pic(dev, 0x10);
pic8259 = dev;
return (0); return (0);
fail: fail:
@ -328,3 +334,11 @@ atpic_unmask(device_t dev, u_int irq)
atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
} }
} }
static uint32_t
atpic_id (device_t dev)
{
return (ATPIC_ID);
}

9
sys/powerpc/mpc85xx/isa.c
View File

@ -32,12 +32,16 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h> #include <machine/bus.h>
#include <sys/rman.h> #include <sys/rman.h>
#include <machine/intr_machdep.h>
#include <machine/ocpbus.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <isa/isareg.h> #include <isa/isareg.h>
#include <isa/isavar.h> #include <isa/isavar.h>
#include <isa/isa_common.h> #include <isa/isa_common.h>
#include "ocpbus.h"
void void
isa_init(device_t dev) isa_init(device_t dev)
{ {
@ -58,7 +62,10 @@ isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
resource_list_find(rl, type, *rid) == NULL) { resource_list_find(rl, type, *rid) == NULL) {
switch (type) { switch (type) {
case SYS_RES_IOPORT: rids = ISA_PNP_NPORT; break; case SYS_RES_IOPORT: rids = ISA_PNP_NPORT; break;
case SYS_RES_IRQ: rids = ISA_PNP_NIRQ; break; case SYS_RES_IRQ:
rids = ISA_PNP_NIRQ;
start = ISA_IRQ(start);
break;
case SYS_RES_MEMORY: rids = ISA_PNP_NMEM; break; case SYS_RES_MEMORY: rids = ISA_PNP_NMEM; break;
default: rids = 0; break; default: rids = 0; break;
} }

42
sys/powerpc/mpc85xx/ocpbus.c
View File

@ -277,7 +277,7 @@ ocpbus_attach(device_t dev)
ccsr_read4(OCP85XX_PORDEVSR), ccsr_read4(OCP85XX_PORDEVSR),
ccsr_read4(OCP85XX_PORDEVSR2)); ccsr_read4(OCP85XX_PORDEVSR2));
for (i = PIC_IRQ_START; i < PIC_IRQ_START + 4; i++) for (i = INTR_VEC(OPIC_ID, 0); i < INTR_VEC(OPIC_ID, 4); i++)
powerpc_config_intr(i, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); powerpc_config_intr(i, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
return (bus_generic_attach(dev)); return (bus_generic_attach(dev));
@ -305,35 +305,35 @@ const struct ocp_resource mpc8555_resources[] = {
{OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCP85XX_QUICC_OFF, {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCP85XX_QUICC_OFF,
OCP85XX_QUICC_SIZE}, OCP85XX_QUICC_SIZE},
{OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(30), 1}, {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, 30, 1},
{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCP85XX_TSEC0_OFF, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCP85XX_TSEC0_OFF,
OCP85XX_TSEC_SIZE}, OCP85XX_TSEC_SIZE},
{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(13), 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, 13, 1},
{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(14), 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, 14, 1},
{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, PIC_IRQ_INT(18), 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, 18, 1},
{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCP85XX_TSEC1_OFF, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCP85XX_TSEC1_OFF,
OCP85XX_TSEC_SIZE}, OCP85XX_TSEC_SIZE},
{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(19), 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, 19, 1},
{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, PIC_IRQ_INT(20), 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, 20, 1},
{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, PIC_IRQ_INT(24), 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, 24, 1},
{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCP85XX_TSEC2_OFF, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCP85XX_TSEC2_OFF,
OCP85XX_TSEC_SIZE}, OCP85XX_TSEC_SIZE},
{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, PIC_IRQ_INT(15), 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, 15, 1},
{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, PIC_IRQ_INT(16), 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, 16, 1},
{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, PIC_IRQ_INT(17), 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, 17, 1},
{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCP85XX_TSEC3_OFF, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCP85XX_TSEC3_OFF,
OCP85XX_TSEC_SIZE}, OCP85XX_TSEC_SIZE},
{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, PIC_IRQ_INT(21), 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, 21, 1},
{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, PIC_IRQ_INT(22), 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, 22, 1},
{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, PIC_IRQ_INT(23), 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, 23, 1},
{OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCP85XX_UART0_OFF, {OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCP85XX_UART0_OFF,
OCP85XX_UART_SIZE}, OCP85XX_UART_SIZE},
{OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, {OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, 26, 1},
{OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCP85XX_UART1_OFF, {OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCP85XX_UART1_OFF,
OCP85XX_UART_SIZE}, OCP85XX_UART_SIZE},
{OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, {OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, 26, 1},
{OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCP85XX_PCI0_OFF, {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCP85XX_PCI0_OFF,
OCP85XX_PCI_SIZE}, OCP85XX_PCI_SIZE},
@ -357,15 +357,15 @@ const struct ocp_resource mpc8555_resources[] = {
{OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCP85XX_I2C0_OFF, {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCP85XX_I2C0_OFF,
OCP85XX_I2C_SIZE}, OCP85XX_I2C_SIZE},
{OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, 27, 1},
{OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCP85XX_I2C1_OFF, {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCP85XX_I2C1_OFF,
OCP85XX_I2C_SIZE}, OCP85XX_I2C_SIZE},
{OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, 27, 1},
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_MEMORY, 0, OCP85XX_SEC_OFF, {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_MEMORY, 0, OCP85XX_SEC_OFF,
OCP85XX_SEC_SIZE}, OCP85XX_SEC_SIZE},
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(29), 1}, {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 0, 29, 1},
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(42), 1}, {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 1, 42, 1},
{0} {0}
}; };
@ -402,7 +402,7 @@ ocpbus_get_resource(device_t dev, device_t child, int type, int rid,
start = res->sr_offset + CCSRBAR_VA; start = res->sr_offset + CCSRBAR_VA;
break; break;
case SYS_RES_IRQ: case SYS_RES_IRQ:
start = res->sr_offset; start = PIC_IRQ_INT(res->sr_offset);
break; break;
default: default:
error = EINVAL; error = EINVAL;

8
sys/powerpc/mpc85xx/ocpbus.h
View File

@ -104,11 +104,9 @@
/* /*
* PIC definitions * PIC definitions
*/ */
#define ISA_IRQ_START 0
#define PIC_IRQ_START (ISA_IRQ_START + 16)
#define ISA_IRQ(n) (ISA_IRQ_START + (n)) #define ISA_IRQ(n) (INTR_VEC(ATPIC_ID, n))
#define PIC_IRQ_EXT(n) (PIC_IRQ_START + (n)) #define PIC_IRQ_EXT(n) (INTR_VEC(OPIC_ID, (n)))
#define PIC_IRQ_INT(n) (PIC_IRQ_START + 16 + (n)) #define PIC_IRQ_INT(n) (INTR_VEC(OPIC_ID, (16 + (n))))
#endif /* _MACHINE_OCP85XX_H */ #endif /* _MACHINE_OCP85XX_H */

10
sys/powerpc/mpc85xx/opic.c
View File

@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$");
* OpenPIC attachment to ocpbus * OpenPIC attachment to ocpbus
*/ */
static int openpic_ocpbus_probe(device_t); static int openpic_ocpbus_probe(device_t);
static uint32_t openpic_ocpbus_id(device_t);
static device_method_t openpic_ocpbus_methods[] = { static device_method_t openpic_ocpbus_methods[] = {
/* Device interface */ /* Device interface */
@ -63,6 +64,7 @@ static device_method_t openpic_ocpbus_methods[] = {
DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_ipi, openpic_ipi),
DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_mask, openpic_mask),
DEVMETHOD(pic_unmask, openpic_unmask), DEVMETHOD(pic_unmask, openpic_unmask),
DEVMETHOD(pic_id, openpic_ocpbus_id),
{ 0, 0 }, { 0, 0 },
}; };
@ -93,3 +95,11 @@ openpic_ocpbus_probe (device_t dev)
device_set_desc(dev, OPENPIC_DEVSTR); device_set_desc(dev, OPENPIC_DEVSTR);
return (BUS_PROBE_DEFAULT); return (BUS_PROBE_DEFAULT);
} }
static uint32_t
openpic_ocpbus_id (device_t dev)
{
return (OPIC_ID);
}

2
sys/powerpc/mpc85xx/pci_ocp.c
View File

@ -792,7 +792,7 @@ pci_ocp_alloc_resource(device_t dev, device_t child, int type, int *rid,
va = sc->sc_iomem_va; va = sc->sc_iomem_va;
break; break;
case SYS_RES_IRQ: case SYS_RES_IRQ:
if (start < PIC_IRQ_START) { if (INTR_IGN(start) == powerpc_ign_lookup(ATPIC_ID)) {
device_printf(dev, "%s requested ISA interrupt %lu\n", device_printf(dev, "%s requested ISA interrupt %lu\n",
device_get_nameunit(child), start); device_get_nameunit(child), start);
} }

7
sys/powerpc/ofw/ofw_pcib_pci.c
View File

@ -42,6 +42,8 @@
#include <dev/pci/pcireg.h> #include <dev/pci/pcireg.h>
#include <dev/pci/pcib_private.h> #include <dev/pci/pcib_private.h>
#include <machine/intr_machdep.h>
#include "pcib_if.h" #include "pcib_if.h"
static int ofw_pcib_pci_probe(device_t bus); static int ofw_pcib_pci_probe(device_t bus);
@ -149,6 +151,7 @@ ofw_pcib_pci_route_interrupt(device_t bridge, device_t dev, int intpin)
struct ofw_bus_iinfo *ii; struct ofw_bus_iinfo *ii;
struct ofw_pci_register reg; struct ofw_pci_register reg;
cell_t pintr, mintr; cell_t pintr, mintr;
phandle_t iparent;
uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
sc = device_get_softc(bridge); sc = device_get_softc(bridge);
@ -157,13 +160,13 @@ ofw_pcib_pci_route_interrupt(device_t bridge, device_t dev, int intpin)
pintr = intpin; pintr = intpin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg,
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf)) { &iparent, maskbuf)) {
/* /*
* If we've found a mapping, return it and don't map * If we've found a mapping, return it and don't map
* it again on higher levels - that causes problems * it again on higher levels - that causes problems
* in some cases, and never seems to be required. * in some cases, and never seems to be required.
*/ */
return (mintr); return (INTR_VEC(iparent, mintr));
} }
} else if (intpin >= 1 && intpin <= 4) { } else if (intpin >= 1 && intpin <= 4) {
/* /*

30
sys/powerpc/ofw/ofw_pcibus.c
View File

@ -212,6 +212,9 @@ ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno)
OF_getprop(iparent, "#interrupt-cells", &icells, OF_getprop(iparent, "#interrupt-cells", &icells,
sizeof(icells)); sizeof(icells));
if (iparent != 0)
intr[0] = INTR_VEC(iparent, intr[0]);
if (iparent != 0 && icells > 1) { if (iparent != 0 && icells > 1) {
powerpc_config_intr(intr[0], powerpc_config_intr(intr[0],
(intr[1] & 1) ? INTR_TRIGGER_LEVEL : (intr[1] & 1) ? INTR_TRIGGER_LEVEL :
@ -293,7 +296,7 @@ static int
ofw_pcibus_assign_interrupt(device_t dev, device_t child) ofw_pcibus_assign_interrupt(device_t dev, device_t child)
{ {
ofw_pci_intr_t intr; ofw_pci_intr_t intr;
phandle_t node; phandle_t node, iparent;
int isz; int isz;
node = ofw_bus_get_node(child); node = ofw_bus_get_node(child);
@ -303,8 +306,8 @@ ofw_pcibus_assign_interrupt(device_t dev, device_t child)
/* /*
* XXX: Right now we don't have anything sensible to do here, * XXX: Right now we don't have anything sensible to do here,
* since the ofw_imap stuff relies on nodes have a reg * since the ofw_imap stuff relies on nodes having a reg
* property. There exists ways around this, so the ePAPR * property. There exist ways around this, so the ePAPR
* spec will need to be studied. * spec will need to be studied.
*/ */
@ -317,19 +320,30 @@ ofw_pcibus_assign_interrupt(device_t dev, device_t child)
#endif #endif
} }
/*
* Try to determine the node's interrupt parent so we know which
* PIC to use.
*/
iparent = -1;
if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) < 0)
iparent = -1;
/* /*
* Any AAPL,interrupts property gets priority and is * Any AAPL,interrupts property gets priority and is
* fully specified (i.e. does not need routing) * fully specified (i.e. does not need routing)
*/ */
isz = OF_getprop(node, "AAPL,interrupts", &intr, sizeof(intr)); isz = OF_getprop(node, "AAPL,interrupts", &intr, sizeof(intr));
if (isz == sizeof(intr)) { if (isz == sizeof(intr))
return (intr); return ((iparent == -1) ? intr : INTR_VEC(iparent, intr));
}
isz = OF_getprop(node, "interrupts", &intr, sizeof(intr)); isz = OF_getprop(node, "interrupts", &intr, sizeof(intr));
if (isz != sizeof(intr)) { if (isz == sizeof(intr)) {
/* No property; our best guess is the intpin. */ if (iparent != -1)
intr = INTR_VEC(iparent, intr);
} else {
/* No property: our best guess is the intpin. */
intr = pci_get_intpin(child); intr = pci_get_intpin(child);
} }

8
sys/powerpc/powermac/cpcht.c
View File

@ -595,6 +595,7 @@ static void openpic_cpcht_config(device_t, u_int irq,
static void openpic_cpcht_enable(device_t, u_int irq, u_int vector); static void openpic_cpcht_enable(device_t, u_int irq, u_int vector);
static void openpic_cpcht_unmask(device_t, u_int irq); static void openpic_cpcht_unmask(device_t, u_int irq);
static void openpic_cpcht_eoi(device_t, u_int irq); static void openpic_cpcht_eoi(device_t, u_int irq);
static uint32_t openpic_cpcht_id(device_t);
static device_method_t openpic_cpcht_methods[] = { static device_method_t openpic_cpcht_methods[] = {
/* Device interface */ /* Device interface */
@ -609,6 +610,7 @@ static device_method_t openpic_cpcht_methods[] = {
DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_ipi, openpic_ipi),
DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_mask, openpic_mask),
DEVMETHOD(pic_unmask, openpic_cpcht_unmask), DEVMETHOD(pic_unmask, openpic_cpcht_unmask),
DEVMETHOD(pic_id, openpic_cpcht_id),
{ 0, 0 }, { 0, 0 },
}; };
@ -808,3 +810,9 @@ openpic_cpcht_eoi(device_t dev, u_int irq)
openpic_eoi(dev, irq); openpic_eoi(dev, irq);
} }
static uint32_t
openpic_cpcht_id(device_t dev)
{
return (ofw_bus_get_node(dev));
}

7
sys/powerpc/powermac/grackle.c
View File

@ -43,6 +43,7 @@
#include <dev/pci/pcireg.h> #include <dev/pci/pcireg.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/intr_machdep.h>
#include <machine/md_var.h> #include <machine/md_var.h>
#include <machine/pio.h> #include <machine/pio.h>
#include <machine/resource.h> #include <machine/resource.h>
@ -341,13 +342,15 @@ grackle_route_interrupt(device_t bus, device_t dev, int pin)
struct grackle_softc *sc; struct grackle_softc *sc;
struct ofw_pci_register reg; struct ofw_pci_register reg;
uint32_t pintr, mintr; uint32_t pintr, mintr;
phandle_t iparent;
uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
sc = device_get_softc(bus); sc = device_get_softc(bus);
pintr = pin; pintr = pin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
return (mintr); &iparent, maskbuf))
return (INTR_VEC(iparent, mintr));
/* Maybe it's a real interrupt, not an intpin */ /* Maybe it's a real interrupt, not an intpin */
if (pin > 4) if (pin > 4)

11
sys/powerpc/powermac/hrowpic.c
View File

@ -70,6 +70,7 @@ static void hrowpic_eoi(device_t, u_int);
static void hrowpic_ipi(device_t, u_int); static void hrowpic_ipi(device_t, u_int);
static void hrowpic_mask(device_t, u_int); static void hrowpic_mask(device_t, u_int);
static void hrowpic_unmask(device_t, u_int); static void hrowpic_unmask(device_t, u_int);
static uint32_t hrowpic_id(device_t dev);
static device_method_t hrowpic_methods[] = { static device_method_t hrowpic_methods[] = {
/* Device interface */ /* Device interface */
@ -80,6 +81,7 @@ static device_method_t hrowpic_methods[] = {
DEVMETHOD(pic_dispatch, hrowpic_dispatch), DEVMETHOD(pic_dispatch, hrowpic_dispatch),
DEVMETHOD(pic_enable, hrowpic_enable), DEVMETHOD(pic_enable, hrowpic_enable),
DEVMETHOD(pic_eoi, hrowpic_eoi), DEVMETHOD(pic_eoi, hrowpic_eoi),
DEVMETHOD(pic_id, hrowpic_id),
DEVMETHOD(pic_ipi, hrowpic_ipi), DEVMETHOD(pic_ipi, hrowpic_ipi),
DEVMETHOD(pic_mask, hrowpic_mask), DEVMETHOD(pic_mask, hrowpic_mask),
DEVMETHOD(pic_unmask, hrowpic_unmask), DEVMETHOD(pic_unmask, hrowpic_unmask),
@ -169,6 +171,8 @@ hrowpic_attach(device_t dev)
hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff); hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff);
powerpc_register_pic(dev, 64); powerpc_register_pic(dev, 64);
root_pic = dev; /* Heathrow systems have only one PIC */
return (0); return (0);
} }
@ -282,3 +286,10 @@ hrowpic_unmask(device_t dev, u_int irq)
sc = device_get_softc(dev); sc = device_get_softc(dev);
hrowpic_toggle_irq(sc, irq, 1); hrowpic_toggle_irq(sc, irq, 1);
} }
static uint32_t
hrowpic_id(device_t dev)
{
return (ofw_bus_get_node(dev));
}

17
sys/powerpc/powermac/macgpio.c
View File

@ -35,15 +35,16 @@
#include <sys/malloc.h> #include <sys/malloc.h>
#include <sys/module.h> #include <sys/module.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h> #include <sys/rman.h>
#include <machine/vmparam.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/pmap.h> #include <vm/pmap.h>
#include <machine/pmap.h>
#include <machine/bus.h>
#include <machine/intr_machdep.h>
#include <machine/pmap.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <machine/vmparam.h>
#include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h> #include <dev/ofw/ofw_bus_subr.h>
@ -150,8 +151,7 @@ macgpio_attach(device_t dev)
{ {
struct macgpio_softc *sc; struct macgpio_softc *sc;
struct macgpio_devinfo *dinfo; struct macgpio_devinfo *dinfo;
phandle_t root; phandle_t root, child, iparent;
phandle_t child;
device_t cdev; device_t cdev;
uint32_t irq; uint32_t irq;
@ -186,10 +186,13 @@ macgpio_attach(device_t dev)
resource_list_init(&dinfo->mdi_resources); resource_list_init(&dinfo->mdi_resources);
if (OF_getprop(child,"interrupts",&irq, sizeof(irq)) == if (OF_getprop(child, "interrupts", &irq, sizeof(irq)) ==
sizeof(irq)) { sizeof(irq)) {
OF_searchprop(child, "interrupt-parent", &iparent,
sizeof(iparent));
resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ,
0, irq, irq, 1); 0, INTR_VEC(iparent, irq), INTR_VEC(iparent, irq),
1);
} }
/* Fix messed-up offsets */ /* Fix messed-up offsets */

18
sys/powerpc/powermac/macio.c
View File

@ -37,15 +37,16 @@
#include <sys/malloc.h> #include <sys/malloc.h>
#include <sys/module.h> #include <sys/module.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h> #include <sys/rman.h>
#include <machine/vmparam.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/pmap.h> #include <vm/pmap.h>
#include <machine/pmap.h>
#include <machine/bus.h>
#include <machine/intr_machdep.h>
#include <machine/pmap.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <machine/vmparam.h>
#include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h> #include <dev/ofw/ofw_bus_subr.h>
@ -186,6 +187,7 @@ macio_get_quirks(const char *name)
static void static void
macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo) macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo)
{ {
phandle_t iparent;
int *intr; int *intr;
int i, nintr; int i, nintr;
int icells; int icells;
@ -211,11 +213,17 @@ macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo)
if (intr[0] == -1) if (intr[0] == -1)
return; return;
if (OF_getprop(devnode, "interrupt-parent", &iparent, sizeof(iparent))
<= 0)
panic("Interrupt but no interrupt parent!\n");
for (i = 0; i < nintr; i+=icells) { for (i = 0; i < nintr; i+=icells) {
resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ,
dinfo->mdi_ninterrupts, intr[i], intr[i], 1); dinfo->mdi_ninterrupts, INTR_VEC(iparent, intr[i]),
INTR_VEC(iparent, intr[i]), 1);
dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = intr[i]; dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] =
INTR_VEC(iparent, intr[i]);
dinfo->mdi_ninterrupts++; dinfo->mdi_ninterrupts++;
} }
} }

9
sys/powerpc/powermac/openpic_macio.c
View File

@ -59,6 +59,7 @@ __FBSDID("$FreeBSD$");
* MacIO interface * MacIO interface
*/ */
static int openpic_macio_probe(device_t); static int openpic_macio_probe(device_t);
static uint32_t openpic_macio_id(device_t);
static device_method_t openpic_macio_methods[] = { static device_method_t openpic_macio_methods[] = {
/* Device interface */ /* Device interface */
@ -73,6 +74,7 @@ static device_method_t openpic_macio_methods[] = {
DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_ipi, openpic_ipi),
DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_mask, openpic_mask),
DEVMETHOD(pic_unmask, openpic_unmask), DEVMETHOD(pic_unmask, openpic_unmask),
DEVMETHOD(pic_id, openpic_macio_id),
{ 0, 0 }, { 0, 0 },
}; };
@ -96,3 +98,10 @@ openpic_macio_probe(device_t dev)
device_set_desc(dev, OPENPIC_DEVSTR); device_set_desc(dev, OPENPIC_DEVSTR);
return (0); return (0);
} }
static uint32_t
openpic_macio_id(device_t dev)
{
return (ofw_bus_get_node(dev));
}

14
sys/powerpc/powermac/uninorth.c
View File

@ -144,9 +144,9 @@ DRIVER_MODULE(unin, nexus, unin_chip_driver, unin_chip_devclass, 0, 0);
static void static void
unin_chip_add_intr(phandle_t devnode, struct unin_chip_devinfo *dinfo) unin_chip_add_intr(phandle_t devnode, struct unin_chip_devinfo *dinfo)
{ {
phandle_t iparent;
int *intr; int *intr;
int i, nintr; int i, nintr;
phandle_t iparent;
int icells; int icells;
if (dinfo->udi_ninterrupts >= 6) { if (dinfo->udi_ninterrupts >= 6) {
@ -176,9 +176,17 @@ unin_chip_add_intr(phandle_t devnode, struct unin_chip_devinfo *dinfo)
for (i = 0; i < nintr; i+=icells) { for (i = 0; i < nintr; i+=icells) {
resource_list_add(&dinfo->udi_resources, SYS_RES_IRQ, resource_list_add(&dinfo->udi_resources, SYS_RES_IRQ,
dinfo->udi_ninterrupts, intr[i], intr[i], 1); dinfo->udi_ninterrupts, INTR_VEC(iparent, intr[i]),
INTR_VEC(iparent, intr[i]), 1);
dinfo->udi_interrupts[dinfo->udi_ninterrupts] = intr[i]; if (icells > 1) {
powerpc_config_intr(INTR_VEC(iparent, intr[i]),
(intr[i+1] & 1) ? INTR_TRIGGER_LEVEL :
INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
}
dinfo->udi_interrupts[dinfo->udi_ninterrupts] =
INTR_VEC(iparent, intr[i]);
dinfo->udi_ninterrupts++; dinfo->udi_ninterrupts++;
} }
} }

5
sys/powerpc/powermac/uninorthpci.c
View File

@ -356,14 +356,15 @@ uninorth_route_interrupt(device_t bus, device_t dev, int pin)
struct uninorth_softc *sc; struct uninorth_softc *sc;
struct ofw_pci_register reg; struct ofw_pci_register reg;
uint32_t pintr, mintr; uint32_t pintr, mintr;
phandle_t iparent;
uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
sc = device_get_softc(bus); sc = device_get_softc(bus);
pintr = pin; pintr = pin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf)) &iparent, maskbuf))
return (mintr); return (INTR_VEC(iparent, mintr));
/* Maybe it's a real interrupt, not an intpin */ /* Maybe it's a real interrupt, not an intpin */
if (pin > 4) if (pin > 4)

104
sys/powerpc/powerpc/intr_machdep.c
View File

@ -85,14 +85,6 @@
#include "pic_if.h" #include "pic_if.h"
#ifdef MPC85XX
#define ISA_IRQ_COUNT 16
#endif
#ifndef ISA_IRQ_COUNT
#define ISA_IRQ_COUNT 0
#endif
#define MAX_STRAY_LOG 5 #define MAX_STRAY_LOG 5
MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data"); MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data");
@ -108,20 +100,25 @@ struct powerpc_intr {
enum intr_polarity pol; enum intr_polarity pol;
}; };
struct pic {
device_t pic;
uint32_t pic_id;
int ipi_irq;
};
static struct mtx intr_table_lock; static struct mtx intr_table_lock;
static struct powerpc_intr *powerpc_intrs[INTR_VECTORS]; static struct powerpc_intr *powerpc_intrs[INTR_VECTORS];
static struct pic piclist[MAX_PICS];
static u_int nvectors; /* Allocated vectors */ static u_int nvectors; /* Allocated vectors */
static u_int npics; /* PICs registered */
static u_int stray_count; static u_int stray_count;
device_t root_pic;
#ifdef SMP #ifdef SMP
static void *ipi_cookie; static void *ipi_cookie;
#endif #endif
static u_int ipi_irq;
device_t pic;
device_t pic8259;
static void static void
intr_init(void *dummy __unused) intr_init(void *dummy __unused)
{ {
@ -198,21 +195,13 @@ static int
powerpc_map_irq(struct powerpc_intr *i) powerpc_map_irq(struct powerpc_intr *i)
{ {
#if ISA_IRQ_COUNT > 0 i->intline = INTR_INTLINE(i->irq);
if (i->irq < ISA_IRQ_COUNT) { i->pic = piclist[INTR_IGN(i->irq)].pic;
if (pic8259 == NULL) {
i->pic = pic; /* Try a best guess if that failed */
i->intline = 0; if (i->pic == NULL)
return (ENXIO); i->pic = root_pic;
}
i->pic = pic8259;
i->intline = i->irq;
return (0);
}
#endif
i->pic = pic;
i->intline = i->irq - ISA_IRQ_COUNT;
return (0); return (0);
} }
@ -243,16 +232,44 @@ powerpc_intr_unmask(void *arg)
void void
powerpc_register_pic(device_t dev, u_int ipi) powerpc_register_pic(device_t dev, u_int ipi)
{ {
int i;
pic = dev; mtx_lock(&intr_table_lock);
ipi_irq = ipi + ISA_IRQ_COUNT;
for (i = 0; i < npics; i++) {
if (piclist[i].pic_id == PIC_ID(dev))
break;
}
piclist[i].pic = dev;
piclist[i].pic_id = PIC_ID(dev);
piclist[i].ipi_irq = ipi;
if (i == npics)
npics++;
mtx_unlock(&intr_table_lock);
} }
void int
powerpc_register_8259(device_t dev) powerpc_ign_lookup(uint32_t pic_id)
{ {
int i;
pic8259 = dev; mtx_lock(&intr_table_lock);
for (i = 0; i < npics; i++) {
if (piclist[i].pic_id == pic_id) {
mtx_unlock(&intr_table_lock);
return (i);
}
}
piclist[i].pic = NULL;
piclist[i].pic_id = pic_id;
piclist[i].ipi_irq = 0;
npics++;
mtx_unlock(&intr_table_lock);
return (i);
} }
int int
@ -260,17 +277,28 @@ powerpc_enable_intr(void)
{ {
struct powerpc_intr *i; struct powerpc_intr *i;
int error, vector; int error, vector;
#ifdef SMP
int n;
#endif
if (pic == NULL) if (npics == 0)
panic("no PIC detected\n"); panic("no PIC detected\n");
#ifdef SMP #ifdef SMP
/* Install an IPI handler. */ /* Install an IPI handler. */
error = powerpc_setup_intr("IPI", ipi_irq, powerpc_ipi_handler,
NULL, NULL, INTR_TYPE_MISC | INTR_EXCL | INTR_FAST, &ipi_cookie); for (n = 0; n < npics; n++) {
if (error) { if (piclist[n].pic != root_pic)
printf("unable to setup IPI handler\n"); continue;
return (error);
error = powerpc_setup_intr("IPI",
INTR_VEC(piclist[n].pic_id, piclist[n].ipi_irq),
powerpc_ipi_handler, NULL, NULL,
INTR_TYPE_MISC | INTR_EXCL | INTR_FAST, &ipi_cookie);
if (error) {
printf("unable to setup IPI handler\n");
return (error);
}
} }
#endif #endif

2
sys/powerpc/powerpc/mp_machdep.c
View File

@ -319,7 +319,7 @@ ipi_send(struct pcpu *pc, int ipi)
pc, pc->pc_cpuid, ipi); pc, pc->pc_cpuid, ipi);
atomic_set_32(&pc->pc_ipimask, (1 << ipi)); atomic_set_32(&pc->pc_ipimask, (1 << ipi));
PIC_IPI(pic, pc->pc_cpuid); PIC_IPI(root_pic, pc->pc_cpuid);
CTR1(KTR_SMP, "%s: sent", __func__); CTR1(KTR_SMP, "%s: sent", __func__);
} }

39
sys/powerpc/powerpc/openpic.c
View File

@ -52,6 +52,7 @@ devclass_t openpic_devclass;
/* /*
* Local routines * Local routines
*/ */
static int openpic_intr(void *arg);
static __inline uint32_t static __inline uint32_t
openpic_read(struct openpic_softc *sc, u_int reg) openpic_read(struct openpic_softc *sc, u_int reg)
@ -110,6 +111,29 @@ openpic_attach(device_t dev)
DELAY(100); DELAY(100);
} }
/* Check if this is a cascaded PIC */
sc->sc_irq = 0;
sc->sc_intr = NULL;
if (resource_list_find(BUS_GET_RESOURCE_LIST(device_get_parent(dev),
dev), SYS_RES_IRQ, 0) != NULL) {
sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->sc_irq, RF_ACTIVE);
/* XXX Cascaded PICs pass NULL trapframes! */
bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
openpic_intr, NULL, dev, &sc->sc_icookie);
}
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
x = openpic_read(sc, OPENPIC_FEATURE); x = openpic_read(sc, OPENPIC_FEATURE);
switch (x & OPENPIC_FEATURE_VERSION_MASK) { switch (x & OPENPIC_FEATURE_VERSION_MASK) {
case 1: case 1:
@ -185,6 +209,10 @@ openpic_attach(device_t dev)
powerpc_register_pic(dev, sc->sc_nirq); powerpc_register_pic(dev, sc->sc_nirq);
/* If this is not a cascaded PIC, it must be the root PIC */
if (sc->sc_intr == NULL)
root_pic = dev;
return (0); return (0);
} }
@ -212,6 +240,17 @@ openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
} }
static int
openpic_intr(void *arg)
{
device_t dev = (device_t)(arg);
/* XXX Cascaded PICs do not pass non-NULL trapframes! */
openpic_dispatch(dev, NULL);
return (FILTER_HANDLED);
}
void void
openpic_dispatch(device_t dev, struct trapframe *tf) openpic_dispatch(device_t dev, struct trapframe *tf)
{ {

4
sys/powerpc/powerpc/pic_if.m
View File

@ -60,6 +60,10 @@ METHOD void ipi {
u_int cpu; u_int cpu;
}; };
METHOD uint32_t id {
device_t dev;
};
METHOD void mask { METHOD void mask {
device_t dev; device_t dev;
u_int irq; u_int irq;

2
sys/sparc64/ebus/ebus.c
View File

@ -619,7 +619,7 @@ ebus_setup_dinfo(device_t dev, struct ebus_softc *sc, phandle_t node)
intr = intrs[i]; intr = intrs[i];
rv = ofw_bus_lookup_imap(node, &sc->sc_iinfo, &reg, rv = ofw_bus_lookup_imap(node, &sc->sc_iinfo, &reg,
sizeof(reg), &intr, sizeof(intr), &rintr, sizeof(reg), &intr, sizeof(intr), &rintr,
sizeof(rintr), maskbuf); sizeof(rintr), NULL, maskbuf);
#ifndef SUN4V #ifndef SUN4V
if (rv != 0) if (rv != 0)
rintr = INTMAP_VEC(sc->sc_ign, rintr); rintr = INTMAP_VEC(sc->sc_ign, rintr);

2
sys/sparc64/isa/ofw_isa.c
View File

@ -113,7 +113,7 @@ ofw_isa_route_intr(device_t bridge, phandle_t node, struct ofw_bus_iinfo *ii,
* fully specified, so we may not continue to map. * fully specified, so we may not continue to map.
*/ */
if (!ofw_bus_lookup_imap(node, ii, &reg, sizeof(reg), if (!ofw_bus_lookup_imap(node, ii, &reg, sizeof(reg),
&intr, sizeof(intr), &mintr, sizeof(mintr), maskbuf)) { &intr, sizeof(intr), &mintr, sizeof(mintr), NULL, maskbuf)) {
/* Try routing at the parent bridge. */ /* Try routing at the parent bridge. */
mintr = PCIB_ROUTE_INTERRUPT(pbridge, bridge, intr); mintr = PCIB_ROUTE_INTERRUPT(pbridge, bridge, intr);
} }

2
sys/sparc64/pci/fire.c
View File

@ -1476,7 +1476,7 @@ fire_route_interrupt(device_t bridge, device_t dev, int pin)
pintr = pin; pintr = pin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
&reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf) != 0) NULL, maskbuf) != 0)
return (mintr); return (mintr);
device_printf(bridge, "could not route pin %d for device %d.%d\n", device_printf(bridge, "could not route pin %d for device %d.%d\n",

2
sys/sparc64/pci/ofw_pcib_subr.c
View File

@ -77,7 +77,7 @@ ofw_pcib_gen_route_interrupt(device_t bridge, device_t dev, int intpin)
pintr = intpin; pintr = intpin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg,
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf)) { NULL, maskbuf)) {
/* /*
* If we've found a mapping, return it and don't map * If we've found a mapping, return it and don't map
* it again on higher levels - that causes problems * it again on higher levels - that causes problems

2
sys/sparc64/pci/psycho.c
View File

@ -1046,7 +1046,7 @@ psycho_route_interrupt(device_t bridge, device_t dev, int pin)
pintr = pin; pintr = pin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
&reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf)) NULL, maskbuf))
return (mintr); return (mintr);
/* /*
* If this is outside of the range for an intpin, it's likely a full * If this is outside of the range for an intpin, it's likely a full

2
sys/sparc64/pci/schizo.c
View File

@ -1077,7 +1077,7 @@ schizo_route_interrupt(device_t bridge, device_t dev, int pin)
pintr = pin; pintr = pin;
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
&reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
maskbuf)) NULL, maskbuf))
return (mintr); return (mintr);
device_printf(bridge, "could not route pin %d for device %d.%d\n", device_printf(bridge, "could not route pin %d for device %d.%d\n",