arm32: Align arguments of sync_icache() syscall to cacheline size.
Otherwise, we may miss synchronization of the last cacheline. MFC after: 3 days
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@ -68,12 +68,9 @@ sync_icache(uintptr_t addr, size_t len)
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size_t size;
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vm_offset_t rv;
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/*
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* Align starting address to even number because value of "1"
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* is used as return value for success.
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*/
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len += addr & 1;
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addr &= ~1;
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/* Align starting address to cacheline size */
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len += addr & cpuinfo.dcache_line_mask;
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addr &= ~cpuinfo.dcache_line_mask;
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/* Break whole range to pages. */
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do {
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