Add convenience macros for the full register set and use them to replace
magic constants in clkbrd.c Info from: OpenSolaris
This commit is contained in:
Marius Strobl
parent
67be19576a
commit
edff99cad1
@ -131,19 +131,20 @@ clkbrd_attach(device_t dev)
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slots = 4;
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r = bus_space_read_1(sc->sc_bt[CLKBRD_CLK], sc->sc_bh[CLKBRD_CLK],
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CLK_STS1);
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switch (r & 0xc0) {
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case 0x40:
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switch (r & CLK_STS1_SLOTS_MASK) {
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case CLK_STS1_SLOTS_16:
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slots = 16;
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break;
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case 0xc0:
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case CLK_STS1_SLOTS_8:
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slots = 8;
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break;
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case 0x80:
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case CLK_STS1_SLOTS_4:
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if (sc->sc_flags & CLKBRD_HAS_CLKVER) {
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r = bus_space_read_1(sc->sc_bt[CLKBRD_CLKVER],
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sc->sc_bh[CLKBRD_CLKVER], 0);
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if (r != 0 && (r & 0x80) == 0)
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slots = 5;
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sc->sc_bh[CLKBRD_CLKVER], CLKVER_SLOTS);
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if (r != 0 &&
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(r & CLKVER_SLOTS_MASK) == CLKVER_SLOTS_PLUS)
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slots = 5;
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}
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}
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2004 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -28,20 +29,69 @@
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* $FreeBSD$
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*/
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#define CLK_CTRL 0x00
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#define CLK_STS1 0x10
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#define CLK_STS2 0x20
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#define CLK_PSTS1 0x30
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#define CLK_PPRES 0x40
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#define CLK_TEMP 0x50
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#define CLK_IRQ 0x60
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#define CLK_PSTS2 0x70
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#ifndef _SPARC64_FHC_CLKBRDREG_H_
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#define _SPARC64_FHC_CLKBRDREG_H_
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#define CLK_CTRL_IEN_FAN 0x80 /* intr enable: fan failure */
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#define CLK_CTRL_IEN_DC 0x40 /* intr enable: pwr supply DC */
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#define CLK_CTRL_IEN_AC 0x20 /* intr enable: AC pwr supply */
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#define CLK_CTRL_IEN_BRD 0x10 /* intr enable: board insert */
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#define CLK_CTRL_POFF 0x08 /* turn off system power */
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#define CLK_CTRL_LLED 0x04 /* left led (reversed) */
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#define CLK_CTRL_MLED 0x02 /* middle led */
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#define CLK_CTRL_RLED 0x01 /* right led */
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/* register bank 0 */
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#define CLK_CF_REG2 0x20 /* clock frequency register 2 */
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#define CLK_CF_REG2_REN_RCONS 0x80 /* reset enable: remote console */
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#define CLK_CF_REG2_REN_GEN 0x40 /* reset enable: frequency change */
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#define CLK_CF_REG2_REN_WDOG 0x20 /* reset enable: watchdog */
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#define CLK_CF_REG2_DIV1 0x10 /* CPU module divisor bit 1 */
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#define CLK_CF_REG2_RANGE 0x0c /* clock range */
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#define CLK_CF_REG2_DIV0 0x02 /* CPU module divisor bit 0 */
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#define CLK_CF_REG2_FREQ8 0x01 /* frequency bit 8 */
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/* register bank 1 */
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#define CLK_CTRL 0x00 /* system control register */
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#define CLK_CTRL_IEN_FAN 0x80 /* intr enable: fan failure */
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#define CLK_CTRL_IEN_DC 0x40 /* intr enable: power supply DC */
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#define CLK_CTRL_IEN_AC 0x20 /* intr enable: AC power */
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#define CLK_CTRL_IEN_BRD 0x10 /* intr enable: board insert */
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#define CLK_CTRL_POFF 0x08 /* turn off system power */
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#define CLK_CTRL_LLED 0x04 /* left led (reversed) */
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#define CLK_CTRL_MLED 0x02 /* middle led */
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#define CLK_CTRL_RLED 0x01 /* right led */
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#define CLK_STS1 0x10 /* system status register 1 */
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#define CLK_STS1_SLOTS_MASK 0xc0 /* system status 1 slots mask */
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#define CLK_STS1_SLOTS_16 0x40 /* 16 slots */
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#define CLK_STS1_SLOTS_8 0xc0 /* 8 slots */
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#define CLK_STS1_SLOTS_4 0x80 /* 4 slots */
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#define CLK_STS1_SLOTS_TESTBED 0x00 /* test machine */
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#define CLK_STS1_SECURE 0x20 /* key in position secure (reversed) */
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#define CLK_STS1_FAN 0x10 /* fan tray present (reversed) */
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#define CLK_STS1_BRD 0x08 /* board inserted (reversed) */
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#define CLK_STS1_PS0 0x04 /* power supply 0 present (reversed) */
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#define CLK_STS1_RST_WDOG 0x02 /* rst by: watchdog (reversed) */
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#define CLK_STS1_RST_GEN 0x01 /* rst by: freq change (reversed) */
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#define CLK_STS2 0x20 /* system status register 2 */
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#define CLK_STS2_RST_RCONS 0x80 /* rst by: remote console (reversed) */
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#define CLK_STS2_OK_PS0 0x40 /* ok: power supply 0 */
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#define CLK_STS2_OK_33V 0x20 /* ok: 3.3V on clock board */
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#define CLK_STS2_OK_50V 0x10 /* ok: 5.0V on clock board */
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#define CLK_STS2_FAIL_AC 0x08 /* failed: AC power */
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#define CLK_STS2_FAIL_FAN 0x04 /* failed: rack fans */
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#define CLK_STS2_OK_ACFAN 0x02 /* ok: 4 AC box fans */
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#define CLK_STS2_OK_KEYFAN 0x01 /* ok: keyswitch fans */
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#define CLK_PSTS1 0x30 /* power supply 1 status register */
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#define CLK_PSTS1_PS 0x80 /* power supply 1 present (reversed) */
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#define CLK_PPRES 0x40 /* power supply presence register */
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#define CLK_PPRES_CSHARE 0x80 /* current share backplane */
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#define CLK_PPRES_OK_MASK 0x7f /* precharge and peripheral pwr mask */
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#define CLK_PPRES_OK_P_5V 0x40 /* ok: peripheral 5V */
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#define CLK_PPRES_OK_P_12V 0x20 /* ok: peripheral 12V */
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#define CLK_PPRES_OK_AUX_5V 0x10 /* ok: auxiliary 5V */
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#define CLK_PPRES_OK_PP_5V 0x08 /* ok: peripheral 5V precharge */
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#define CLK_PPRES_OK_PP_12V 0x04 /* ok: peripheral 12V precharge */
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#define CLK_PPRES_OK_SP_3V 0x02 /* ok: system 3.3V precharge */
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#define CLK_PPRES_OK_SP_5V 0x01 /* ok: system 5V precharge */
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#define CLK_TEMP 0x50 /* temperature register */
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#define CLK_IDIAG 0x60 /* interrupt diagnostic register */
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#define CLK_PSTS2 0x70 /* power supply 2 status register */
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/* register bank 2 */
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#define CLKVER_SLOTS 0x00 /* clock version slots register */
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#define CLKVER_SLOTS_MASK 0x80 /* clock version slots mask */
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#define CLKVER_SLOTS_PLUS 0x00 /* plus system (reversed) */
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#endif /* !_SPARC64_FHC_CLKBRDREG_H_ */
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