Fix COP0 hazards for XLR and XLP

The XLR CPUs do not have any software visible hazards for COP0 operations.
On XLP the hazard is a ehb, since it is mips64r2.

sys/mips/include/asm.h

@@ -855,6 +855,15 @@ _C_LABEL(x):
  * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture 
  *    For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
  */
+#if defined(CPU_NLM)
+#define	HAZARD_DELAY	sll $0,3
+#define	ITLBNOPFIX	sll $0,3
+#elif defined(CPU_RMI)
+#define	HAZARD_DELAY
+#define	ITLBNOPFIX
+#else
 #define	ITLBNOPFIX	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
 #define	HAZARD_DELAY	nop;nop;nop;nop;nop;
+#endif
+
 #endif /* !_MACHINE_ASM_H_ */

sys/mips/include/cpufunc.h

@@ -69,7 +69,7 @@
 static __inline void
 mips_barrier(void)
 {
-#ifdef CPU_CNMIPS
+#if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
 	__asm __volatile("" : : : "memory");
 #else
 	__asm __volatile (".set noreorder\n\t"

sys/mips/include/cpuregs.h

@@ -200,6 +200,8 @@
 /* CPU dependent mtc0 hazard hook */
 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
 #define	COP0_SYNC
+#elif defined(CPU_NLM)
+#define	COP0_SYNC	.word 0xc0	/* ehb */
 #elif defined(CPU_SB1)
 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
 #else