Remove unused #defines. All this is now retrieved from the device tree.
MFC after: 1 week
This commit is contained in:
Rafal Jaworowski
parent
d7c784b1a8
commit
f05c7d9044
@ -34,132 +34,6 @@
|
||||
#ifndef _MVREG_H_
|
||||
#define _MVREG_H_
|
||||
|
||||
/*
|
||||
* Interrupt sources
|
||||
*/
|
||||
#if defined(SOC_MV_ORION)
|
||||
|
||||
#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */
|
||||
#define MV_INT_UART0 3 /* UART0 Interrupt */
|
||||
#define MV_INT_UART1 4
|
||||
#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */
|
||||
#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */
|
||||
#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */
|
||||
#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */
|
||||
#define MV_INT_PEX0_ERR 10 /* PCI Express Error */
|
||||
#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */
|
||||
#define MV_INT_PCI_ERR 15 /* PCI Error */
|
||||
#define MV_INT_USB_BERR 16 /* USB Bridge Error */
|
||||
#define MV_INT_USB_CI 17 /* USB Controller interrupt */
|
||||
#define MV_INT_GBERX 18 /* GbE receive interrupt */
|
||||
#define MV_INT_GBETX 19 /* GbE transmit interrupt */
|
||||
#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */
|
||||
#define MV_INT_GBESUM 21 /* GbE summary interrupt */
|
||||
#define MV_INT_GBEERR 22 /* GbE error interrupt */
|
||||
#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */
|
||||
#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */
|
||||
#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */
|
||||
#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */
|
||||
#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */
|
||||
#define MV_INT_SATA 29 /* Serial-ATA Interrupt */
|
||||
|
||||
#elif defined(SOC_MV_KIRKWOOD)
|
||||
|
||||
#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */
|
||||
#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */
|
||||
#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */
|
||||
#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */
|
||||
#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */
|
||||
#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */
|
||||
#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */
|
||||
#define MV_INT_GBERX 12 /* GbE0 receive interrupt */
|
||||
#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */
|
||||
#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */
|
||||
#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */
|
||||
#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */
|
||||
#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */
|
||||
#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */
|
||||
#define MV_INT_USB_CI 19 /* USB Controller interrupt */
|
||||
#define MV_INT_SATA 21 /* Serial-ATA Interrupt */
|
||||
#define MV_INT_CESA 22 /* Security engine completion int. */
|
||||
#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */
|
||||
#define MV_INT_UART0 33 /* UART0 Interrupt */
|
||||
#define MV_INT_UART1 34
|
||||
#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */
|
||||
#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */
|
||||
#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */
|
||||
#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */
|
||||
#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */
|
||||
#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */
|
||||
#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */
|
||||
#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */
|
||||
#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */
|
||||
#define MV_INT_PEX0_ERR 44 /* PCI Express Error */
|
||||
#define MV_INT_GBEERR 46 /* GbE0 error interrupt */
|
||||
#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */
|
||||
#define MV_INT_USB_BERR 48 /* USB Bridge Error */
|
||||
|
||||
#elif defined(SOC_MV_DISCOVERY)
|
||||
|
||||
#define MV_INT_ERRSUM 0 /* Summary of error interrupts */
|
||||
#define MV_INT_SPI 1 /* SPI interrupt */
|
||||
#define MV_INT_TWSI0 2 /* TWSI0 interrupt */
|
||||
#define MV_INT_TWSI1 3 /* TWSI1 interrupt */
|
||||
#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */
|
||||
#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */
|
||||
#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */
|
||||
#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */
|
||||
#define MV_INT_TIMER0 8 /* Timer0 interrupt */
|
||||
#define MV_INT_TIMER1 9 /* Timer1 interrupt */
|
||||
#define MV_INT_TIMER2 10 /* Timer2 interrupt */
|
||||
#define MV_INT_TIMER3 11 /* Timer3 interrupt */
|
||||
#define MV_INT_UART0 12 /* UART0 interrupt */
|
||||
#define MV_INT_UART1 13 /* UART1 interrupt */
|
||||
#define MV_INT_UART2 14 /* UART2 interrupt */
|
||||
#define MV_INT_UART3 15 /* UART3 interrupt */
|
||||
#define MV_INT_USB0 16 /* USB0 interrupt */
|
||||
#define MV_INT_USB1 17 /* USB1 interrupt */
|
||||
#define MV_INT_USB2 18 /* USB2 interrupt */
|
||||
#define MV_INT_CESA 19 /* Crypto engine completion interrupt */
|
||||
#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */
|
||||
#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */
|
||||
#define MV_INT_SATA 26 /* SATA interrupt */
|
||||
#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */
|
||||
#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */
|
||||
#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */
|
||||
#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */
|
||||
#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */
|
||||
#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */
|
||||
#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */
|
||||
#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */
|
||||
#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */
|
||||
#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */
|
||||
#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */
|
||||
#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */
|
||||
#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */
|
||||
#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */
|
||||
#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */
|
||||
#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */
|
||||
#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */
|
||||
#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */
|
||||
#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */
|
||||
#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */
|
||||
#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */
|
||||
#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */
|
||||
#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */
|
||||
#define MV_INT_DEV_ERR 65 /* Device bus error */
|
||||
#define MV_INT_IDMA_ERR 66 /* DMA error */
|
||||
#define MV_INT_CPU_ERR 67 /* CPU error */
|
||||
#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */
|
||||
#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */
|
||||
#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */
|
||||
#define MV_INT_USB_ERR 72 /* USB error */
|
||||
#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */
|
||||
#define MV_INT_XOR_ERR 74 /* XOR engine error */
|
||||
#define MV_INT_WD 79 /* WD Timer interrupt */
|
||||
|
||||
#endif /* SOC_MV_ORION */
|
||||
|
||||
#define BRIDGE_IRQ_CAUSE 0x10
|
||||
#define BRIGDE_IRQ_MASK 0x14
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user