Update to "stable-167" release; totally reimplements media detection.
Submitted by: Ustimenko Semen <semen@iclub.nsu.ru>
This commit is contained in:
Jordan K. Hubbard
parent
7ec73f6417
commit
f082783a66
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Load Diff
725
sys/pci/if_tx.c
725
sys/pci/if_tx.c
File diff suppressed because it is too large
Load Diff
@ -23,7 +23,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* stable-166
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* stable-167
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*
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*/
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@ -40,7 +40,7 @@
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/* packet to new allocated mbuf, */
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/* receive directly to mbuf */
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/*#define TX_FRAG_LIST 1 Eliminites need of copy xmiting */
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#define TX_FRAG_LIST 1 /* Eliminites need of copy xmiting */
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/* packet to static buffer, xmit from */
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/* mbuf directly */
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@ -167,6 +167,15 @@
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#define GENCTL_SOFTWARE2 0x00002000
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#define GENCTL_RESET_PHY 0x00004000
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#define NVCTL_ENABLE_MEMORY_MAP 0x00000001
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#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002
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#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004
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#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008
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#define NVCTL_GP1 0x00000010
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#define NVCTL_GP2 0x00000020
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#define NVCTL_CARDBUS_MODE 0x00000040
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#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7)
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#define RXCON_SAVE_ERRORED_PACKETS 0x00000001
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#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002
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#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004
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@ -192,9 +201,11 @@
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/*
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* National Semiconductor's DP83840A Registers and bits
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*/
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#define DP83840_OUI 0x080017
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#define DP83840_BMCR 0x00 /* Control register */
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#define DP83840_BMSR 0x01 /* Status rgister */
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#define DP83840_ANAR 0x04 /* Autonegotiation advertising register */
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#define DP83840_LPAR 0x05 /* Link Partner Ability register */
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#define DP83840_ANER 0x06 /* Auto-Negotiation Expansion Register */
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#define DP83840_PAR 0x19 /* PHY Address Register */
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#define DP83840_PHYIDR1 0x02
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@ -219,16 +230,37 @@
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#define ANER_MULTIPLE_LINK_FAULT 0x10
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/* ANAR and LPAR have the same bits, define them only once */
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#define ANAR_10 0x0020
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#define ANAR_10_FD 0x0040
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#define ANAR_100 0x0080
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#define ANAR_100_FD 0x0100
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#define ANAR_100_TX 0x0080
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#define ANAR_100_TX_FD 0x0100
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#define ANAR_100_T4 0x0200
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/*
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* Quality Semiconductor's QS6612 registers and bits
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*/
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#define QS6612_OUI 0x006051
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#define QS6612_INTSTAT 29
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#define QS6612_INTMASK 30
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#define INTSTAT_AN_COMPLETE 0x40 /* Autonegotiation complete */
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#define INTSTAT_RF_DETECTED 0x20 /* Remote Fault detected */
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#define INTSTAT_LINK_STATUS 0x10 /* Link status changed */
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#define INTSTAT_AN_LP_ACK 0x08 /* Autoneg. LP Acknoledge */
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#define INTSTAT_PD_FAULT 0x04 /* Parallel Detection Fault */
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#define INTSTAT_AN_PAGE 0x04 /* Autoneg. Page Received */
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#define INTSTAT_RE_CNT_FULL 0x01 /* Receive Error Counter Full */
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#define INTMASK_THUNDERLAN 0x8000 /* Enable interrupts */
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/*
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* Structures definition and Functions prototypes
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*/
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/* EPIC's hardware descriptors, must be aligned on dword in memory */
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/* NB: to make driver happy, this two structures MUST have thier sizes */
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/* be divisor of PAGE_SIZE */
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struct epic_tx_desc {
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u_int16_t status;
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u_int16_t txlength;
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@ -244,29 +276,31 @@ struct epic_rx_desc {
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u_int32_t buflength;
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u_int32_t next;
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};
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struct epic_frag_elem { /* frag elem structure for LFFORM=0 */
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u_int32_t fragaddr;
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u_int32_t fraglen;
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};
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/* This structure defines EPIC's fragment list, maximum number of frags */
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/* is 63. Let use maximum, becouse size of struct MUST be divisor of */
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/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */
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struct epic_frag_list {
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u_int32_t numfrags;
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struct epic_frag_elem frag[63];
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struct {
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u_int32_t fragaddr;
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u_int32_t fraglen;
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} frag[63];
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u_int32_t pad; /* align on 256 bytes */
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};
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/* This is driver's structure to define EPIC descriptors */
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struct epic_rx_buffer {
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struct epic_rx_desc desc; /* EPIC's descriptor */
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caddr_t data; /* Rx buffer address */
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#if defined(RX_TO_MBUF)
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struct mbuf * mbuf; /* Or mbuf */
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struct mbuf * mbuf; /* mbuf receiving packet */
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#else
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caddr_t data; /* or static address */
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#endif
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};
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struct epic_tx_buffer {
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struct epic_tx_desc desc; /* EPIC's descriptor */
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#if defined(TX_FRAG_LIST)
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struct mbuf * mbuf; /* mbuf contained packet */
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struct epic_frag_list flist; /* static frag list */
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#else
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caddr_t data; /* Tx buffer address */
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#endif
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@ -282,7 +316,18 @@ typedef struct {
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u_int32_t unit;
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struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
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struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
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/* Each element of array MUST be aligned on dword */
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/* and bounded on PAGE_SIZE */
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struct epic_rx_desc *rx_desc;
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struct epic_tx_desc *tx_desc;
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#if defined(TX_FRAG_LIST)
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struct epic_frag_list *tx_flist;
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#endif
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struct ifmedia ifmedia;
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struct arpcom epic_ac;
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u_int32_t phyid;
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u_int32_t cur_tx;
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u_int32_t cur_rx;
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u_int32_t dirty_tx;
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@ -298,35 +343,38 @@ typedef struct {
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//extern epic_softc_t *epics[];
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//extern u_long epic_pci_count;
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static char* epic_pci_probe(pcici_t, pcidi_t);
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static char* epic_pci_probe __P((pcici_t, pcidi_t));
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/* Folowing functions calls splimp() */
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static int epic_ifioctl(register struct ifnet *, int, caddr_t);
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static void epic_ifstart(struct ifnet *);
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static void epic_ifwatchdog(struct ifnet *);
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static void epic_pci_attach(pcici_t, int);
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static int epic_init(epic_softc_t *);
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static void epic_stop(epic_softc_t *);
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static int epic_ifioctl __P((register struct ifnet *, int, caddr_t));
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static void epic_ifstart __P((struct ifnet *));
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static void epic_ifwatchdog __P((struct ifnet *));
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static void epic_pci_attach __P((pcici_t, int));
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static int epic_init __P((epic_softc_t *));
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static void epic_stop __P((epic_softc_t *));
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static int epic_ifmedia_change __P((struct ifnet *));
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static void epic_ifmedia_status __P((struct ifnet *, struct ifmediareq *));
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/* Following functions doesn't call splimp() */
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static void epic_intr_normal(void *);
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static void epic_rx_done(epic_softc_t *);
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static void epic_tx_done(epic_softc_t *);
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static void epic_intr_normal __P((void *));
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static inline void epic_rx_done __P((epic_softc_t *));
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static inline void epic_tx_done __P((epic_softc_t *));
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static void epic_shutdown __P((int, void *));
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static void epic_update_if_media_flags(epic_softc_t *);
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static int epic_init_rings(epic_softc_t *);
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static void epic_free_rings(epic_softc_t *);
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static void epic_set_rx_mode(epic_softc_t *);
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static void epic_set_mc_table(epic_softc_t *);
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static void epic_set_media_speed(epic_softc_t *);
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static int epic_autoneg(epic_softc_t *);
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static int epic_init_rings __P((epic_softc_t *));
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static void epic_free_rings __P((epic_softc_t *));
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static void epic_set_rx_mode __P((epic_softc_t *));
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static void epic_set_mc_table __P((epic_softc_t *));
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static void epic_set_media_speed __P((epic_softc_t *));
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static int epic_autoneg __P((epic_softc_t *));
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static int epic_read_eeprom(u_int16_t,u_int16_t);
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static void epic_output_eepromw(u_int16_t, u_int16_t);
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static u_int16_t epic_input_eepromw(u_int16_t);
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static u_int8_t epic_eeprom_clock(u_int16_t,u_int8_t);
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static void epic_write_eepromreg(u_int16_t,u_int8_t);
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static u_int8_t epic_read_eepromreg(u_int16_t);
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static int epic_read_eeprom __P((u_int16_t,u_int16_t));
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static void epic_output_eepromw __P((u_int16_t, u_int16_t));
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static u_int16_t epic_input_eepromw __P((u_int16_t));
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static u_int8_t epic_eeprom_clock __P((u_int16_t,u_int8_t));
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static void epic_write_eepromreg __P((u_int16_t,u_int8_t));
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static u_int8_t epic_read_eepromreg __P((u_int16_t));
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static int epic_read_phy_register(u_int16_t, u_int16_t);
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static void epic_write_phy_register(u_int16_t, u_int16_t,u_int16_t);
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static int epic_read_phy_register __P((u_int16_t, u_int16_t));
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static void epic_write_phy_register __P((u_int16_t, u_int16_t,u_int16_t));
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