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Set LCDC clock frequency to 2*148500 KHz

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Minimum LCDC is 2 so clock freq shouild be 2*max_pixel_clock. Maximum pixel
clock for HDMI is 148500 (1920x1080). But AM335x can not run in this mode
due to bandwidth and clock limitations
This commit is contained in:
Oleksandr Tymoshenko 2015-01-29 01:59:42 +00:00
parent f773f195ea
commit f100177dfb
1 changed files with 3 additions and 3 deletions
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6
sys/arm/ti/am335x/am335x_prcm.c
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@ -729,10 +729,10 @@ am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev)
DELAY(10); DELAY(10);
/* /*
* For now set frequency to 5xSYSFREQ * For now set frequency to 99*SYSFREQ/8 which is twice as
* More flexible control might be required * HDMI 1080p pixel clock (minimum LCDC freq divisor is 2)
*/ */
prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (5 << 8) | 0); prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (99 << 8) | 8);
/* Locked mode */ /* Locked mode */
prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7);