Rename arm64 macros in preperation for a script to generate them.
I have a script to generate most of the ID_AA64* macros from the Arm XML source [1]. In preperation for using this we need to clean up the macros to be in line with what the script will generate. This is the first step, rename the macros to follow the names in said XML. [1] https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools MFC after: 1 week Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20976
This commit is contained in:
Andrew Turner
parent
9344e4d738
commit
f1fbf9c3b1
@ -216,7 +216,7 @@ static struct mrs_field id_aa64isar0_fields[] = {
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SM3_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA3_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_RDM_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_ATOMIC_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_Atomic_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_CRC32_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA2_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64ISAR0_SHA1_SHIFT),
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@ -240,7 +240,7 @@ static struct mrs_field id_aa64pfr0_fields[] = {
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_SVE_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_RAS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_GIC_SHIFT),
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MRS_FIELD(true, MRS_LOWER, ID_AA64PFR0_ADV_SIMD_SHIFT),
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MRS_FIELD(true, MRS_LOWER, ID_AA64PFR0_AdvSIMD_SHIFT),
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MRS_FIELD(true, MRS_LOWER, ID_AA64PFR0_FP_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL3_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL2_SHIFT),
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@ -250,13 +250,13 @@ static struct mrs_field id_aa64pfr0_fields[] = {
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};
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static struct mrs_field id_aa64dfr0_fields[] = {
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMS_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_CTX_CMPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_WRPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_BRPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMU_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_TRACE_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT_VAL(0x6), ID_AA64DFR0_DEBUG_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMSVer_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_CTX_CMPs_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_WRPs_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_BRPs_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMUVer_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_TraceVer_SHIFT),
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MRS_FIELD(false, MRS_EXACT_VAL(0x6), ID_AA64DFR0_DebugVer_SHIFT),
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MRS_FIELD_END,
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};
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@ -420,9 +420,9 @@ identify_cpu_sysinit(void *dummy __unused)
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/* Create a user visible cpu description with safe values */
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memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
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/* Safe values for these registers */
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user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_ADV_SIMD_NONE |
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user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE |
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ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | ID_AA64PFR0_EL0_64;
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user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DEBUG_VER_8;
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user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8;
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CPU_FOREACH(cpu) {
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@ -552,10 +552,10 @@ print_cpu_features(u_int cpu)
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sbuf_printf(sb, "%sUnknown RDM", SEP_STR);
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}
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switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) {
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case ID_AA64ISAR0_ATOMIC_NONE:
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switch (ID_AA64ISAR0_Atomic(cpu_desc[cpu].id_aa64isar0)) {
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case ID_AA64ISAR0_Atomic_NONE:
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break;
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case ID_AA64ISAR0_ATOMIC_IMPL:
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case ID_AA64ISAR0_Atomic_IMPL:
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sbuf_printf(sb, "%sAtomic", SEP_STR);
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break;
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default:
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@ -760,13 +760,13 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64PFR0_ADV_SIMD(cpu_desc[cpu].id_aa64pfr0)) {
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case ID_AA64PFR0_ADV_SIMD_NONE:
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switch (ID_AA64PFR0_AdvSIMD(cpu_desc[cpu].id_aa64pfr0)) {
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case ID_AA64PFR0_AdvSIMD_NONE:
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break;
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case ID_AA64PFR0_ADV_SIMD_IMPL:
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case ID_AA64PFR0_AdvSIMD_IMPL:
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sbuf_printf(sb, "%sAdvSIMD", SEP_STR);
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break;
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case ID_AA64PFR0_ADV_SIMD_HP:
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case ID_AA64PFR0_AdvSIMD_HP:
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sbuf_printf(sb, "%sAdvSIMD+HP", SEP_STR);
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break;
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default:
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@ -861,10 +861,10 @@ print_cpu_features(u_int cpu)
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) {
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printed = 0;
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sbuf_printf(sb, " Memory Model Features 0 = <");
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switch (ID_AA64MMFR0_TGRAN4(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGRAN4_NONE:
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switch (ID_AA64MMFR0_TGran4(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGran4_NONE:
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break;
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case ID_AA64MMFR0_TGRAN4_IMPL:
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case ID_AA64MMFR0_TGran4_IMPL:
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sbuf_printf(sb, "%s4k Granule", SEP_STR);
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break;
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default:
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@ -872,10 +872,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGRAN64_NONE:
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switch (ID_AA64MMFR0_TGran64(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGran64_NONE:
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break;
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case ID_AA64MMFR0_TGRAN64_IMPL:
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case ID_AA64MMFR0_TGran64_IMPL:
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sbuf_printf(sb, "%s64k Granule", SEP_STR);
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break;
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default:
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@ -883,10 +883,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGRAN16_NONE:
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switch (ID_AA64MMFR0_TGran16(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_TGran16_NONE:
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break;
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case ID_AA64MMFR0_TGRAN16_IMPL:
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case ID_AA64MMFR0_TGran16_IMPL:
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sbuf_printf(sb, "%s16k Granule", SEP_STR);
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break;
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default:
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@ -894,10 +894,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_BIGEND_EL0(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_BIGEND_EL0_FIXED:
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switch (ID_AA64MMFR0_BigEndEL0(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_BigEndEL0_FIXED:
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break;
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case ID_AA64MMFR0_BIGEND_EL0_MIXED:
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case ID_AA64MMFR0_BigEndEL0_MIXED:
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sbuf_printf(sb, "%sEL0 MixEndian", SEP_STR);
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break;
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default:
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@ -905,10 +905,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_S_NS_MEM(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_S_NS_MEM_NONE:
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switch (ID_AA64MMFR0_SNSMem(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_SNSMem_NONE:
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break;
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case ID_AA64MMFR0_S_NS_MEM_DISTINCT:
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case ID_AA64MMFR0_SNSMem_DISTINCT:
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sbuf_printf(sb, "%sS/NS Mem", SEP_STR);
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break;
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default:
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@ -916,10 +916,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_BIGEND_FIXED:
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switch (ID_AA64MMFR0_BigEnd(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_BigEnd_FIXED:
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break;
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case ID_AA64MMFR0_BIGEND_MIXED:
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case ID_AA64MMFR0_BigEnd_MIXED:
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sbuf_printf(sb, "%sMixedEndian", SEP_STR);
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break;
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default:
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@ -927,11 +927,11 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_ASID_BITS(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_ASID_BITS_8:
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switch (ID_AA64MMFR0_ASIDBits(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_ASIDBits_8:
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sbuf_printf(sb, "%s8bit ASID", SEP_STR);
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break;
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case ID_AA64MMFR0_ASID_BITS_16:
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case ID_AA64MMFR0_ASIDBits_16:
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sbuf_printf(sb, "%s16bit ASID", SEP_STR);
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break;
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default:
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@ -939,26 +939,26 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR0_PA_RANGE(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_PA_RANGE_4G:
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switch (ID_AA64MMFR0_PARange(cpu_desc[cpu].id_aa64mmfr0)) {
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case ID_AA64MMFR0_PARange_4G:
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sbuf_printf(sb, "%s4GB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_64G:
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case ID_AA64MMFR0_PARange_64G:
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sbuf_printf(sb, "%s64GB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_1T:
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case ID_AA64MMFR0_PARange_1T:
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sbuf_printf(sb, "%s1TB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_4T:
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case ID_AA64MMFR0_PARange_4T:
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sbuf_printf(sb, "%s4TB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_16T:
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case ID_AA64MMFR0_PARange_16T:
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sbuf_printf(sb, "%s16TB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_256T:
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case ID_AA64MMFR0_PARange_256T:
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sbuf_printf(sb, "%s256TB PA", SEP_STR);
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break;
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case ID_AA64MMFR0_PA_RANGE_4P:
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case ID_AA64MMFR0_PARange_4P:
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sbuf_printf(sb, "%s4PB PA", SEP_STR);
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break;
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default:
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@ -990,10 +990,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR1_SPEC_SEI(cpu_desc[cpu].id_aa64mmfr1)) {
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case ID_AA64MMFR1_SPEC_SEI_NONE:
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switch (ID_AA64MMFR1_SpecSEI(cpu_desc[cpu].id_aa64mmfr1)) {
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case ID_AA64MMFR1_SpecSEI_NONE:
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break;
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case ID_AA64MMFR1_SPEC_SEI_IMPL:
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case ID_AA64MMFR1_SpecSEI_IMPL:
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sbuf_printf(sb, "%sSpecSEI", SEP_STR);
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break;
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default:
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@ -1051,10 +1051,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR1_VMIDBITS(cpu_desc[cpu].id_aa64mmfr1)) {
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case ID_AA64MMFR1_VMIDBITS_8:
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switch (ID_AA64MMFR1_VMIDBits(cpu_desc[cpu].id_aa64mmfr1)) {
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case ID_AA64MMFR1_VMIDBits_8:
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break;
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case ID_AA64MMFR1_VMIDBITS_16:
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case ID_AA64MMFR1_VMIDBits_16:
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sbuf_printf(sb, "%s16 VMID bits", SEP_STR);
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break;
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default:
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@ -1112,11 +1112,11 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR2_VA_RANGE(cpu_desc[cpu].id_aa64mmfr2)) {
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case ID_AA64MMFR2_VA_RANGE_48:
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switch (ID_AA64MMFR2_VARange(cpu_desc[cpu].id_aa64mmfr2)) {
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case ID_AA64MMFR2_VARange_48:
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sbuf_printf(sb, "%s48b VA", SEP_STR);
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break;
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case ID_AA64MMFR2_VA_RANGE_52:
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case ID_AA64MMFR2_VARange_52:
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sbuf_printf(sb, "%s52b VA", SEP_STR);
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break;
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default:
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@ -1157,10 +1157,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64MMFR2_CNP(cpu_desc[cpu].id_aa64mmfr2)) {
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case ID_AA64MMFR2_CNP_NONE:
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switch (ID_AA64MMFR2_CnP(cpu_desc[cpu].id_aa64mmfr2)) {
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case ID_AA64MMFR2_CnP_NONE:
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break;
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case ID_AA64MMFR2_CNP_IMPL:
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case ID_AA64MMFR2_CnP_IMPL:
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sbuf_printf(sb, "%sCnP", SEP_STR);
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break;
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default:
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@ -1180,10 +1180,10 @@ print_cpu_features(u_int cpu)
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) {
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printed = 0;
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sbuf_printf(sb, " Debug Features 0 = <");
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switch(ID_AA64DFR0_PMS_VER(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_PMS_VER_NONE:
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switch(ID_AA64DFR0_PMSVer(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_PMSVer_NONE:
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break;
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case ID_AA64DFR0_PMS_VER_V1:
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case ID_AA64DFR0_PMSVer_V1:
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sbuf_printf(sb, "%sSPE v1", SEP_STR);
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break;
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default:
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@ -1192,24 +1192,24 @@ print_cpu_features(u_int cpu)
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}
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sbuf_printf(sb, "%s%lu CTX Breakpoints", SEP_STR,
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ID_AA64DFR0_CTX_CMPS(cpu_desc[cpu].id_aa64dfr0));
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ID_AA64DFR0_CTX_CMPs(cpu_desc[cpu].id_aa64dfr0));
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sbuf_printf(sb, "%s%lu Watchpoints", SEP_STR,
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ID_AA64DFR0_WRPS(cpu_desc[cpu].id_aa64dfr0));
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ID_AA64DFR0_WRPs(cpu_desc[cpu].id_aa64dfr0));
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sbuf_printf(sb, "%s%lu Breakpoints", SEP_STR,
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ID_AA64DFR0_BRPS(cpu_desc[cpu].id_aa64dfr0));
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ID_AA64DFR0_BRPs(cpu_desc[cpu].id_aa64dfr0));
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switch (ID_AA64DFR0_PMU_VER(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_PMU_VER_NONE:
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switch (ID_AA64DFR0_PMUVer(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_PMUVer_NONE:
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break;
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case ID_AA64DFR0_PMU_VER_3:
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case ID_AA64DFR0_PMUVer_3:
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sbuf_printf(sb, "%sPMUv3", SEP_STR);
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break;
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case ID_AA64DFR0_PMU_VER_3_1:
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case ID_AA64DFR0_PMUVer_3_1:
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sbuf_printf(sb, "%sPMUv3+16 bit evtCount", SEP_STR);
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break;
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case ID_AA64DFR0_PMU_VER_IMPL:
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case ID_AA64DFR0_PMUVer_IMPL:
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sbuf_printf(sb, "%sImplementation defined PMU", SEP_STR);
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break;
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default:
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@ -1217,10 +1217,10 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64DFR0_TRACE_VER(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_TRACE_VER_NONE:
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switch (ID_AA64DFR0_TraceVer(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_TraceVer_NONE:
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break;
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case ID_AA64DFR0_TRACE_VER_IMPL:
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case ID_AA64DFR0_TraceVer_IMPL:
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sbuf_printf(sb, "%sTrace", SEP_STR);
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break;
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default:
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@ -1228,14 +1228,14 @@ print_cpu_features(u_int cpu)
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break;
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}
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switch (ID_AA64DFR0_DEBUG_VER(cpu_desc[cpu].id_aa64dfr0)) {
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case ID_AA64DFR0_DEBUG_VER_8:
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switch (ID_AA64DFR0_DebugVer(cpu_desc[cpu].id_aa64dfr0)) {
|
||||
case ID_AA64DFR0_DebugVer_8:
|
||||
sbuf_printf(sb, "%sDebug v8", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_DEBUG_VER_8_VHE:
|
||||
case ID_AA64DFR0_DebugVer_8_VHE:
|
||||
sbuf_printf(sb, "%sDebug v8+VHE", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_DEBUG_VER_8_2:
|
||||
case ID_AA64DFR0_DebugVer_8_2:
|
||||
sbuf_printf(sb, "%sDebug v8.2", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -175,41 +175,41 @@
|
||||
|
||||
/* ID_AA64DFR0_EL1 */
|
||||
#define ID_AA64DFR0_MASK 0x0000000ff0f0fffful
|
||||
#define ID_AA64DFR0_DEBUG_VER_SHIFT 0
|
||||
#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
|
||||
#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK)
|
||||
#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
|
||||
#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT)
|
||||
#define ID_AA64DFR0_DEBUG_VER_8_2 (0x8 << ID_AA64DFR0_DEBUG_VER_SHIFT)
|
||||
#define ID_AA64DFR0_TRACE_VER_SHIFT 4
|
||||
#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
|
||||
#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK)
|
||||
#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
|
||||
#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMU_VER_SHIFT 8
|
||||
#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK)
|
||||
#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
|
||||
#define ID_AA64DFR0_BRPS_SHIFT 12
|
||||
#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT)
|
||||
#define ID_AA64DFR0_BRPS(x) \
|
||||
((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_WRPS_SHIFT 20
|
||||
#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT)
|
||||
#define ID_AA64DFR0_WRPS(x) \
|
||||
((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
|
||||
#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
|
||||
#define ID_AA64DFR0_CTX_CMPS(x) \
|
||||
((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_PMS_VER_SHIFT 32
|
||||
#define ID_AA64DFR0_PMS_VER_MASK (0xful << ID_AA64DFR0_PMS_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMS_VER(x) ((x) & ID_AA64DFR0_PMS_VER_MASK)
|
||||
#define ID_AA64DFR0_PMS_VER_NONE (0x0ul << ID_AA64DFR0_PMS_VER_SHIFT)
|
||||
#define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT)
|
||||
#define ID_AA64DFR0_DebugVer_SHIFT 0
|
||||
#define ID_AA64DFR0_DebugVer_MASK (0xf << ID_AA64DFR0_DebugVer_SHIFT)
|
||||
#define ID_AA64DFR0_DebugVer(x) ((x) & ID_AA64DFR0_DebugVer_MASK)
|
||||
#define ID_AA64DFR0_DebugVer_8 (0x6 << ID_AA64DFR0_DebugVer_SHIFT)
|
||||
#define ID_AA64DFR0_DebugVer_8_VHE (0x7 << ID_AA64DFR0_DebugVer_SHIFT)
|
||||
#define ID_AA64DFR0_DebugVer_8_2 (0x8 << ID_AA64DFR0_DebugVer_SHIFT)
|
||||
#define ID_AA64DFR0_TraceVer_SHIFT 4
|
||||
#define ID_AA64DFR0_TraceVer_MASK (0xf << ID_AA64DFR0_TraceVer_SHIFT)
|
||||
#define ID_AA64DFR0_TraceVer(x) ((x) & ID_AA64DFR0_TraceVer_MASK)
|
||||
#define ID_AA64DFR0_TraceVer_NONE (0x0 << ID_AA64DFR0_TraceVer_SHIFT)
|
||||
#define ID_AA64DFR0_TraceVer_IMPL (0x1 << ID_AA64DFR0_TraceVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMUVer_SHIFT 8
|
||||
#define ID_AA64DFR0_PMUVer_MASK (0xf << ID_AA64DFR0_PMUVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMUVer(x) ((x) & ID_AA64DFR0_PMUVer_MASK)
|
||||
#define ID_AA64DFR0_PMUVer_NONE (0x0 << ID_AA64DFR0_PMUVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMUVer_3 (0x1 << ID_AA64DFR0_PMUVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMUVer_3_1 (0x4 << ID_AA64DFR0_PMUVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMUVer_IMPL (0xf << ID_AA64DFR0_PMUVer_SHIFT)
|
||||
#define ID_AA64DFR0_BRPs_SHIFT 12
|
||||
#define ID_AA64DFR0_BRPs_MASK (0xf << ID_AA64DFR0_BRPs_SHIFT)
|
||||
#define ID_AA64DFR0_BRPs(x) \
|
||||
((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_WRPs_SHIFT 20
|
||||
#define ID_AA64DFR0_WRPs_MASK (0xf << ID_AA64DFR0_WRPs_SHIFT)
|
||||
#define ID_AA64DFR0_WRPs(x) \
|
||||
((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_CTX_CMPs_SHIFT 28
|
||||
#define ID_AA64DFR0_CTX_CMPs_MASK (0xf << ID_AA64DFR0_CTX_CMPs_SHIFT)
|
||||
#define ID_AA64DFR0_CTX_CMPs(x) \
|
||||
((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
|
||||
#define ID_AA64DFR0_PMSVer_SHIFT 32
|
||||
#define ID_AA64DFR0_PMSVer_MASK (0xful << ID_AA64DFR0_PMSVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMSVer(x) ((x) & ID_AA64DFR0_PMSVer_MASK)
|
||||
#define ID_AA64DFR0_PMSVer_NONE (0x0ul << ID_AA64DFR0_PMSVer_SHIFT)
|
||||
#define ID_AA64DFR0_PMSVer_V1 (0x1ul << ID_AA64DFR0_PMSVer_SHIFT)
|
||||
|
||||
/* ID_AA64ISAR0_EL1 */
|
||||
#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul
|
||||
@ -235,11 +235,11 @@
|
||||
#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
|
||||
#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT)
|
||||
#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT)
|
||||
#define ID_AA64ISAR0_ATOMIC_SHIFT 20
|
||||
#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT)
|
||||
#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK)
|
||||
#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT)
|
||||
#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT)
|
||||
#define ID_AA64ISAR0_Atomic_SHIFT 20
|
||||
#define ID_AA64ISAR0_Atomic_MASK (0xf << ID_AA64ISAR0_Atomic_SHIFT)
|
||||
#define ID_AA64ISAR0_Atomic(x) ((x) & ID_AA64ISAR0_Atomic_MASK)
|
||||
#define ID_AA64ISAR0_Atomic_NONE (0x0 << ID_AA64ISAR0_Atomic_SHIFT)
|
||||
#define ID_AA64ISAR0_Atomic_IMPL (0x2 << ID_AA64ISAR0_Atomic_SHIFT)
|
||||
#define ID_AA64ISAR0_RDM_SHIFT 28
|
||||
#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT)
|
||||
#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
|
||||
@ -311,51 +311,51 @@
|
||||
|
||||
/* ID_AA64MMFR0_EL1 */
|
||||
#define ID_AA64MMFR0_MASK 0xffffffff
|
||||
#define ID_AA64MMFR0_PA_RANGE_SHIFT 0
|
||||
#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
|
||||
#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_PA_RANGE_4P (0x6 << ID_AA64MMFR0_PA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR0_ASID_BITS_SHIFT 4
|
||||
#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
|
||||
#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK)
|
||||
#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
|
||||
#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND_SHIFT 8
|
||||
#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK)
|
||||
#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
|
||||
#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12
|
||||
#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
|
||||
#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
|
||||
#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
|
||||
#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16
|
||||
#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
|
||||
#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
|
||||
#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN16_SHIFT 20
|
||||
#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK)
|
||||
#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN64_SHIFT 24
|
||||
#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK)
|
||||
#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN4_SHIFT 28
|
||||
#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
|
||||
#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
|
||||
#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_SHIFT 0
|
||||
#define ID_AA64MMFR0_PARange_MASK (0xf << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange(x) ((x) & ID_AA64MMFR0_PARange_MASK)
|
||||
#define ID_AA64MMFR0_PARange_4G (0x0 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_64G (0x1 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_1T (0x2 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_4T (0x3 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_16T (0x4 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_256T (0x5 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_PARange_4P (0x6 << ID_AA64MMFR0_PARange_SHIFT)
|
||||
#define ID_AA64MMFR0_ASIDBits_SHIFT 4
|
||||
#define ID_AA64MMFR0_ASIDBits_MASK (0xf << ID_AA64MMFR0_ASIDBits_SHIFT)
|
||||
#define ID_AA64MMFR0_ASIDBits(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK)
|
||||
#define ID_AA64MMFR0_ASIDBits_8 (0x0 << ID_AA64MMFR0_ASIDBits_SHIFT)
|
||||
#define ID_AA64MMFR0_ASIDBits_16 (0x2 << ID_AA64MMFR0_ASIDBits_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEnd_SHIFT 8
|
||||
#define ID_AA64MMFR0_BigEnd_MASK (0xf << ID_AA64MMFR0_BigEnd_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEnd(x) ((x) & ID_AA64MMFR0_BigEnd_MASK)
|
||||
#define ID_AA64MMFR0_BigEnd_FIXED (0x0 << ID_AA64MMFR0_BigEnd_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEnd_MIXED (0x1 << ID_AA64MMFR0_BigEnd_SHIFT)
|
||||
#define ID_AA64MMFR0_SNSMem_SHIFT 12
|
||||
#define ID_AA64MMFR0_SNSMem_MASK (0xf << ID_AA64MMFR0_SNSMem_SHIFT)
|
||||
#define ID_AA64MMFR0_SNSMem(x) ((x) & ID_AA64MMFR0_SNSMem_MASK)
|
||||
#define ID_AA64MMFR0_SNSMem_NONE (0x0 << ID_AA64MMFR0_SNSMem_SHIFT)
|
||||
#define ID_AA64MMFR0_SNSMem_DISTINCT (0x1 << ID_AA64MMFR0_SNSMem_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEndEL0_SHIFT 16
|
||||
#define ID_AA64MMFR0_BigEndEL0_MASK (0xf << ID_AA64MMFR0_BigEndEL0_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEndEL0(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
|
||||
#define ID_AA64MMFR0_BigEndEL0_FIXED (0x0 << ID_AA64MMFR0_BigEndEL0_SHIFT)
|
||||
#define ID_AA64MMFR0_BigEndEL0_MIXED (0x1 << ID_AA64MMFR0_BigEndEL0_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran16_SHIFT 20
|
||||
#define ID_AA64MMFR0_TGran16_MASK (0xf << ID_AA64MMFR0_TGran16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran16(x) ((x) & ID_AA64MMFR0_TGran16_MASK)
|
||||
#define ID_AA64MMFR0_TGran16_NONE (0x0 << ID_AA64MMFR0_TGran16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran16_IMPL (0x1 << ID_AA64MMFR0_TGran16_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran64_SHIFT 24
|
||||
#define ID_AA64MMFR0_TGran64_MASK (0xf << ID_AA64MMFR0_TGran64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran64(x) ((x) & ID_AA64MMFR0_TGran64_MASK)
|
||||
#define ID_AA64MMFR0_TGran64_IMPL (0x0 << ID_AA64MMFR0_TGran64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran64_NONE (0xf << ID_AA64MMFR0_TGran64_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran4_SHIFT 28
|
||||
#define ID_AA64MMFR0_TGran4_MASK (0xf << ID_AA64MMFR0_TGran4_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran4(x) ((x) & ID_AA64MMFR0_TGran4_MASK)
|
||||
#define ID_AA64MMFR0_TGran4_IMPL (0x0 << ID_AA64MMFR0_TGran4_SHIFT)
|
||||
#define ID_AA64MMFR0_TGran4_NONE (0xf << ID_AA64MMFR0_TGran4_SHIFT)
|
||||
|
||||
/* ID_AA64MMFR1_EL1 */
|
||||
#define ID_AA64MMFR1_MASK 0xffffffff
|
||||
@ -365,11 +365,11 @@
|
||||
#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT)
|
||||
#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT)
|
||||
#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
|
||||
#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK)
|
||||
#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBits_SHIFT 4
|
||||
#define ID_AA64MMFR1_VMIDBits_MASK (0xf << ID_AA64MMFR1_VMIDBits_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBits(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK)
|
||||
#define ID_AA64MMFR1_VMIDBits_8 (0x0 << ID_AA64MMFR1_VMIDBits_SHIFT)
|
||||
#define ID_AA64MMFR1_VMIDBits_16 (0x2 << ID_AA64MMFR1_VMIDBits_SHIFT)
|
||||
#define ID_AA64MMFR1_VH_SHIFT 8
|
||||
#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT)
|
||||
#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK)
|
||||
@ -392,11 +392,11 @@
|
||||
#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT)
|
||||
#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT)
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#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT)
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#define ID_AA64MMFR1_SPEC_SEI_SHIFT 24
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#define ID_AA64MMFR1_SPEC_SEI_MASK (0xf << ID_AA64MMFR1_SPEC_SEI_SHIFT)
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#define ID_AA64MMFR1_SPEC_SEI(x) ((x) & ID_AA64MMFR1_SPEC_SEI_MASK)
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#define ID_AA64MMFR1_SPEC_SEI_NONE (0x0 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
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#define ID_AA64MMFR1_SPEC_SEI_IMPL (0x1 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
|
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#define ID_AA64MMFR1_SpecSEI_SHIFT 24
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#define ID_AA64MMFR1_SpecSEI_MASK (0xf << ID_AA64MMFR1_SpecSEI_SHIFT)
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#define ID_AA64MMFR1_SpecSEI(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK)
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||||
#define ID_AA64MMFR1_SpecSEI_NONE (0x0 << ID_AA64MMFR1_SpecSEI_SHIFT)
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#define ID_AA64MMFR1_SpecSEI_IMPL (0x1 << ID_AA64MMFR1_SpecSEI_SHIFT)
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#define ID_AA64MMFR1_XNX_SHIFT 28
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#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT)
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#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
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@ -406,11 +406,11 @@
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/* ID_AA64MMFR2_EL1 */
|
||||
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
|
||||
#define ID_AA64MMFR2_MASK 0x0fffffff
|
||||
#define ID_AA64MMFR2_CNP_SHIFT 0
|
||||
#define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT)
|
||||
#define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK)
|
||||
#define ID_AA64MMFR2_CNP_NONE (0x0 << ID_AA64MMFR2_CNP_SHIFT)
|
||||
#define ID_AA64MMFR2_CNP_IMPL (0x1 << ID_AA64MMFR2_CNP_SHIFT)
|
||||
#define ID_AA64MMFR2_CnP_SHIFT 0
|
||||
#define ID_AA64MMFR2_CnP_MASK (0xf << ID_AA64MMFR2_CnP_SHIFT)
|
||||
#define ID_AA64MMFR2_CnP(x) ((x) & ID_AA64MMFR2_CnP_MASK)
|
||||
#define ID_AA64MMFR2_CnP_NONE (0x0 << ID_AA64MMFR2_CnP_SHIFT)
|
||||
#define ID_AA64MMFR2_CnP_IMPL (0x1 << ID_AA64MMFR2_CnP_SHIFT)
|
||||
#define ID_AA64MMFR2_UAO_SHIFT 4
|
||||
#define ID_AA64MMFR2_UAO_MASK (0xf << ID_AA64MMFR2_UAO_SHIFT)
|
||||
#define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK)
|
||||
@ -426,11 +426,11 @@
|
||||
#define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK)
|
||||
#define ID_AA64MMFR2_IESB_NONE (0x0 << ID_AA64MMFR2_IESB_SHIFT)
|
||||
#define ID_AA64MMFR2_IESB_IMPL (0x1 << ID_AA64MMFR2_IESB_SHIFT)
|
||||
#define ID_AA64MMFR2_VA_RANGE_SHIFT 16
|
||||
#define ID_AA64MMFR2_VA_RANGE_MASK (0xf << ID_AA64MMFR2_VA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK)
|
||||
#define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT)
|
||||
#define ID_AA64MMFR2_VARange_SHIFT 16
|
||||
#define ID_AA64MMFR2_VARange_MASK (0xf << ID_AA64MMFR2_VARange_SHIFT)
|
||||
#define ID_AA64MMFR2_VARange(x) ((x) & ID_AA64MMFR2_VARange_MASK)
|
||||
#define ID_AA64MMFR2_VARange_48 (0x0 << ID_AA64MMFR2_VARange_SHIFT)
|
||||
#define ID_AA64MMFR2_VARange_52 (0x1 << ID_AA64MMFR2_VARange_SHIFT)
|
||||
#define ID_AA64MMFR2_CCIDX_SHIFT 20
|
||||
#define ID_AA64MMFR2_CCIDX_MASK (0xf << ID_AA64MMFR2_CCIDX_SHIFT)
|
||||
#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
|
||||
@ -472,12 +472,12 @@
|
||||
#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT)
|
||||
#define ID_AA64PFR0_FP_HP (0x1 << ID_AA64PFR0_FP_SHIFT)
|
||||
#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT)
|
||||
#define ID_AA64PFR0_ADV_SIMD_SHIFT 20
|
||||
#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
|
||||
#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
|
||||
#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
|
||||
#define ID_AA64PFR0_ADV_SIMD_HP (0x1 << ID_AA64PFR0_ADV_SIMD_SHIFT)
|
||||
#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
|
||||
#define ID_AA64PFR0_AdvSIMD_SHIFT 20
|
||||
#define ID_AA64PFR0_AdvSIMD_MASK (0xf << ID_AA64PFR0_AdvSIMD_SHIFT)
|
||||
#define ID_AA64PFR0_AdvSIMD(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK)
|
||||
#define ID_AA64PFR0_AdvSIMD_IMPL (0x0 << ID_AA64PFR0_AdvSIMD_SHIFT)
|
||||
#define ID_AA64PFR0_AdvSIMD_HP (0x1 << ID_AA64PFR0_AdvSIMD_SHIFT)
|
||||
#define ID_AA64PFR0_AdvSIMD_NONE (0xf << ID_AA64PFR0_AdvSIMD_SHIFT)
|
||||
#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
|
||||
#define ID_AA64PFR0_GIC_SHIFT 24
|
||||
#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user