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For the SMP case, flush the TLB at the beginning of the page zero/copy

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routines.  Otherwise we run into trouble with speculative tlb preloads
on SMP systems.  This effectively defeats Jeff's revision 1.438
optimization (for his pentium4-M laptop) in the SMP case.  It breaks
other systems, particularly athlon-MP's.
This commit is contained in:
Peter Wemm 2003-10-25 18:51:41 +00:00
parent 93dbd07122
commit f3075be88a
1 changed files with 13 additions and 0 deletions
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13
sys/i386/i386/pmap.c
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@ -2389,6 +2389,9 @@ pmap_zero_page(vm_page_t m)
curthread->td_pcb->pcb_switchout = pmap_zpi_switchout2;
#endif
*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
#ifdef SMP
invlpg((u_int)CADDR2);
#endif
pagezero(CADDR2);
*CMAP2 = 0;
invlcaddr(CADDR2);
@ -2415,6 +2418,9 @@ pmap_zero_page_area(vm_page_t m, int off, int size)
curthread->td_pcb->pcb_switchout = pmap_zpi_switchout2;
#endif
*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
#ifdef SMP
invlpg((u_int)CADDR2);
#endif
if (off == 0 && size == PAGE_SIZE)
pagezero(CADDR2);
else
@ -2443,6 +2449,9 @@ pmap_zero_page_idle(vm_page_t m)
curthread->td_pcb->pcb_switchout = pmap_zpi_switchout3;
#endif
*CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
#ifdef SMP
invlpg((u_int)CADDR3);
#endif
pagezero(CADDR3);
*CMAP3 = 0;
invlcaddr(CADDR3);
@ -2471,6 +2480,10 @@ pmap_copy_page(vm_page_t src, vm_page_t dst)
#endif
*CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A;
*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M;
#ifdef SMP
invlpg((u_int)CADDR1);
invlpg((u_int)CADDR2);
#endif
bcopy(CADDR1, CADDR2, PAGE_SIZE);
*CMAP1 = 0;
*CMAP2 = 0;