[rt305x] add PCI bus / resource allocation code for the MT7620.
This is based on the sys/arm/mv/ pci resource/allocation code. Submitted by: Stanislav Galabov <galabov@gmail.com>
This commit is contained in:
Adrian Chadd
parent
c40db2e376
commit
f3213f44b2
955
sys/mips/rt305x/rt305x_pci.c
Normal file
955
sys/mips/rt305x/rt305x_pci.c
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@ -0,0 +1,955 @@
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/*-
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* Copyright (c) 2015 Stanislav Galabov.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This is based on the pci allocator code from sys/dev/arm/mv/:
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*
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* Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
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* Copyright (c) 2010 The FreeBSD Foundation
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* Copyright (c) 2010-2012 Semihalf
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* All rights reserved.
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*
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* Developed by Semihalf.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/endian.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr_machdep.h>
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#include <machine/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <mips/rt305x/rt305xreg.h>
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#include <mips/rt305x/rt305x_pcireg.h>
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#include <mips/rt305x/rt305x_sysctlvar.h>
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struct mtx rt305x_pci_mtx;
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MTX_SYSINIT(rt305x_pci_mtx, &rt305x_pci_mtx, "rt305x PCI/PCIe mutex", MTX_SPIN);
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struct rt305x_pci_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_busno;
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struct rman sc_mem_rman;
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struct rman sc_io_rman;
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struct rman sc_irq_rman;
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bus_addr_t sc_mem_base;
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bus_addr_t sc_mem_size;
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uint32_t sc_mem_map[(256*1024*1024) /
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(PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
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bus_addr_t sc_io_base;
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bus_addr_t sc_io_size;
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uint32_t sc_io_map[(16*1024*1024) /
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(PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
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struct intr_event *sc_eventstab[RT305X_PCI_NIRQS];
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mips_intrcnt_t sc_intr_counter[RT305X_PCI_NIRQS];
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int pcie_link_status;
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};
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static void rt305x_pci_phy_init(device_t);
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static void rt305x_pci_init(device_t);
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static int rt305x_pcib_init(device_t, int, int);
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static int rt305x_pci_intr(void *);
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static void rt305x_pci_dump_regs(device_t);
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static struct rt305x_pci_softc *rt_sc = NULL;
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static int
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rt305x_pci_probe(device_t dev)
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{
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return (BUS_PROBE_NOWILDCARD);
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}
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static int
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rt305x_pci_attach(device_t dev)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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rt_sc = sc;
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sc->sc_dev = dev;
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sc->sc_mem_base = PCIE_MEM_BASE;
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sc->sc_mem_size = 0x10000000;
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sc->sc_io_base = PCIE_IO_BASE;
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sc->sc_io_size = 0x10000;
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sc->sc_bsh = MIPS_PHYS_TO_KSEG1(PCIE_BASE);
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sc->sc_bst = mips_bus_space_generic;
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "rt305x pci memory window";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
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sc->sc_mem_base + sc->sc_mem_size - 1) != 0) {
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panic("%s: failed to set up memory rman", __FUNCTION__);
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}
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sc->sc_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_io_rman.rm_descr = "rt305x pci io window";
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if (rman_init(&sc->sc_io_rman) != 0 ||
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rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
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sc->sc_io_base + sc->sc_io_size - 1) != 0) {
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panic("%s: failed to set up io rman", __FUNCTION__);
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "rt305x pci irqs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, RT305X_PCIE0_IRQ,
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RT305X_PCIE0_IRQ) != 0) {
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panic("%s: failed to set up irq rman", __FUNCTION__);
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}
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cpu_establish_hardintr("pci", rt305x_pci_intr, NULL, sc,
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RT305X_PCI_INTR_PIN, INTR_TYPE_MISC | INTR_EXCL, NULL);
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rt305x_pci_phy_init(dev);
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rt305x_pci_init(dev);
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rt305x_pci_dump_regs(dev);
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rt305x_pcib_init(dev, 0, PCI_SLOTMAX);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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rt305x_pci_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = device_get_unit(dev);
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_busno;
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return (0);
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}
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return (ENOENT);
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}
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static int
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rt305x_pci_write_ivar(device_t dev, device_t child, int which,
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uintptr_t result)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->sc_busno = result;
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return (0);
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}
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return (ENOENT);
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}
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static struct resource *
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rt305x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct rt305x_pci_softc *sc = device_get_softc(bus);
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struct resource *rv;
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struct rman *rm;
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vm_offset_t va;
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switch (type) {
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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case SYS_RES_IOPORT:
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rm = &sc->sc_io_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_mem_rman;
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break;
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default:
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return (NULL);
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}
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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if (type != SYS_RES_IRQ) {
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if (type == SYS_RES_MEMORY) {
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va = (vm_offset_t)pmap_mapdev(start, count);
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} else if (type == SYS_RES_IOPORT){
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va = (vm_offset_t)MIPS_PHYS_TO_KSEG1(start);
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}
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rman_set_bushandle(rv, va);
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rman_set_virtual(rv, (void *)va);
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rman_set_bustag(rv, mips_bus_space_generic);
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}
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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rman_release_resource(rv);
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return (NULL);
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}
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}
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return (rv);
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}
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static int
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rt305x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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return rman_activate_resource(r);
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}
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static inline int
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rt305x_idx_to_irq(int idx)
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{
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return ((idx == 0) ? RT305X_PCIE0_IRQ :
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(idx == 1) ? RT305X_PCIE1_IRQ :
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(idx == 2) ? RT305X_PCIE2_IRQ : -1);
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}
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static inline int
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rt305x_irq_to_idx(int irq)
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{
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return ((irq == RT305X_PCIE0_IRQ) ? 0 :
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(irq == RT305X_PCIE1_IRQ) ? 1 :
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(irq == RT305X_PCIE2_IRQ) ? 2 : -1);
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}
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static void
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rt305x_pci_mask_irq(void *source)
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{
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RT_WRITE32(rt_sc, RT305X_PCI_PCIENA,
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RT_READ32(rt_sc, RT305X_PCI_PCIENA) & ~(1<<((int)source)));
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}
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static void
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rt305x_pci_unmask_irq(void *source)
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{
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RT_WRITE32(rt_sc, RT305X_PCI_PCIENA,
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RT_READ32(rt_sc, RT305X_PCI_PCIENA) | (1<<((int)source)));
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}
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static int
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rt305x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *handler,
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void *arg, void **cookiep)
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{
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struct rt305x_pci_softc *sc = device_get_softc(bus);
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struct intr_event *event;
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int irq, error, irqidx;
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irq = rman_get_start(ires);
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if ((irqidx = rt305x_irq_to_idx(irq)) == -1)
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panic("%s: bad irq %d", __FUNCTION__, irq);
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event = sc->sc_eventstab[irqidx];
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if (event == NULL) {
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error = intr_event_create(&event, (void *)irq, 0, irq,
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rt305x_pci_mask_irq, rt305x_pci_unmask_irq, NULL, NULL,
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"pci intr%d:", irq);
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if (error == 0) {
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sc->sc_eventstab[irqidx] = event;
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sc->sc_intr_counter[irqidx] =
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mips_intrcnt_create(event->ie_name);
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}
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else
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return (error);
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}
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intr_event_add_handler(event, device_get_nameunit(child), filt,
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handler, arg, intr_priority(flags), flags, cookiep);
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mips_intrcnt_setname(sc->sc_intr_counter[irqidx], event->ie_fullname);
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rt305x_pci_unmask_irq((void*)irq);
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return (0);
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}
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static int
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rt305x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
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void *cookie)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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int irq, result, irqidx;
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irq = rman_get_start(ires);
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if ((irqidx = rt305x_irq_to_idx(irq)) == -1)
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panic("%s: bad irq %d", __FUNCTION__, irq);
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if (sc->sc_eventstab[irqidx] == NULL)
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panic("Trying to teardown unoccupied IRQ");
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rt305x_pci_mask_irq((void*)irq);
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result = intr_event_remove_handler(cookie);
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if (!result)
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sc->sc_eventstab[irqidx] = NULL;
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return (result);
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}
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static inline uint32_t
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rt305x_pci_make_addr(int bus, int slot, int func, int reg)
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{
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uint32_t addr;
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addr = (((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
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(func << 8) | (reg & 0xfc) | (1 << 31);
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return (addr);
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}
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static int
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rt305x_pci_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static uint32_t
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rt305x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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uint32_t addr = 0, data = 0;
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if (bus == 0 && (sc->pcie_link_status & (1<<slot)) == 0)
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return (~0U);
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mtx_lock_spin(&rt305x_pci_mtx);
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addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
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RT_WRITE32(sc, RT305X_PCI_CFGADDR, addr);
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switch (bytes % 4) {
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case 0:
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data = RT_READ32(sc, RT305X_PCI_CFGDATA);
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break;
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case 1:
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data = RT_READ8(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
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break;
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case 2:
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data = RT_READ16(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
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break;
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default:
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panic("%s(): Wrong number of bytes (%d) requested!\n",
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__FUNCTION__, bytes % 4);
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}
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mtx_unlock_spin(&rt305x_pci_mtx);
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return (data);
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}
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static void
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rt305x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t val, int bytes)
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{
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struct rt305x_pci_softc *sc = device_get_softc(dev);
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uint32_t addr = 0, data = val;
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if (bus == 0 && (sc->pcie_link_status & (1<<slot)) == 0)
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return;
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mtx_lock_spin(&rt305x_pci_mtx);
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addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
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RT_WRITE32(sc, RT305X_PCI_CFGADDR, addr);
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switch (bytes % 4) {
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case 0:
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RT_WRITE32(sc, RT305X_PCI_CFGDATA, data);
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break;
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case 1:
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RT_WRITE8(sc, RT305X_PCI_CFGDATA + (reg & 0x3), data);
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break;
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case 2:
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RT_WRITE16(sc, RT305X_PCI_CFGDATA + (reg & 0x3), data);
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break;
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default:
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panic("%s(): Wrong number of bytes (%d) requested!\n",
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__FUNCTION__, bytes % 4);
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}
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mtx_unlock_spin(&rt305x_pci_mtx);
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}
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static int
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rt305x_pci_route_interrupt(device_t pcib, device_t device, int pin)
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{
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//struct rt305x_pci_softc *sc = device_get_softc(pcib);
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int bus, sl;
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bus = pci_get_bus(device);
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sl = pci_get_slot(device);
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if (bus != 0)
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panic("Unexpected bus number %d\n", bus);
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//printf("%s: not done yet.\n", __FUNCTION__);
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switch (sl) {
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case 0: return RT305X_PCIE0_IRQ;
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default: return (-1);
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}
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return (-1);
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}
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static device_method_t rt305x_pci_methods[] = {
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/* Device interface */
|
||||
DEVMETHOD(device_probe, rt305x_pci_probe),
|
||||
DEVMETHOD(device_attach, rt305x_pci_attach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD(device_suspend, bus_generic_suspend),
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, rt305x_pci_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, rt305x_pci_write_ivar),
|
||||
DEVMETHOD(bus_alloc_resource, rt305x_pci_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, rt305x_pci_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
||||
DEVMETHOD(bus_setup_intr, rt305x_pci_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, rt305x_pci_teardown_intr),
|
||||
|
||||
/* pcib interface */
|
||||
DEVMETHOD(pcib_maxslots, rt305x_pci_maxslots),
|
||||
DEVMETHOD(pcib_read_config, rt305x_pci_read_config),
|
||||
DEVMETHOD(pcib_write_config, rt305x_pci_write_config),
|
||||
DEVMETHOD(pcib_route_interrupt, rt305x_pci_route_interrupt),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t rt305x_pci_driver = {
|
||||
"pcib",
|
||||
rt305x_pci_methods,
|
||||
sizeof(struct rt305x_pci_softc),
|
||||
};
|
||||
|
||||
static devclass_t rt305x_pci_devclass;
|
||||
|
||||
DRIVER_MODULE(rt305x_pci, nexus, rt305x_pci_driver, rt305x_pci_devclass, 0, 0);
|
||||
|
||||
static void
|
||||
rt305x_pci_dump_regs(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
uint32_t reg = 0;
|
||||
|
||||
reg = 0x0000;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x0008;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x000c;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x0020;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x0024;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x0028;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x002c;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2010;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2014;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2018;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2030;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2034;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2038;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2050;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2060;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
|
||||
reg = 0x2064;
|
||||
printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
rt305x_pci_init(device_t dev)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
uint32_t tmp;
|
||||
|
||||
rt305x_sysctl_set(SYSCTL_SYSCFG1,
|
||||
rt305x_sysctl_get(SYSCTL_SYSCFG1) | (1 << 8));
|
||||
|
||||
rt305x_sysctl_set(SYSCTL_GPIOMODE,
|
||||
rt305x_sysctl_get(SYSCTL_GPIOMODE) & ~(0x3 << 16));
|
||||
rt305x_sysctl_set(SYSCTL_RSTCTRL,
|
||||
rt305x_sysctl_get(SYSCTL_RSTCTRL) & ~(1<<26));
|
||||
rt305x_sysctl_set(SYSCTL_CLKCFG1,
|
||||
rt305x_sysctl_get(SYSCTL_CLKCFG1) | (1<<26));
|
||||
|
||||
tmp = rt305x_sysctl_get(SYSCTL_PPLL_CFG1);
|
||||
if ((tmp & (1<<23)) == 0) {
|
||||
device_printf(dev, "PPLL not locked\n");
|
||||
return;
|
||||
}
|
||||
|
||||
tmp = rt305x_sysctl_get(SYSCTL_PPLL_DRV);
|
||||
tmp |= (1<<19);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
|
||||
tmp &= ~(1<<18);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
|
||||
tmp &= ~(1<<17);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
|
||||
tmp|= (1<<31);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
|
||||
|
||||
RT_WRITE32(sc, RT305X_PCI_MEMBASE, sc->sc_mem_base);
|
||||
RT_WRITE32(sc, RT305X_PCI_IOBASE, sc->sc_io_base);
|
||||
|
||||
RT_WRITE32(sc, RT305X_PCI_PCICFG, RT_READ32(sc, 0) & ~(1<<1));
|
||||
DELAY(500000);
|
||||
if ((RT_READ32(sc, RT305X_PCI_PCIE0_STATUS) & 0x1) == 1)
|
||||
sc->pcie_link_status = 1;
|
||||
else
|
||||
sc->pcie_link_status = 0;
|
||||
|
||||
RT_WRITE32(sc, RT305X_PCI_PCIE0_BAR0SETUP, 0x7FFF0001);
|
||||
RT_WRITE32(sc, RT305X_PCI_PCIE0_BAR1SETUP, 0x00000000);
|
||||
RT_WRITE32(sc, RT305X_PCI_PCIE0_IMBASEBAR0, 0x00000000);
|
||||
RT_WRITE32(sc, RT305X_PCI_PCIE0_CLASS, 0x06040001);
|
||||
|
||||
tmp = rt305x_pci_read_config(dev, 0, 0, 0, 4, 4);
|
||||
rt305x_pci_write_config(dev, 0, 0, 0, 4, tmp | 0x7, 4);
|
||||
tmp = rt305x_pci_read_config(dev, 0, 0, 0, 0x70c, 4);
|
||||
tmp &= ~(0xff)<<8;
|
||||
tmp |= 0x50<<8;
|
||||
rt305x_pci_write_config(dev, 0, 0, 0, 0x70c, tmp, 4);
|
||||
tmp = rt305x_pci_read_config(dev, 0, 0, 0, 0x70c, 4);
|
||||
|
||||
rt305x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), 0, 4);
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
pcib_bit_get(uint32_t *map, uint32_t bit)
|
||||
{
|
||||
uint32_t n = bit / BITS_PER_UINT32;
|
||||
|
||||
bit = bit % BITS_PER_UINT32;
|
||||
return (map[n] & (1 << bit));
|
||||
}
|
||||
|
||||
static inline void
|
||||
pcib_bit_set(uint32_t *map, uint32_t bit)
|
||||
{
|
||||
uint32_t n = bit / BITS_PER_UINT32;
|
||||
|
||||
bit = bit % BITS_PER_UINT32;
|
||||
map[n] |= (1 << bit);
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = start; i < start + bits; i++)
|
||||
if (pcib_bit_get(map, i))
|
||||
return (0);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = start; i < start + bits; i++)
|
||||
pcib_bit_set(map, i);
|
||||
}
|
||||
|
||||
static bus_addr_t
|
||||
pcib_alloc(device_t dev, uint32_t smask)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
uint32_t bits, bits_limit, i, *map, min_alloc, size;
|
||||
bus_addr_t addr = 0;
|
||||
bus_addr_t base;
|
||||
|
||||
if (smask & 1) {
|
||||
base = sc->sc_io_base;
|
||||
min_alloc = PCI_MIN_IO_ALLOC;
|
||||
bits_limit = sc->sc_io_size / min_alloc;
|
||||
map = sc->sc_io_map;
|
||||
smask &= ~0x3;
|
||||
} else {
|
||||
base = sc->sc_mem_base;
|
||||
min_alloc = PCI_MIN_MEM_ALLOC;
|
||||
bits_limit = sc->sc_mem_size / min_alloc;
|
||||
map = sc->sc_mem_map;
|
||||
smask &= ~0xF;
|
||||
}
|
||||
|
||||
size = ~smask + 1;
|
||||
bits = size / min_alloc;
|
||||
|
||||
for (i = 0; i + bits <= bits_limit; i+= bits)
|
||||
if (pcib_map_check(map, i, bits)) {
|
||||
pcib_map_set(map, i, bits);
|
||||
addr = base + (i * min_alloc);
|
||||
return (addr);
|
||||
}
|
||||
|
||||
return (addr);
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_pcib_init_bar(device_t dev, int bus, int slot, int func, int barno)
|
||||
{
|
||||
uint32_t addr, bar;
|
||||
int reg, width;
|
||||
|
||||
reg = PCIR_BAR(barno);
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func, reg, ~0, 4);
|
||||
bar = rt305x_pci_read_config(dev, bus, slot, func, reg, 4);
|
||||
if (bar == 0)
|
||||
return (1);
|
||||
|
||||
/* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
|
||||
width = ((bar & 7) == 4) ? 2 : 1;
|
||||
|
||||
addr = pcib_alloc(dev, bar);
|
||||
if (!addr)
|
||||
return (-1);
|
||||
|
||||
if (bootverbose)
|
||||
printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
|
||||
bus, slot, func, reg, bar, addr);
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func, reg, addr, 4);
|
||||
if (width == 2)
|
||||
rt305x_pci_write_config(dev, bus, slot, func, reg + 4, 0, 4);
|
||||
|
||||
return (width);
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_pcib_init_all_bars(device_t dev, int bus, int slot, int func,
|
||||
int hdrtype)
|
||||
{
|
||||
int maxbar, bar, i;
|
||||
|
||||
maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
|
||||
bar = 0;
|
||||
|
||||
while (bar < maxbar) {
|
||||
i = rt305x_pcib_init_bar(dev, bus, slot, func, bar);
|
||||
bar += i;
|
||||
if (i < 0) {
|
||||
device_printf(dev, "PCI IO/Memory space exhausted\n");
|
||||
return (ENOMEM);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static inline int
|
||||
rt305x_pci_slot_has_link(device_t dev, int slot)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
return !!(sc->pcie_link_status & (1<<slot));
|
||||
}
|
||||
|
||||
static int cur_secbus = 0;
|
||||
|
||||
static void
|
||||
rt305x_pcib_init_bridge(device_t dev, int bus, int slot, int func)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
bus_addr_t io_base, mem_base;
|
||||
uint32_t io_limit, mem_limit;
|
||||
int secbus;
|
||||
|
||||
if (bus == 0 && !rt305x_pci_slot_has_link(dev, slot)) {
|
||||
device_printf(dev, "Skip bus %d due to no link\n",++cur_secbus);
|
||||
return;
|
||||
}
|
||||
|
||||
io_base = sc->sc_io_base;
|
||||
io_limit = io_base + sc->sc_io_size - 1;
|
||||
mem_base = sc->sc_mem_base;
|
||||
mem_limit = mem_base + sc->sc_mem_size - 1;
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOBASEL_1,
|
||||
io_base >> 8, 1);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOBASEH_1,
|
||||
io_base >> 16, 2);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITL_1,
|
||||
io_limit >> 8, 1);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITH_1,
|
||||
io_limit >> 16, 2);
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_MEMBASE_1,
|
||||
mem_base >> 16, 2);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_MEMLIMIT_1,
|
||||
mem_limit >> 16, 2);
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMBASEL_1,
|
||||
0x10, 2);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMBASEH_1,
|
||||
0x0, 4);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITL_1,
|
||||
0xF, 2);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITH_1,
|
||||
0x0, 4);
|
||||
|
||||
secbus = rt305x_pci_read_config(dev, bus, slot, func, PCIR_SECBUS_1, 1);
|
||||
|
||||
if (secbus == 0) {
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_SECBUS_1,
|
||||
++cur_secbus, 1);
|
||||
rt305x_pci_write_config(dev, bus, slot, func, PCIR_SUBBUS_1,
|
||||
cur_secbus, 1);
|
||||
secbus = cur_secbus;
|
||||
}
|
||||
|
||||
rt305x_pcib_init(dev, secbus, PCI_SLOTMAX);
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_pcib_init(device_t dev, int bus, int maxslot)
|
||||
{
|
||||
int slot, func, maxfunc, error;
|
||||
uint8_t hdrtype, command, class, subclass;
|
||||
|
||||
for (slot = 0; slot <= maxslot; slot++) {
|
||||
maxfunc = 0;
|
||||
for (func = 0; func <= maxfunc; func++) {
|
||||
hdrtype = rt305x_pci_read_config(dev, bus, slot, func,
|
||||
PCIR_HDRTYPE, 1);
|
||||
|
||||
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
|
||||
continue;
|
||||
|
||||
if (func == 0 && (hdrtype & PCIM_MFDEV))
|
||||
maxfunc = PCI_FUNCMAX;
|
||||
|
||||
command = rt305x_pci_read_config(dev, bus, slot, func,
|
||||
PCIR_COMMAND, 1);
|
||||
command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
|
||||
rt305x_pci_write_config(dev, bus, slot, func,
|
||||
PCIR_COMMAND, command, 1);
|
||||
|
||||
error = rt305x_pcib_init_all_bars(dev, bus, slot, func,
|
||||
hdrtype);
|
||||
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
|
||||
PCIM_CMD_PORTEN;
|
||||
rt305x_pci_write_config(dev, bus, slot, func,
|
||||
PCIR_COMMAND, command, 1);
|
||||
|
||||
rt305x_pci_write_config(dev, bus, slot, func,
|
||||
PCIR_CACHELNSZ, 16, 1);
|
||||
|
||||
class = rt305x_pci_read_config(dev, bus, slot, func,
|
||||
PCIR_CLASS, 1);
|
||||
subclass = rt305x_pci_read_config(dev, bus, slot, func,
|
||||
PCIR_SUBCLASS, 1);
|
||||
|
||||
if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_PCI)
|
||||
continue;
|
||||
|
||||
rt305x_pcib_init_bridge(dev, bus, slot, func);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#define BUSY 0x80000000
|
||||
#define WAITRETRY_MAX 10
|
||||
#define WRITE_MODE (1<<23)
|
||||
#define DATA_SHIFT 0
|
||||
#define ADDR_SHIFT 8
|
||||
|
||||
static int
|
||||
rt305x_wait_pci_phy_busy(struct rt305x_pci_softc *sc)
|
||||
{
|
||||
uint32_t reg_value = 0x0, retry = 0;
|
||||
|
||||
while (1) {
|
||||
reg_value = RT_READ32(sc, RT305X_PCI_PHY0_CFG);
|
||||
if (reg_value & BUSY)
|
||||
DELAY(100000);
|
||||
else
|
||||
break;
|
||||
if (retry++ > WAITRETRY_MAX) {
|
||||
printf("PHY retry failed\n");
|
||||
return (-1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
rt305x_pci_phy(struct rt305x_pci_softc *sc, char rwmode, uint32_t addr,
|
||||
uint32_t val)
|
||||
{
|
||||
uint32_t reg_value = 0x0;
|
||||
|
||||
rt305x_wait_pci_phy_busy(sc);
|
||||
if (rwmode == 'w') {
|
||||
reg_value |= WRITE_MODE;
|
||||
reg_value |= (val) << DATA_SHIFT;
|
||||
}
|
||||
reg_value |= (addr) << ADDR_SHIFT;
|
||||
|
||||
RT_WRITE32(sc, RT305X_PCI_PHY0_CFG, reg_value);
|
||||
DELAY(1000);
|
||||
|
||||
rt305x_wait_pci_phy_busy(sc);
|
||||
|
||||
if (rwmode == 'r') {
|
||||
reg_value = RT_READ32(sc, RT305X_PCI_PHY0_CFG);
|
||||
return (reg_value);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
rt305x_pci_phy_init(device_t dev)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = device_get_softc(dev);
|
||||
uint32_t tmp;
|
||||
|
||||
rt305x_pci_phy(sc, 'w', 0x00, 0x80);
|
||||
rt305x_pci_phy(sc, 'w', 0x01, 0x04);
|
||||
rt305x_pci_phy(sc, 'w', 0x68, 0x84);
|
||||
|
||||
rt305x_sysctl_set(SYSCTL_RSTCTRL,
|
||||
rt305x_sysctl_get(SYSCTL_RSTCTRL) | (1<<26));
|
||||
rt305x_sysctl_set(SYSCTL_CLKCFG1,
|
||||
rt305x_sysctl_get(SYSCTL_CLKCFG1) & ~(1<<26));
|
||||
|
||||
tmp = rt305x_sysctl_get(SYSCTL_PPLL_CFG1);
|
||||
tmp &= ~(1<<19);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_CFG1, tmp);
|
||||
tmp |= (1<<31);
|
||||
rt305x_sysctl_set(SYSCTL_PPLL_CFG1, tmp);
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_pci_intr(void *arg)
|
||||
{
|
||||
struct rt305x_pci_softc *sc = arg;
|
||||
struct intr_event *event;
|
||||
uint32_t reg, irq, irqidx;
|
||||
|
||||
reg = RT_READ32(sc, RT305X_PCI_PCIINT);
|
||||
|
||||
for (irqidx = 0; irqidx < RT305X_PCI_NIRQS; irqidx++) {
|
||||
irq = rt305x_idx_to_irq(irqidx);
|
||||
if (reg & (1<<irq)) {
|
||||
event = sc->sc_eventstab[irqidx];
|
||||
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
|
||||
if (irq != 0)
|
||||
printf("Stray PCI IRQ %d\n", irq);
|
||||
continue;
|
||||
}
|
||||
|
||||
intr_event_handle(event, NULL);
|
||||
mips_intrcnt_inc(sc->sc_intr_counter[irqidx]);
|
||||
}
|
||||
}
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
76
sys/mips/rt305x/rt305x_pcireg.h
Normal file
76
sys/mips/rt305x/rt305x_pcireg.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*-
|
||||
* Copyright (c) 2015 Stanislav Galabov.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef __RT305X_PCIREG_H__
|
||||
#define __RT305X_PCIREG_H__
|
||||
|
||||
#define RT305X_PCI_NIRQS 1
|
||||
#define RT305X_PCI_BASESLOT 0
|
||||
|
||||
#define RT305X_PCI_PCICFG 0x0000
|
||||
#define RT305X_PCI_PCIINT 0x0008
|
||||
#define RT305X_PCI_PCIENA 0x000C
|
||||
#define RT305X_PCI_CFGADDR 0x0020
|
||||
#define RT305X_PCI_CFGDATA 0x0024
|
||||
#define RT305X_PCI_MEMBASE 0x0028
|
||||
#define RT305X_PCI_IOBASE 0x002C
|
||||
#define RT305X_PCI_PHY0_CFG 0x0090
|
||||
|
||||
#define RT305X_PCI_PCIE0_BAR0SETUP 0x2010
|
||||
#define RT305X_PCI_PCIE0_BAR1SETUP 0x2014
|
||||
#define RT305X_PCI_PCIE0_IMBASEBAR0 0x2018
|
||||
#define RT305X_PCI_PCIE0_ID 0x2030
|
||||
#define RT305X_PCI_PCIE0_CLASS 0x2034
|
||||
#define RT305X_PCI_PCIE0_SUBID 0x2038
|
||||
#define RT305X_PCI_PCIE0_STATUS 0x2050
|
||||
#define RT305X_PCI_PCIE0_DLECR 0x2060
|
||||
#define RT305X_PCI_PCIE0_ECRC 0x2064
|
||||
|
||||
#define RT305X_PCIE0_IRQ 20
|
||||
#define RT305X_PCIE1_IRQ 21
|
||||
#define RT305X_PCIE2_IRQ 22
|
||||
|
||||
#define RT305X_PCI_INTR_PIN 2
|
||||
|
||||
#define PCI_MIN_IO_ALLOC 4
|
||||
#define PCI_MIN_MEM_ALLOC 16
|
||||
#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
|
||||
|
||||
#define RT_WRITE32(sc, off, val) \
|
||||
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
|
||||
#define RT_WRITE16(sc, off, val) \
|
||||
bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
|
||||
#define RT_WRITE8(sc, off, val) \
|
||||
bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
|
||||
#define RT_READ32(sc, off) \
|
||||
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (off))
|
||||
#define RT_READ16(sc, off) \
|
||||
bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (off))
|
||||
#define RT_READ8(sc, off) \
|
||||
bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (off))
|
||||
|
||||
#endif /* __RT305X_PCIREG_H__ */
|
||||
Loading…
Reference in New Issue
Block a user